diff --git a/SPECtestformatmodifier_z.txt b/SPECtestformatmodifier_z.txt new file mode 100644 index 000000000..eb43b2354 --- /dev/null +++ b/SPECtestformatmodifier_z.txt @@ -0,0 +1,4 @@ +The following line should contain a single '3': +3 +If it said anything else (such as 'zd') try compiling +with -DSPEC_CPU_NOZMODIFIER diff --git a/TAGE_SC_L/GemsFDTD/config.ini b/TAGE_SC_L/GemsFDTD/config.ini new file mode 100644 index 000000000..57cfa1a87 --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 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+eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + 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+eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList0 system.cpu.fuPool.FUList8.opList1 system.cpu.fuPool.FUList8.opList2 system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 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CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/GemsFDTD/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/GemsFDTD/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/GemsFDTD/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/GemsFDTD/config.json b/TAGE_SC_L/GemsFDTD/config.json new file mode 100644 index 000000000..5e1a4ff74 --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/GemsFDTD/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/GemsFDTD/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/GemsFDTD/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": 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"possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": 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"numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 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1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/GemsFDTD/fs/proc/cpuinfo b/TAGE_SC_L/GemsFDTD/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/GemsFDTD/fs/proc/stat b/TAGE_SC_L/GemsFDTD/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/online b/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/GemsFDTD/ref.log b/TAGE_SC_L/GemsFDTD/ref.log new file mode 100644 index 000000000..f40519fd2 --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/ref.log @@ -0,0 +1,5 @@ + Welcome to GemsFDTD + + EXECUTION HALTED ! (in Check_open) + Application could not open file yee.dat + The value of ios was: 2 diff --git a/TAGE_SC_L/GemsFDTD/stats.txt b/TAGE_SC_L/GemsFDTD/stats.txt new file mode 100644 index 000000000..0bd0d48d5 --- /dev/null +++ b/TAGE_SC_L/GemsFDTD/stats.txt @@ -0,0 +1,1357 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 61962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 72722 # Simulator instruction rate (inst/s) +host_mem_usage 855288 # Number of bytes of host memory used +host_op_rate 88771 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.40 # Real time elapsed on the host +host_tick_rate 153425768 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 29355 # Number of instructions simulated +sim_ops 35849 # Number of ops (including micro ops) simulated +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 61962500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.723205 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 4252 # Number of BTB hits +system.cpu.branchPred.BTBLookups 5542 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 10 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8981 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 497 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 457 # Number of indirect misses. +system.cpu.branchPred.lookups 12734 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2775 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 2242 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2728 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 2289 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 99 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 265 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 82 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 24 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 20 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 56 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 9 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 16 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 48 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 19 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 157 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 4 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 50 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 3609 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 603 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 184 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 27 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 43 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 61 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 14 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 358 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 24 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1041 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 131 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 10477 # number of cc regfile reads +system.cpu.cc_regfile_writes 10350 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 934 # The number of times a branch was mispredicted +system.cpu.commit.branches 6765 # Number of branches committed +system.cpu.commit.bw_lim_events 1464 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 48 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14283 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 29435 # Number of instructions committed +system.cpu.commit.committedOps 35929 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 47276 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.759984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.826531 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36313 76.81% 76.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3795 8.03% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1998 4.23% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1237 2.62% 91.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 892 1.89% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 730 1.54% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 432 0.91% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 415 0.88% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1464 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 47276 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 609 # Number of function calls committed. +system.cpu.commit.int_insts 32730 # Number of committed integer instructions. +system.cpu.commit.loads 5438 # Number of loads committed +system.cpu.commit.membars 24 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 24199 67.35% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 53 0.15% 67.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 6 0.02% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.07% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 32 0.09% 67.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.08% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 38 0.11% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 5438 15.14% 83.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6102 16.98% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 35929 # Class of committed instruction +system.cpu.commit.refs 11540 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 477 # Number of committed Vector instructions. +system.cpu.committedInsts 29355 # Number of Instructions Simulated +system.cpu.committedOps 35849 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.221632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.221632 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 15232 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 516 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4408 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 55880 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23119 # Number of cycles decode is idle +system.cpu.decode.RunCycles 9540 # Number of cycles decode is running +system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1797 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 778 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 12734 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7861 # Number of cache lines fetched +system.cpu.fetch.Cycles 20839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 901 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 55013 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2968 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.102755 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 5333 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.443918 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 49646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.316078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.623215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 37422 75.38% 75.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1043 2.10% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1301 2.62% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1176 2.37% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1493 3.01% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 985 1.98% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 951 1.92% 89.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 638 1.29% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4637 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 49646 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 74280 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1117 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 8135 # Number of branches executed +system.cpu.iew.exec_nop 169 # number of nop insts executed +system.cpu.iew.exec_rate 0.366243 # Inst execution rate +system.cpu.iew.exec_refs 14525 # number of memory reference insts executed +system.cpu.iew.exec_stores 6953 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2520 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 7866 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8014 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 50287 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 7572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 45387 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 734 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 752 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 105 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2428 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1912 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 897 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 38852 # num instructions consuming a value +system.cpu.iew.wb_count 43582 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.561155 # average fanout of values written-back +system.cpu.iew.wb_producers 21802 # num instructions producing a value +system.cpu.iew.wb_rate 0.351678 # insts written-back per cycle +system.cpu.iew.wb_sent 44447 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 50533 # number of integer regfile reads +system.cpu.int_regfile_writes 31002 # number of integer regfile writes +system.cpu.ipc 0.236875 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.236875 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 31303 67.04% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 54 0.12% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.01% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.07% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.09% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 36 0.08% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 45 0.10% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 7886 16.89% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7275 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 46692 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 660 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014135 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 201 30.45% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.30% 30.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.45% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 201 30.45% 61.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 253 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 46706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 142541 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 43022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 63464 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 50040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 46692 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 49646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.940499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 34591 69.68% 69.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3579 7.21% 76.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 3204 6.45% 83.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2742 5.52% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2133 4.30% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1590 3.20% 96.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1016 2.05% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 427 0.86% 99.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 364 0.73% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 49646 # Number of insts issued each cycle +system.cpu.iq.rate 0.376773 # Inst issue rate +system.cpu.iq.vec_alu_accesses 637 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1294 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 560 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 945 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 112 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 7866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8014 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 35114 # number of misc regfile reads +system.cpu.misc_regfile_writes 97 # number of misc regfile writes +system.cpu.numCycles 123926 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3665 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 33835 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 210 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 24047 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 128 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 76045 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 53101 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 49590 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 9354 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1484 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2164 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15755 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 59261 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9439 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 343 # count of serializing insts renamed +system.cpu.rename.skidInsts 3984 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 80 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 803 # Number of vector rename lookups +system.cpu.rob.rob_reads 95673 # The number of ROB reads +system.cpu.rob.rob_writes 102806 # The number of ROB writes +system.cpu.timesIdled 740 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 621 # number of vector regfile reads +system.cpu.vec_regfile_writes 183 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1306 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 648 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 2137 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1064 # Transaction distribution +system.membus.trans_dist::ReadExReq 178 # Transaction distribution +system.membus.trans_dist::ReadExResp 178 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1065 # Transaction distribution +system.membus.trans_dist::InvalidateReq 63 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1306 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1306 # Request fanout histogram +system.membus.reqLayer0.occupancy 1614000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 6586250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1243 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 50 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 543 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 54 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 182 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 182 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1029 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 216 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 63 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 63 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2599 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1026 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3625 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 100480 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 129152 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1490 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001342 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.036625 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1488 99.87% 99.87% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1490 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1661500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 628500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1540500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 144 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 183 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 144 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 183 # number of overall hits +system.l2.demand_misses::.cpu.inst 885 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 359 # number of demand (read+write) misses +system.l2.demand_misses::total 1244 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 885 # number of overall misses +system.l2.overall_misses::.cpu.data 359 # number of overall misses +system.l2.overall_misses::total 1244 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69107000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 30532500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 99639500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69107000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 30532500 # number of overall miss cycles +system.l2.overall_miss_latency::total 99639500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1029 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 398 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1427 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1029 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 398 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1427 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.860058 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.902010 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.871759 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.860058 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.902010 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.871759 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 885 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 359 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1244 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 885 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 359 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1244 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60277000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 26942001 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 87219001 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60277000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 26942001 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 87219001 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.871759 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.871759 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 50 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 50 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 543 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 543 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 543 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 543 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 4 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 4 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 178 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 178 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 63 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 63 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19015.873016 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19015.873016 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 674.522414 # Cycle average of tags in use +system.l2.tags.total_refs 2071 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1248 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.659455 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.805164 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 455.337647 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 217.379603 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013896 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006634 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.020585 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1248 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.038086 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 18336 # Number of tag accesses +system.l2.tags.data_accesses 18336 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56576 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 22976 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 79552 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 884 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 359 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1243 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 913068388 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 370804922 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1283873310 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 913068388 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 370804922 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1283873310 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 884.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 359.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000554500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2436 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1243 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1243 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 151 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 25 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 12775500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6215000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 36081750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10277.96 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29027.96 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 971 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.12 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1243 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 698 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 361 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 260 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 297.107692 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.423498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.377322 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 30.00% 30.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 65 25.00% 55.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45 17.31% 72.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 19 7.31% 79.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 6.15% 85.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 3.46% 89.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 1.92% 91.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 2.31% 93.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 6.54% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 260 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 79552 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 79552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1283.87 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1283.87 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.03 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 61929000 # Total gap between requests +system.mem_ctrls.avgGap 49822.20 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56576 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 22976 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 913068388.137986779213 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 370804922.332055687904 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 884 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 359 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23954000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 12127750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27097.29 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33782.03 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1185240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 607200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4976580 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 27790920 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 390720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 39253140 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 633.498326 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 824000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 59318500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 756840 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3898440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 27598260 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 552960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 37488480 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 605.018842 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1232500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 58910000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6542 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6542 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6542 # number of overall hits +system.cpu.icache.overall_hits::total 6542 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1319 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1319 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1319 # number of overall misses +system.cpu.icache.overall_misses::total 1319 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 91010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 91010500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7861 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.167790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.167790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.167790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.167790 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 543 # number of writebacks +system.cpu.icache.writebacks::total 543 # number of writebacks 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task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 16749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 16749 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 11600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 11622 # number of overall hits +system.cpu.dcache.overall_hits::total 11622 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1511 # number of overall misses +system.cpu.dcache.overall_misses::total 1511 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 98038926 # number of overall miss cycles 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number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 72346.492274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72346.492274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72339.434498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72339.434498 # average overall mshr miss latency +system.cpu.dcache.replacements 104 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 6518 # number of ReadReq hits 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296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 231.645691 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12141 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 461 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.336226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 231.645691 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 26849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 26849 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 61962500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/astar/config.ini b/TAGE_SC_L/astar/config.ini new file mode 100644 index 000000000..fc906c9b0 --- /dev/null +++ b/TAGE_SC_L/astar/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + 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+stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system 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+id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/exe/astar_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/473.astar/data/ref/input/rivers.cfg +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/exe/astar_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lake.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/astar/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/astar/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/astar/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/astar/config.json b/TAGE_SC_L/astar/config.json new file mode 100644 index 000000000..96c3003fe --- /dev/null +++ b/TAGE_SC_L/astar/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/astar/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/astar/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/astar/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": 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"system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.tol2bus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 4, + "writeback_clean": false, + "tags": { + "tag_latency": 2, + "replacement_policy": "system.cpu.dcache.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "SetAssociative", + "path": "system.cpu.dcache.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 32768 + }, + "system": "system", + "sequential_access": false, + "assoc": 2, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.cpu.dcache.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 32768 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": 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"possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/astar/fs/proc/cpuinfo b/TAGE_SC_L/astar/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/astar/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/astar/fs/proc/stat b/TAGE_SC_L/astar/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/astar/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/astar/fs/sys/devices/system/cpu/online b/TAGE_SC_L/astar/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/astar/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/astar/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/astar/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/astar/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/astar/lake.out b/TAGE_SC_L/astar/lake.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/astar/stats.txt b/TAGE_SC_L/astar/stats.txt new file mode 100644 index 000000000..55a607467 --- /dev/null +++ b/TAGE_SC_L/astar/stats.txt @@ -0,0 +1,1334 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 302249500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 128934 # Simulator instruction rate (inst/s) +host_mem_usage 852312 # Number of bytes of host memory used +host_op_rate 161660 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.76 # Real time elapsed on the host +host_tick_rate 38969162 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1253848 # Number of ops (including micro ops) simulated +sim_seconds 0.000302 # Number of seconds simulated +sim_ticks 302249500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.726888 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 65838 # Number of BTB hits +system.cpu.branchPred.BTBLookups 66687 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 940 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 137232 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 5 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 195 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 190 # Number of indirect misses. +system.cpu.branchPred.lookups 190641 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 106078 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 28445 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 106057 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 28466 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 49 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 11 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 4570 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3064 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 6082 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1508 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 3016 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 58 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 6 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 115674 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 434 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3066 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1530 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3035 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 6080 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1514 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1507 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1513 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 18188 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 11 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 14 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 15573 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 257457 # number of cc regfile reads +system.cpu.cc_regfile_writes 257394 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted +system.cpu.commit.branches 186765 # Number of branches committed +system.cpu.commit.bw_lim_events 94499 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 10029 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000029 # Number of instructions committed +system.cpu.commit.committedOps 1253875 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 544665 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.302103 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.085122 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 256502 47.09% 47.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 99545 18.28% 65.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16582 3.04% 68.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15860 2.91% 71.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26192 4.81% 76.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9331 1.71% 77.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16907 3.10% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9247 1.70% 82.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94499 17.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 544665 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 15355 # Number of function calls committed. +system.cpu.commit.int_insts 1159380 # Number of committed integer instructions. +system.cpu.commit.loads 199569 # Number of loads committed +system.cpu.commit.membars 46 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 805940 64.28% 64.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6086 0.49% 64.76% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 64.76% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 3024 0.24% 65.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 3030 0.24% 65.24% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 65.25% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 1 0.00% 65.25% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3027 0.24% 65.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 3030 0.24% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 18 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 16 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 2 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 15 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.73% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 199569 15.92% 81.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 230090 18.35% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1253875 # Class of committed instruction +system.cpu.commit.refs 429659 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 12432 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1253848 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.604499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.604499 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 311838 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 350 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 65976 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1267701 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 53723 # Number of cycles decode is idle +system.cpu.decode.RunCycles 155521 # Number of cycles decode is running +system.cpu.decode.SquashCycles 655 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1243 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 24577 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 190641 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 123192 # Number of cache lines fetched +system.cpu.fetch.Cycles 407883 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 629 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1017294 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1980 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.315370 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 137366 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 81416 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.682868 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 546314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.330413 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.189247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 312236 57.15% 57.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21834 4.00% 61.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28076 5.14% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24818 4.54% 70.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5336 0.98% 71.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29169 5.34% 77.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 20123 3.68% 80.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5006 0.92% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 99716 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 546314 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 58186 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 696 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 187807 # Number of branches executed +system.cpu.iew.exec_nop 53 # number of nop insts executed +system.cpu.iew.exec_rate 2.085166 # Inst execution rate +system.cpu.iew.exec_refs 431688 # number of memory reference insts executed +system.cpu.iew.exec_stores 230626 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1778 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 201333 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 231254 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1264033 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 201062 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1260483 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 136 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 655 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 148 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 59 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 131 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1764 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1153 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1250427 # num instructions consuming a value +system.cpu.iew.wb_count 1259445 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.561443 # average fanout of values written-back +system.cpu.iew.wb_producers 702044 # num instructions producing a value +system.cpu.iew.wb_rate 2.083449 # insts written-back per cycle +system.cpu.iew.wb_sent 1259831 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1492844 # number of integer regfile reads +system.cpu.int_regfile_writes 917683 # number of integer regfile writes +system.cpu.ipc 1.654263 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.654263 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 6 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 811022 64.30% 64.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6089 0.48% 64.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 64.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3024 0.24% 65.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3030 0.24% 65.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 65.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 1 0.00% 65.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3029 0.24% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 3032 0.24% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 20 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 23 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 2 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 65.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 201264 15.96% 81.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230791 18.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1261381 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 24689 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019573 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3199 12.96% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2 0.01% 12.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 12.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1 0.00% 12.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 11 0.04% 13.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 13.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 13.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6151 24.91% 37.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15322 62.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1273515 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3068803 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1246976 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1261467 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1263897 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1261381 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6406 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 546314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.308894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.621936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 228698 41.86% 41.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 50844 9.31% 51.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59460 10.88% 62.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 46862 8.58% 70.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30025 5.50% 76.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 41511 7.60% 83.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 33989 6.22% 89.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19958 3.65% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34967 6.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 546314 # Number of insts issued each cycle +system.cpu.iq.rate 2.086652 # Inst issue rate +system.cpu.iq.vec_alu_accesses 12549 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 25055 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 12469 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 12636 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 136 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3127 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 201333 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 231254 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 879286 # number of misc regfile reads +system.cpu.misc_regfile_writes 9273 # number of misc regfile writes +system.cpu.numCycles 604500 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 1939 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1187393 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 46 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 72400 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1882005 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1266201 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1199914 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 161399 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1045 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 655 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 31540 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 12467 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1499310 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 278381 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 18326 # count of serializing insts renamed +system.cpu.rename.skidInsts 155948 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 85 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 15638 # Number of vector rename lookups +system.cpu.rob.rob_reads 1713797 # The number of ROB reads +system.cpu.rob.rob_writes 2529518 # The number of ROB writes +system.cpu.timesIdled 533 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 15536 # number of vector regfile reads +system.cpu.vec_regfile_writes 9195 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 965 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1357 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 816 # Transaction distribution +system.membus.trans_dist::ReadExReq 139 # Transaction distribution +system.membus.trans_dist::ReadExResp 139 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 1920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1920 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 61120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 61120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 965 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 965 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 965 # Request fanout histogram +system.membus.reqLayer0.occupancy 1200500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 5059250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 879 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 303 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 9 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 140 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 140 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 765 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 10 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 10 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1833 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 553 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 2386 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 68352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 17280 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 85632 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1029 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000972 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.031174 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1028 99.90% 99.90% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1029 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 997500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 386000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1147500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 63 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 64 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 63 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 64 # number of overall hits +system.l2.demand_misses::.cpu.inst 702 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 253 # number of demand (read+write) misses +system.l2.demand_misses::total 955 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 702 # number of overall misses +system.l2.overall_misses::.cpu.data 253 # number of overall misses +system.l2.overall_misses::total 955 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 55600500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 21544500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 77145000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 55600500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 21544500 # number of overall miss cycles +system.l2.overall_miss_latency::total 77145000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 765 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 254 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1019 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 765 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 254 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1019 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.917647 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.996063 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.937193 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.917647 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.996063 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.937193 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79202.991453 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85156.126482 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80780.104712 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79202.991453 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85156.126482 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80780.104712 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 702 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 253 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 955 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 702 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 253 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 955 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 48580500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 19014500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 67595000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 48580500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 19014500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 67595000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.996063 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.937193 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.996063 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.937193 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75156.126482 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70780.104712 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75156.126482 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70780.104712 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 16 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 303 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 303 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 303 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 303 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 139 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 139 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 11261500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 11261500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 140 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 140 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.992857 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.992857 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 81017.985612 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 81017.985612 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 139 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 9871500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 9871500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.992857 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 71017.985612 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 71017.985612 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 63 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 63 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 702 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 55600500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 55600500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 765 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 765 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.917647 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.917647 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79202.991453 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79202.991453 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 702 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 702 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 48580500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 48580500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.917647 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69202.991453 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_misses::.cpu.data 114 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 114 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10283000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10283000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 90201.754386 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 90201.754386 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 114 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 114 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9143000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9143000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 80201.754386 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 80201.754386 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 191000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 191000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19100 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19100 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 889.241744 # Cycle average of tags in use +system.l2.tags.total_refs 1347 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 955 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.410471 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.cpu.inst 648.924584 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 240.317160 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.cpu.inst 0.019804 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.007334 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.027138 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.029144 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 11811 # Number of tag accesses +system.l2.tags.data_accesses 11811 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 44928 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 16192 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 61120 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 44928 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 702 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 253 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 955 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 148645407 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 53571635 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 202217043 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 148645407 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 148645407 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 148645407 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 53571635 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 202217043 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 702.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 253.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000566000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 1936 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 955 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 955 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 20 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 45 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 96 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 158 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.12 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10336000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 4775000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 28242250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10823.04 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29573.04 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 745 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.01 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 955 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 513 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 286 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see 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incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 291.047619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 182.955326 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 302.852290 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 65 30.95% 30.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 67 31.90% 62.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 24 11.43% 74.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 12 5.71% 80.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 3.81% 83.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 4.29% 88.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 1.43% 89.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.95% 90.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 20 9.52% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 210 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 61120 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 61120 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 202.22 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 202.22 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 1.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 45588000 # Total gap between requests +system.mem_ctrls.avgGap 47736.13 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 44928 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 16192 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 148645407.188432067633 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 53571635.354235492647 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 702 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 253 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 19686250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8556000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28043.09 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33818.18 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.01 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 406065 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 3291540 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 23356320.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 24254640 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 95639040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 147711585 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 488.707459 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 248453500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 9880000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 43916000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 735420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 390885 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3527160 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 23356320.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 24667890 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 95291040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 147968715 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 489.558180 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 247533000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 9880000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 44836500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 122236 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 122236 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 122236 # number of overall hits +system.cpu.icache.overall_hits::total 122236 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 955 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 955 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 955 # number of overall misses +system.cpu.icache.overall_misses::total 955 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 69195999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69195999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 69195999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69195999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 123191 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 123191 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 123191 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 123191 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.007752 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007752 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.007752 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007752 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 72456.543455 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72456.543455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 72456.543455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72456.543455 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 939 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 303 # number of writebacks +system.cpu.icache.writebacks::total 303 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 190 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 190 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 190 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 765 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 765 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 57479999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57479999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 57479999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57479999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.006210 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006210 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.006210 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006210 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 75137.253595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75137.253595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 75137.253595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75137.253595 # average overall mshr miss latency +system.cpu.icache.replacements 303 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 122236 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 122236 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 955 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 955 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 69195999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69195999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 123191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 123191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.007752 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007752 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 72456.543455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72456.543455 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 190 # number of ReadReq MSHR hits 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+system.cpu.icache.tags.tagsinuse 434.599009 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 123001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 765 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 160.785621 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 434.599009 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.848826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.848826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 462 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 247147 # Number of tag accesses +system.cpu.icache.tags.data_accesses 247147 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 429766 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 429766 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 429774 # number of overall hits +system.cpu.dcache.overall_hits::total 429774 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 871 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 871 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 873 # number of overall misses +system.cpu.dcache.overall_misses::total 873 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 61890955 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 61890955 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 61890955 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 61890955 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 430637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 430637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 430647 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 430647 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.002023 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002023 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.002027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002027 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 71057.353617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71057.353617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 70894.564719 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70894.564719 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2750 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.354839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 609 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 609 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 609 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 609 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 264 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 22065995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22065995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 22250495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22250495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.000608 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000608 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.000613 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000613 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 84221.354962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84221.354962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 84282.178030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84282.178030 # average overall mshr miss latency +system.cpu.dcache.replacements 25 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 200355 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200355 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 238 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 19406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 200593 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 200593 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 81537.815126 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81537.815126 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000558 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000558 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 91714.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91714.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 229411 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 229411 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 626 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 626 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 42262457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42262457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 230037 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 230037 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.002721 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002721 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67511.912141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67511.912141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 11578497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11578497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.000622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000622 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 80968.510490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80968.510490 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 46 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 46 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 46 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 46 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 228.156978 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 430139 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 264 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 1629.314394 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 228.156978 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.445619 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.445619 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 239 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 861760 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 861760 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 302249500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 302249500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/bwaves/config.ini b/TAGE_SC_L/bwaves/config.ini new file mode 100644 index 000000000..5e04e0e16 --- /dev/null +++ b/TAGE_SC_L/bwaves/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + 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+pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/410.bwaves/exe/bwaves_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/410.bwaves/exe/bwaves_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/bwaves/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/bwaves/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/bwaves/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/bwaves/config.json b/TAGE_SC_L/bwaves/config.json new file mode 100644 index 000000000..ee7c8fe94 --- /dev/null +++ b/TAGE_SC_L/bwaves/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/bwaves/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/bwaves/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/bwaves/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": 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"possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": 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"UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.tol2bus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 4, + "writeback_clean": false, + "tags": { + "tag_latency": 2, + "replacement_policy": "system.cpu.dcache.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "SetAssociative", + "path": "system.cpu.dcache.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 32768 + }, + "system": "system", + "sequential_access": false, + "assoc": 2, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.cpu.dcache.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 32768 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/bwaves/fs/proc/cpuinfo b/TAGE_SC_L/bwaves/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/bwaves/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/bwaves/fs/proc/stat b/TAGE_SC_L/bwaves/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/bwaves/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/online b/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/bwaves/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/bwaves/stats.txt b/TAGE_SC_L/bwaves/stats.txt new file mode 100644 index 000000000..5ffb0395c --- /dev/null +++ b/TAGE_SC_L/bwaves/stats.txt @@ -0,0 +1,1360 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 339479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 142044 # Simulator instruction rate (inst/s) +host_mem_usage 854244 # Number of bytes of host memory used +host_op_rate 159409 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.04 # Real time elapsed on the host +host_tick_rate 48219488 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000003 # Number of instructions simulated +sim_ops 1122282 # Number of ops (including micro ops) simulated +sim_seconds 0.000339 # Number of seconds simulated +sim_ticks 339479500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.085163 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 128238 # Number of BTB hits +system.cpu.branchPred.BTBLookups 129422 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 2213 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197461 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 8376 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 8771 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 395 # Number of indirect misses. +system.cpu.branchPred.lookups 300048 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 123319 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 63823 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 117015 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 70127 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 142 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 33 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 2506 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1560 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 515 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 240 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1402 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 94 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 212 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 279 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 122 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 78 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 57 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 521 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1107 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1138 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1341 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1652 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1386 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1151 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 556 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 45 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 523 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 170 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 250 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 169061 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 597 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 136 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1190 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1566 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 363 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 661 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 221 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1421 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 112 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 206 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 128 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 378 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 55 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1100 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 538 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1130 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 224 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1510 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 2162 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1829 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1301 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 121 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 15258 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 107 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 575 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 38249 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 107 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 511809 # number of cc regfile reads +system.cpu.cc_regfile_writes 403824 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 1772 # The number of times a branch was mispredicted +system.cpu.commit.branches 284274 # Number of branches committed +system.cpu.commit.bw_lim_events 67742 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 50016 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000157 # Number of instructions committed +system.cpu.commit.committedOps 1122436 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 606998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.849159 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.730137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 327929 54.02% 54.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75665 12.47% 66.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 39742 6.55% 73.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28495 4.69% 77.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23646 3.90% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22522 3.71% 85.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16127 2.66% 87.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5130 0.85% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67742 11.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 606998 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 37015 # Number of function calls committed. +system.cpu.commit.int_insts 967650 # Number of committed integer instructions. +system.cpu.commit.loads 117873 # Number of loads committed +system.cpu.commit.membars 4 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 11 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 911480 81.21% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 67 0.01% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 81.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 35 0.00% 81.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 81.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 42 0.00% 81.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 45 0.00% 81.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 81.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 49 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 81.23% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 117873 10.50% 91.73% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 92831 8.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1122436 # Class of committed instruction +system.cpu.commit.refs 210704 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 748 # Number of committed Vector instructions. +system.cpu.committedInsts 1000003 # Number of Instructions Simulated +system.cpu.committedOps 1122282 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.678958 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.678958 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 142162 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 453 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 128088 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1185663 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 212533 # Number of cycles decode is idle +system.cpu.decode.RunCycles 250424 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1847 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1532 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 7319 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 300048 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 213259 # Number of cache lines fetched +system.cpu.fetch.Cycles 382197 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 947 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1065306 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4576 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.441923 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 229747 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 174863 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.569026 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 614285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.949395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 344451 56.07% 56.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 17002 2.77% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 54538 8.88% 67.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 50671 8.25% 75.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 15880 2.59% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 41337 6.73% 85.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28897 4.70% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16266 2.65% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 45243 7.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 614285 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 64675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2093 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 290877 # Number of branches executed +system.cpu.iew.exec_nop 234 # number of nop insts executed +system.cpu.iew.exec_rate 1.718438 # Inst execution rate +system.cpu.iew.exec_refs 226495 # number of memory reference insts executed +system.cpu.iew.exec_stores 96201 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 69958 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124124 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 254 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 98932 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1172821 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 130294 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3539 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1166751 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 313 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2552 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1847 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3611 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 125 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2307 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 7751 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 6251 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 6101 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1266 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1121362 # num instructions consuming a value +system.cpu.iew.wb_count 1156597 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.493114 # average fanout of values written-back +system.cpu.iew.wb_producers 552959 # num instructions producing a value +system.cpu.iew.wb_rate 1.703483 # insts written-back per cycle +system.cpu.iew.wb_sent 1157753 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1292601 # number of integer regfile reads +system.cpu.int_regfile_writes 845114 # number of integer regfile writes +system.cpu.ipc 1.472845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.472845 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 13 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 941752 80.47% 80.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 68 0.01% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 45 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 56 0.00% 80.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 53 0.00% 80.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 131270 11.22% 91.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 96977 8.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1170295 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5696 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004867 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4303 75.54% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.04% 75.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.04% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 862 15.13% 90.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 527 9.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1175065 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2958955 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1155773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1221829 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1172539 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1170295 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 218 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 23362 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 614285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.905134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.963457 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 195082 31.76% 31.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 126243 20.55% 52.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 96946 15.78% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 82283 13.39% 81.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30589 4.98% 86.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 41245 6.71% 93.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 23946 3.90% 97.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12554 2.04% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5397 0.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 614285 # Number of insts issued each cycle +system.cpu.iq.rate 1.723658 # Inst issue rate +system.cpu.iq.vec_alu_accesses 913 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1829 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 824 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1080 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 11040 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25122 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124124 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 98932 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 787214 # number of misc regfile reads +system.cpu.misc_regfile_writes 17 # number of misc regfile writes +system.cpu.numCycles 678960 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 103480 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1214169 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 16798 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 215486 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1767 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1559 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1833131 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1179521 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1270510 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 253088 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7057 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1847 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 29707 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 56313 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1308165 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 10677 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 291 # count of serializing insts renamed +system.cpu.rename.skidInsts 40905 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 50 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1032 # Number of vector rename lookups +system.cpu.rob.rob_reads 1711006 # The number of ROB reads +system.cpu.rob.rob_writes 2352238 # The number of ROB writes +system.cpu.timesIdled 621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 918 # number of vector regfile reads +system.cpu.vec_regfile_writes 239 # number of vector regfile writes +system.cpu.workload.numSyscalls 37 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2465 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 6021 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 13019 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1804 # Transaction distribution +system.membus.trans_dist::ReadExReq 540 # Transaction distribution +system.membus.trans_dist::ReadExResp 540 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1804 # Transaction distribution +system.membus.trans_dist::InvalidateReq 121 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 4809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4809 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 150016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 150016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2465 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2465 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2465 # Request fanout histogram +system.membus.reqLayer0.occupancy 2906500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 12369500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 6316 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1471 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 372 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 4178 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 561 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 561 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 837 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 5479 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 121 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 121 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2046 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 17971 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 20017 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 77376 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 480704 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 558080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6998 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000143 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.011954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6997 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6998 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8352500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 9120500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1255500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 39 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4494 # number of demand (read+write) hits +system.l2.demand_hits::total 4533 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 39 # number of overall hits +system.l2.overall_hits::.cpu.data 4494 # number of overall hits +system.l2.overall_hits::total 4533 # number of overall hits +system.l2.demand_misses::.cpu.inst 798 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1546 # number of demand (read+write) misses +system.l2.demand_misses::total 2344 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 798 # number of overall misses +system.l2.overall_misses::.cpu.data 1546 # number of overall misses +system.l2.overall_misses::total 2344 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61922500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 117258500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 179181000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61922500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 117258500 # number of overall miss cycles +system.l2.overall_miss_latency::total 179181000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 837 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 6040 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6877 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 837 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 6040 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6877 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.953405 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.255960 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.340846 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.953405 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.255960 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.340846 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77597.117794 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75846.377749 # average overall miss latency +system.l2.demand_avg_miss_latency::total 76442.406143 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77597.117794 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75846.377749 # average overall miss latency +system.l2.overall_avg_miss_latency::total 76442.406143 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 798 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1546 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2344 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 798 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1546 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2344 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53942500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 101798500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 155741000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53942500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 101798500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 155741000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.953405 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.255960 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.340846 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.953405 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.255960 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.340846 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67597.117794 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65846.377749 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 66442.406143 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67597.117794 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65846.377749 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 66442.406143 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1471 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1471 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1471 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1471 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 372 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 372 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 372 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 372 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 21 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 21 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 540 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 540 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 41602500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 41602500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 561 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 561 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.962567 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.962567 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77041.666667 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77041.666667 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 540 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 540 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 36202500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 36202500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.962567 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.962567 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67041.666667 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67041.666667 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 39 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 39 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 798 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 798 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61922500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61922500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 837 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 837 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.953405 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.953405 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77597.117794 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77597.117794 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 798 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 798 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53942500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53942500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.953405 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.953405 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67597.117794 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67597.117794 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 4473 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 4473 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1006 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1006 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 75656000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 75656000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 5479 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 5479 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.183610 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.183610 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 75204.771372 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 75204.771372 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1006 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1006 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 65596000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 65596000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.183610 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.183610 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 65204.771372 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 65204.771372 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 121 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 121 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 121 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 121 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 121 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 121 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2304000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2304000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19041.322314 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19041.322314 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1966.253700 # Cycle average of tags in use +system.l2.tags.total_refs 12897 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2465 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 5.232049 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 96.320963 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 721.870685 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1148.062052 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.002939 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.022030 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.035036 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.060005 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2465 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2463 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.075226 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 106609 # Number of tag accesses +system.l2.tags.data_accesses 106609 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 51072 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 98944 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 150016 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 51072 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 51072 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 798 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1546 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2344 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 150442074 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 291457953 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 441900026 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 150442074 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 150442074 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 150442074 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 291457953 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 441900026 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 798.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1546.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000572000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4730 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2344 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2344 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 148 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 275 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 278 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 227 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 233 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 230 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 76 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 38 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15584500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 11720000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 59534500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6648.68 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 25398.68 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2021 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.22 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2344 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1781 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 396 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 124 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 323 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 464.445820 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 289.149635 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 384.954042 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 71 21.98% 21.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 69 21.36% 43.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 24 7.43% 50.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26 8.05% 58.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 25 7.74% 66.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.72% 70.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.79% 73.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.55% 74.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 82 25.39% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 323 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 150016 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 150016 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 441.90 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 441.90 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.45 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.45 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 275660500 # Total gap between requests +system.mem_ctrls.avgGap 117602.60 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 51072 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 98944 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 150442073.821836054325 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 291457952.542053341866 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 798 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1546 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21092500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 38442000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26431.70 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24865.46 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.22 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 742560 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 394680 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4833780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 39948450 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 96719520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 169068510 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 498.022738 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 250987000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 77312500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1563660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 831105 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 11902380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 89839410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 54706080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 185272155 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 545.753587 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 141171000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 187128500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 212178 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 212178 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 212178 # number of overall hits +system.cpu.icache.overall_hits::total 212178 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1080 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1080 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1080 # number of overall misses +system.cpu.icache.overall_misses::total 1080 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 79565499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 79565499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 79565499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 79565499 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 213258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 213258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 213258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 213258 # number of overall (read+write) accesses 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+system.cpu.dcache.WriteReq_accesses::.cpu.data 92709 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 92709 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.027948 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027948 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 55046.101891 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55046.101891 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 569 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 569 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 43008989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 43008989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.006137 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006137 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 75586.975395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75586.975395 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 113 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 113 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3611936 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3611936 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 120 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 120 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.941667 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.941667 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31964.035398 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31964.035398 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 113 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 113 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3498936 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3498936 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.941667 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.941667 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30964.035398 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30964.035398 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 457.484501 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 204603 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6161 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.209382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 457.484501 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.893524 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.893524 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 431619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 431619 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 339479500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 339479500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/bzip2/config.ini b/TAGE_SC_L/bzip2/config.ini new file mode 100644 index 000000000..b64e39095 --- /dev/null +++ b/TAGE_SC_L/bzip2/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc 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+clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2/data/ref/input/input.source 1 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=input.source.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 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+use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/bzip2/config.json b/TAGE_SC_L/bzip2/config.json new file mode 100644 index 000000000..5860f2bd0 --- /dev/null +++ b/TAGE_SC_L/bzip2/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": 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"path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/bzip2/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/bzip2/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/bzip2/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": 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"numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + 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"clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/bzip2/fs/proc/cpuinfo b/TAGE_SC_L/bzip2/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/bzip2/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/bzip2/fs/proc/stat b/TAGE_SC_L/bzip2/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/bzip2/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/online b/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/bzip2/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/bzip2/input.source.out b/TAGE_SC_L/bzip2/input.source.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/bzip2/stats.txt b/TAGE_SC_L/bzip2/stats.txt new file mode 100644 index 000000000..909d58cbb --- /dev/null +++ b/TAGE_SC_L/bzip2/stats.txt @@ -0,0 +1,1385 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 378669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 98361 # Simulator instruction rate (inst/s) +host_mem_usage 850764 # Number of bytes of host memory used +host_op_rate 103606 # Simulator op (including micro ops) rate (op/s) +host_seconds 10.17 # Real time elapsed on the host +host_tick_rate 37245660 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1053339 # Number of ops (including micro ops) simulated +sim_seconds 0.000379 # Number of seconds simulated +sim_ticks 378669000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.503404 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115614 # Number of BTB hits +system.cpu.branchPred.BTBLookups 116191 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 2464 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 165497 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 7 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 226 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 219 # Number of indirect misses. +system.cpu.branchPred.lookups 215070 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95597 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 25234 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89459 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 31372 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 77 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 17 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1398 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3995 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1548 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2699 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 4225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 691 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1062 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1543 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1073 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1096 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1741 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2997 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1489 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 3809 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2871 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1179 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1383 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 91 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 510 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 72520 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 390 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1150 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 613 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3333 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 828 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5300 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1929 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4449 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 886 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1064 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 936 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 872 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1487 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1877 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1646 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 4123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 2434 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2290 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1615 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 44496 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 359 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1004 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1255 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 58 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 313770 # number of cc regfile reads +system.cpu.cc_regfile_writes 314274 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2236 # The number of times a branch was mispredicted +system.cpu.commit.branches 166034 # Number of branches committed +system.cpu.commit.bw_lim_events 89784 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 186372 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000753 # Number of instructions committed +system.cpu.commit.committedOps 1054092 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 689773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.528172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.731295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417532 60.53% 60.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116341 16.87% 77.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 28634 4.15% 81.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 17254 2.50% 84.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4031 0.58% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6864 1.00% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5326 0.77% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4007 0.58% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89784 13.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 689773 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 949 # Number of function calls committed. +system.cpu.commit.int_insts 932693 # Number of committed integer instructions. +system.cpu.commit.loads 381890 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 9 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 499972 47.43% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 23 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 29 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 34 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 36 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 26 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 381890 36.23% 83.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 172070 16.32% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1054092 # Class of committed instruction +system.cpu.commit.refs 553960 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 224 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1053339 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.757339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.757339 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 360461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 238 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 107076 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1267054 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 119405 # Number of cycles decode is idle +system.cpu.decode.RunCycles 192717 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3090 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 38933 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 215070 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157254 # Number of cache lines fetched +system.cpu.fetch.Cycles 542149 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1264248 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6636 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.283981 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 169064 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 116876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.669329 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 714606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.851436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.916258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 423481 59.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 93221 13.05% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14864 2.08% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3790 0.53% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24832 3.47% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40621 5.68% 84.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2761 0.39% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18559 2.60% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 92477 12.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 714606 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2409 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 196664 # Number of branches executed +system.cpu.iew.exec_nop 1021 # number of nop insts executed +system.cpu.iew.exec_rate 1.740594 # Inst execution rate +system.cpu.iew.exec_refs 722788 # number of memory reference insts executed +system.cpu.iew.exec_stores 202589 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 32308 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 426666 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 208592 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1244237 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 520199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1318220 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 23397 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3090 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 22831 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2201 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 114 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 72 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 57119 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 44776 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 36521 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 72 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1520 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 889 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1296071 # num instructions consuming a value +system.cpu.iew.wb_count 1190532 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.595900 # average fanout of values written-back +system.cpu.iew.wb_producers 772329 # num instructions producing a value +system.cpu.iew.wb_rate 1.571994 # insts written-back per cycle +system.cpu.iew.wb_sent 1216310 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1585569 # number of integer regfile reads +system.cpu.int_regfile_writes 864051 # number of integer regfile writes +system.cpu.ipc 1.320413 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.320413 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 596296 45.14% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 26 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 38 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 40 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 28 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 521557 39.48% 84.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 203026 15.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1321063 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 25708 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019460 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1956 7.61% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22214 86.41% 94.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1533 5.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1346476 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3382155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1190281 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1432674 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1243135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1321063 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 189873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 300 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 119405 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 714606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.848659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.064894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 293888 41.13% 41.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78022 10.92% 52.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 110896 15.52% 67.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 75702 10.59% 78.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 71454 10.00% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35453 4.96% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22686 3.17% 96.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17094 2.39% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9411 1.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 714606 # Number of insts issued each cycle +system.cpu.iq.rate 1.744348 # Inst issue rate +system.cpu.iq.vec_alu_accesses 285 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 585 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 251 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 478 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 106597 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65049 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 426666 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 208592 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1050401 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 757339 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 82529 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 994060 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 9884 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 138535 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 71021 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1546 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1838328 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1257405 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1218260 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 211199 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 176346 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3090 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 269320 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 224182 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1510334 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9933 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 206 # count of serializing insts renamed +system.cpu.rename.skidInsts 227667 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 486 # Number of vector rename lookups +system.cpu.rob.rob_reads 1830001 # The number of ROB reads +system.cpu.rob.rob_writes 2505786 # The number of ROB writes +system.cpu.timesIdled 374 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 333 # number of vector regfile reads +system.cpu.vec_regfile_writes 167 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1159 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6744 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4866 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 16 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10619 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 16 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2017 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1151 # Transaction distribution +system.membus.trans_dist::CleanEvict 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 3561 # Transaction distribution +system.membus.trans_dist::ReadExResp 3561 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2017 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 5585 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5585 # Request fanout histogram +system.membus.reqLayer0.occupancy 12181000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 28800250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2150 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4546 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 142 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1353 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 517 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1633 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 8 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 8 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1176 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15196 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16372 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 551872 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 594048 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1175 # Total snoops (count) +system.tol2bus.snoopTraffic 73664 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6928 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002454 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.049479 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6911 99.75% 99.75% # Request fanout histogram +system.tol2bus.snoop_fanout::1 17 0.25% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6928 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8846500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 7846000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 775500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 9 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 158 # number of demand (read+write) hits +system.l2.demand_hits::total 167 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 9 # number of overall hits +system.l2.overall_hits::.cpu.data 158 # number of overall hits +system.l2.overall_hits::total 167 # number of overall hits +system.l2.demand_misses::.cpu.inst 508 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5070 # number of demand (read+write) misses +system.l2.demand_misses::total 5578 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 508 # number of overall misses +system.l2.overall_misses::.cpu.data 5070 # number of overall misses +system.l2.overall_misses::total 5578 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40426500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 445531000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 485957500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40426500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 445531000 # number of overall miss cycles +system.l2.overall_miss_latency::total 485957500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 517 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5228 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5745 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 517 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5228 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5745 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.982592 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.969778 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.970931 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.982592 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.969778 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.970931 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.demand_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.overall_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1151 # number of writebacks +system.l2.writebacks::total 1151 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 508 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5070 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 5578 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 508 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5070 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 5578 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35346500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 394831000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 430177500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35346500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 394831000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 430177500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.970931 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.970931 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.replacements 1175 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 142 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 142 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 142 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 142 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 34 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 34 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3561 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3561 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3219.497523 # Cycle average of tags in use +system.l2.tags.total_refs 10611 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 5590 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.898211 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 7.025790 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 423.809713 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2788.662020 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000214 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.012934 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.085103 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.098251 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 4119 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.134705 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 90534 # Number of tag accesses +system.l2.tags.data_accesses 90534 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32512 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 324480 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 356992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 73664 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 73664 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 508 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5070 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 5578 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1151 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1151 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 85858626 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 856896128 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 942754754 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 194534013 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 85858626 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 856896128 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1137288767 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1151.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 508.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5070.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000326398500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 70 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 70 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 11431 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 1054 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 5578 # Number of read requests accepted +system.mem_ctrls.writeReqs 1151 # Number of write requests accepted +system.mem_ctrls.readBursts 5578 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1151 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 353 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 445 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 432 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 309 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 285 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 70 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 71 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 65 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 20.52 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 94535750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 27890000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 199123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16947.97 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 35697.97 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4807 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 945 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.18 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.10 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 5578 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1151 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1928 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1431 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1215 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 984 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 129 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 138 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 945 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 453.079365 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 384.495920 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 199.503629 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 8.25% 8.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 87 9.21% 17.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48 5.08% 22.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 4.02% 26.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 630 66.67% 93.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.95% 94.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 20 2.12% 96.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.21% 96.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 33 3.49% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 945 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 70 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 76.500000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 21.987624 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.513517 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 64 91.43% 91.43% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-255 1 1.43% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::256-383 4 5.71% 98.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2560-2687 1 1.43% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 70 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 70 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 70 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 70 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 356992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 71680 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 356992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 73664 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 942.75 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 189.29 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 942.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 194.53 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.84 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 7.37 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 378545500 # Total gap between requests +system.mem_ctrls.avgGap 56255.83 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 324480 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 71680 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 85858625.871143400669 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 856896128.280899643898 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 189294608.219843715429 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 508 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5070 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1151 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14431750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 184691500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 3158337250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28408.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 36428.30 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 2743994.14 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 85.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3127320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1658415 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 20149080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 2949300 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 165006450 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 6456480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 228849765 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 604.353050 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 15482250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 350706750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3627120 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1927860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 19677840 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 2897100 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 77622600 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 80042880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 215298120 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 568.565475 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 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MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 331352977 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 399.938493 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 89.770053 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 399.938493 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 174 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 952628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 952628 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 378669000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/cactusADM/benchADM.out b/TAGE_SC_L/cactusADM/benchADM.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/cactusADM/config.ini b/TAGE_SC_L/cactusADM/config.ini new file mode 100644 index 000000000..dc584ae1b --- /dev/null +++ b/TAGE_SC_L/cactusADM/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] 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+clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//data/ref/input/benchADM.par +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=benchADM.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/cactusADM/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/cactusADM/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/cactusADM/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/cactusADM/config.json b/TAGE_SC_L/cactusADM/config.json new file mode 100644 index 000000000..a0b2fcfe2 --- /dev/null +++ b/TAGE_SC_L/cactusADM/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/cactusADM/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/cactusADM/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/cactusADM/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + 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100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/cactusADM/fs/proc/cpuinfo b/TAGE_SC_L/cactusADM/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/cactusADM/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/cactusADM/fs/proc/stat b/TAGE_SC_L/cactusADM/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/cactusADM/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/online b/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/cactusADM/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/cactusADM/stats.txt b/TAGE_SC_L/cactusADM/stats.txt new file mode 100644 index 000000000..8d5c11a13 --- /dev/null +++ b/TAGE_SC_L/cactusADM/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 468934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 105725 # Simulator instruction rate (inst/s) +host_mem_usage 857928 # Number of bytes of host memory used +host_op_rate 117927 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.46 # Real time elapsed on the host +host_tick_rate 49577057 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1115434 # Number of ops (including micro ops) simulated +sim_seconds 0.000469 # Number of seconds simulated +sim_ticks 468934500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.262346 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 141471 # Number of BTB hits +system.cpu.branchPred.BTBLookups 145453 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 9391 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 220443 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3812 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 4741 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 929 # Number of indirect misses. +system.cpu.branchPred.lookups 302124 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95777 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 77037 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 92105 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80709 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 741 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 220 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 20202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1973 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 864 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1733 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3428 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1457 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 3210 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3917 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 4292 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 4162 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 2969 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1781 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 638 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1316 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 3060 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 386 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 314 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 142 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1900 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 617 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 883 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 108110 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2099 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3520 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4793 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1956 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1090 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4841 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 4720 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2582 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 3607 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 3667 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 4716 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4073 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1191 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 2928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 887 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4328 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 515 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 637 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 510 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 348 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 54309 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 445 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1757 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 30296 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 519 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 359643 # number of cc regfile reads +system.cpu.cc_regfile_writes 343424 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 8332 # The number of times a branch was mispredicted +system.cpu.commit.branches 231894 # Number of branches committed +system.cpu.commit.bw_lim_events 61305 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 150260 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001506 # Number of instructions committed +system.cpu.commit.committedOps 1116940 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 825652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.352798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.277638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 431090 52.21% 52.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 199057 24.11% 76.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 65640 7.95% 84.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25941 3.14% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18585 2.25% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7816 0.95% 90.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8606 1.04% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7612 0.92% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61305 7.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825652 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 22009 # Number of function calls committed. +system.cpu.commit.int_insts 1003889 # Number of committed integer instructions. +system.cpu.commit.loads 188126 # Number of loads committed +system.cpu.commit.membars 234 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 8 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 793381 71.03% 71.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 444 0.04% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 14 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 20 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 54 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 61 0.01% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 188126 16.84% 87.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 134785 12.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1116940 # Class of committed instruction +system.cpu.commit.refs 322911 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1515 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1115434 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.937870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.937870 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 351151 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1084 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131130 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1328223 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 235007 # Number of cycles decode is idle +system.cpu.decode.RunCycles 224796 # Number of cycles decode is running +system.cpu.decode.SquashCycles 8407 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4080 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 29047 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 302124 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 222644 # Number of cache lines fetched +system.cpu.fetch.Cycles 535575 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1285656 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18932 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.322138 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 303270 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 175579 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.370825 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 848408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.699079 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 525019 61.88% 61.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42918 5.06% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 73846 8.70% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28765 3.39% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26350 3.11% 82.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30088 3.55% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28164 3.32% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8804 1.04% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 84454 9.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 848408 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 89462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9865 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 251794 # Number of branches executed +system.cpu.iew.exec_nop 1869 # number of nop insts executed +system.cpu.iew.exec_rate 1.303190 # Inst execution rate +system.cpu.iew.exec_refs 355366 # number of memory reference insts executed +system.cpu.iew.exec_stores 146931 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 16550 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 213838 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 154189 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1267807 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 208435 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1222223 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 4213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8407 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4294 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2777 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 50 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 62 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25707 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 19402 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 62 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 6197 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3668 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1106565 # num instructions consuming a value +system.cpu.iew.wb_count 1213951 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.582876 # average fanout of values written-back +system.cpu.iew.wb_producers 644990 # num instructions producing a value +system.cpu.iew.wb_rate 1.294370 # insts written-back per cycle +system.cpu.iew.wb_sent 1218084 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1420776 # number of integer regfile reads +system.cpu.int_regfile_writes 874576 # number of integer regfile writes +system.cpu.ipc 1.066246 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.066246 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 871958 70.78% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480 0.04% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 14 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 58 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 18 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 68 0.01% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 210407 17.08% 87.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 148868 12.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1231948 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14526 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011791 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4852 33.40% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 33.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4991 34.36% 67.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4678 32.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1244743 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3323953 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1212381 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1414639 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1265632 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1231948 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150480 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 495 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 78863 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 848408 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 393727 46.41% 46.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150412 17.73% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 105051 12.38% 76.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72755 8.58% 85.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52873 6.23% 91.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32913 3.88% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 19751 2.33% 97.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8802 1.04% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12124 1.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 848408 # Number of insts issued each cycle +system.cpu.iq.rate 1.313559 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1722 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3369 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1570 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1837 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 5612 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9134 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 213838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 154189 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1000136 # number of misc regfile reads +system.cpu.misc_regfile_writes 957 # number of misc regfile writes +system.cpu.numCycles 937870 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 21506 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1121395 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 249451 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 444 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1970254 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1295032 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1298125 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239899 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5945 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 8407 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 30468 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 176678 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1507674 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 298677 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 18843 # count of serializing insts renamed +system.cpu.rename.skidInsts 135698 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 311 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1703 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031157 # The number of ROB reads +system.cpu.rob.rob_writes 2557380 # The number of ROB writes +system.cpu.timesIdled 2383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1549 # number of vector regfile reads +system.cpu.vec_regfile_writes 238 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2163 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4766 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10513 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1294 # Transaction distribution +system.membus.trans_dist::ReadExReq 793 # Transaction distribution +system.membus.trans_dist::ReadExResp 793 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1294 # Transaction distribution +system.membus.trans_dist::InvalidateReq 76 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2163 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2163 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2163 # Request fanout histogram +system.membus.reqLayer0.occupancy 2694500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 11077500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4801 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 781 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 3742 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 243 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 868 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 868 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 4213 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 588 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 78 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 78 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 12168 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4092 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16260 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 509120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 143168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 652288 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5747 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000174 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013191 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5746 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5747 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9779500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2223499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 6319500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 3199 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 383 # number of demand (read+write) hits +system.l2.demand_hits::total 3582 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 3199 # number of overall hits +system.l2.overall_hits::.cpu.data 383 # number of overall hits +system.l2.overall_hits::total 3582 # number of overall hits +system.l2.demand_misses::.cpu.inst 1014 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1073 # number of demand (read+write) misses +system.l2.demand_misses::total 2087 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1014 # number of overall misses +system.l2.overall_misses::.cpu.data 1073 # number of overall misses +system.l2.overall_misses::total 2087 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 79654500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 85698500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 165353000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 79654500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 85698500 # number of overall miss cycles +system.l2.overall_miss_latency::total 165353000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 4213 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1456 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5669 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 4213 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1456 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5669 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.240684 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.736951 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.368143 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.240684 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.736951 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.368143 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1014 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1073 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2087 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1014 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1073 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2087 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 69514500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 74968500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 144483000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 69514500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 74968500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 144483000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.368143 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.368143 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 781 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 781 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 3742 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 3742 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 3742 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 3742 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 75 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 75 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 793 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 793 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 76 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 76 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18907.894737 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18907.894737 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1545.070072 # Cycle average of tags in use +system.l2.tags.total_refs 10436 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2145 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 4.865268 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 34.455603 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 823.783092 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 686.831377 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001052 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.025140 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.020960 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047152 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1854 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.065399 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 86241 # Number of tag accesses +system.l2.tags.data_accesses 86241 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 64896 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 68672 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 133568 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1014 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1073 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2087 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 138390330 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 146442627 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 284832956 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 138390330 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 146442627 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 284832956 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1014.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1073.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4241 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2087 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2087 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 116 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 98 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 121 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 89 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 19480500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 10435000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 58611750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9334.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28084.21 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1636 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.39 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2087 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1462 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 439 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 295.537778 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 184.185643 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 301.373367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 148 32.89% 32.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 130 28.89% 61.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 47 10.44% 72.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 6.67% 78.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 20 4.44% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 16 3.56% 86.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 18 4.00% 90.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.11% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 36 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 133568 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 133568 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 284.83 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 284.83 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.23 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 468792000 # Total gap between requests +system.mem_ctrls.avgGap 224624.82 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 64896 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 68672 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 138390329.566282719374 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 146442626.848738998175 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1014 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1073 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 27791000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 30820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27407.30 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28723.90 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.39 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1570800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 834900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6418860 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 127052430 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 73079520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 245834910 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 524.241467 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 188810000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 264524500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1649340 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 872850 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 8482320 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 181366590 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 27341280 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 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mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67858.667159 # average WriteReq miss latency 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1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 454.875030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 336606 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 219.430248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 454.875030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 680902 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 680902 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 468934500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/calculix/beampic.log b/TAGE_SC_L/calculix/beampic.log new file mode 100644 index 000000000..f2915065d --- /dev/null +++ b/TAGE_SC_L/calculix/beampic.log @@ -0,0 +1,2 @@ + *ERROR in openfile: input file /data/ref/input/hyperviscoplastic.inp.inp + does not exist diff --git a/TAGE_SC_L/calculix/config.ini b/TAGE_SC_L/calculix/config.ini new file mode 100644 index 000000000..987de1a4c --- /dev/null +++ b/TAGE_SC_L/calculix/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc 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opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 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+id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross -i /data/ref/input/hyperviscoplastic.inp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=beampic.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/calculix/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/calculix/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/calculix/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/calculix/config.json b/TAGE_SC_L/calculix/config.json new file mode 100644 index 000000000..83ea5dbb6 --- /dev/null +++ b/TAGE_SC_L/calculix/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/calculix/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/calculix/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/calculix/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, 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"device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/calculix/fs/proc/cpuinfo b/TAGE_SC_L/calculix/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/calculix/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/calculix/fs/proc/stat b/TAGE_SC_L/calculix/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/calculix/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/online b/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/calculix/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/calculix/stats.txt b/TAGE_SC_L/calculix/stats.txt new file mode 100644 index 000000000..5b136e16a --- /dev/null +++ b/TAGE_SC_L/calculix/stats.txt @@ -0,0 +1,1359 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 56861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 61232 # Simulator instruction rate (inst/s) +host_mem_usage 856820 # Number of bytes of host memory used +host_op_rate 73961 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.38 # Real time elapsed on the host +host_tick_rate 147811949 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 23532 # Number of instructions simulated +sim_ops 28450 # Number of ops (including micro ops) simulated +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56861000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.498652 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 3688 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4821 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8019 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 34 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 465 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 431 # Number of indirect misses. +system.cpu.branchPred.lookups 11185 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2360 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 1810 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2273 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 1897 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 124 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 31 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 112 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 37 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 2916 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 558 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 93 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 66 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 347 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 15 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 859 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 8625 # number of cc regfile reads +system.cpu.cc_regfile_writes 8679 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 834 # The number of times a branch was mispredicted +system.cpu.commit.branches 5605 # Number of branches committed +system.cpu.commit.bw_lim_events 1239 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 54 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 23588 # Number of instructions committed +system.cpu.commit.committedOps 28506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 39891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.714597 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.779156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30973 77.64% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3276 8.21% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1731 4.34% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 879 2.20% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 598 1.50% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 551 1.38% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 436 1.09% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208 0.52% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1239 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39891 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 490 # Number of function calls committed. +system.cpu.commit.int_insts 25886 # Number of committed integer instructions. +system.cpu.commit.loads 4020 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 19666 68.99% 69.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.15% 69.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.01% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.09% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 26 0.09% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.10% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 30 0.11% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 4020 14.10% 83.66% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4658 16.34% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 28506 # Class of committed instruction +system.cpu.commit.refs 8678 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 413 # Number of committed Vector instructions. +system.cpu.committedInsts 23532 # Number of Instructions Simulated +system.cpu.committedOps 28450 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.832696 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.832696 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 13004 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 460 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3802 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 47302 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 19734 # Number of cycles decode is idle +system.cpu.decode.RunCycles 7777 # Number of cycles decode is running +system.cpu.decode.SquashCycles 869 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1546 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 710 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 11185 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6474 # Number of cache lines fetched +system.cpu.fetch.Cycles 17733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 47366 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2642 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.098353 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22801 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4581 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.416503 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 42094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.317646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 31882 75.74% 75.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1052 2.50% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1015 2.41% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 717 1.70% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1034 2.46% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 1.74% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1010 2.40% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 843 2.00% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3810 9.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 42094 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 71629 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 997 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 6864 # Number of branches executed +system.cpu.iew.exec_nop 122 # number of nop insts executed +system.cpu.iew.exec_rate 0.326908 # Inst execution rate +system.cpu.iew.exec_refs 11357 # number of memory reference insts executed +system.cpu.iew.exec_stores 5453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2304 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 6339 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 89 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6321 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 42090 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 5904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1114 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 37177 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 869 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1371 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 86 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1663 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 188 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 31510 # num instructions consuming a value +system.cpu.iew.wb_count 35773 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.563504 # average fanout of values written-back +system.cpu.iew.wb_producers 17756 # num instructions producing a value +system.cpu.iew.wb_rate 0.314563 # insts written-back per cycle +system.cpu.iew.wb_sent 36351 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 41177 # number of integer regfile reads +system.cpu.int_regfile_writes 25395 # number of integer regfile writes +system.cpu.ipc 0.206924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.206924 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 8 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 26234 68.51% 68.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.11% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.01% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 28 0.07% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.07% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 32 0.08% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.09% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 6191 16.17% 85.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5691 14.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 38291 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 555 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189 34.05% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.18% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.36% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 118 21.26% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 245 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 38309 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 118302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 35311 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 54736 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 41879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 38291 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13517 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 42094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.909655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29929 71.10% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2997 7.12% 78.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2546 6.05% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2071 4.92% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1657 3.94% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1133 2.69% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 951 2.26% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 490 1.16% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 320 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42094 # Number of insts issued each cycle +system.cpu.iq.rate 0.336704 # Inst issue rate +system.cpu.iq.vec_alu_accesses 529 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1074 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 462 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 769 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 6339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6321 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 28736 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 113723 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3701 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 26781 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 202 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 20563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 64176 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 44669 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 42396 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 7626 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 751 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 869 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1430 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15615 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 49589 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 7905 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 302 # count of serializing insts renamed +system.cpu.rename.skidInsts 3721 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 688 # Number of vector rename lookups +system.cpu.rob.rob_reads 80411 # The number of ROB reads +system.cpu.rob.rob_writes 86307 # The number of ROB writes +system.cpu.timesIdled 663 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 512 # number of vector regfile reads +system.cpu.vec_regfile_writes 137 # number of vector regfile writes +system.cpu.workload.numSyscalls 17 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1251 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 502 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1817 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1026 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution +system.membus.trans_dist::ReadExResp 168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1027 # Transaction distribution +system.membus.trans_dist::InvalidateReq 56 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1251 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1251 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1251 # Request fanout histogram +system.membus.reqLayer0.occupancy 1533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 6321500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1089 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 27 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 440 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 33 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 171 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 171 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 925 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 165 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 56 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 56 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2289 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 844 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3133 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 87296 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 23232 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 110528 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001519 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.038954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1315 99.85% 99.85% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.15% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1375500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 532000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1386000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 42 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 66 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 42 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 66 # number of overall hits +system.l2.demand_misses::.cpu.inst 883 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 312 # number of demand (read+write) misses +system.l2.demand_misses::total 1195 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 883 # number of overall misses +system.l2.overall_misses::.cpu.data 312 # number of overall misses +system.l2.overall_misses::total 1195 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 68520500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 25782500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 94303000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 68520500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 25782500 # number of overall miss cycles +system.l2.overall_miss_latency::total 94303000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 925 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 336 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1261 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 925 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 336 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1261 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.954595 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.928571 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.947661 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.954595 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.928571 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.947661 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 883 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 312 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1195 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 883 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 312 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1195 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 59700500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 22662500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 82363000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 59700500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 22662500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 82363000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.947661 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.947661 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 27 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 27 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 440 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 440 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 440 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 440 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 168 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 168 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 56 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 56 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19000 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19000 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 638.816237 # Cycle average of tags in use +system.l2.tags.total_refs 1760 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1196 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.471572 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 0.787737 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 434.030626 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 203.997874 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000024 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013246 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006226 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.019495 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1196 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1019 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.036499 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 15732 # Number of tag accesses +system.l2.tags.data_accesses 15732 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56448 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 19968 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 76416 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 882 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 312 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1194 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 992736674 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 351172157 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1343908830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 992736674 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 351172157 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1343908830 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 883.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 312.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000542000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2358 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1195 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1195 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 126 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 91 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.77 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10859000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 5975000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 33265250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9087.03 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27837.03 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 963 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.59 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1195 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 132 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 225 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 336.213333 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 219.600202 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.995257 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 57 25.33% 25.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 62 27.56% 52.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 32 14.22% 67.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 7.56% 74.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 4.44% 79.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 15 6.67% 85.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.67% 88.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 3.56% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 18 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 225 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 76480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 76480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1345.03 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1345.03 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.51 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.51 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 56833500 # Total gap between requests +system.mem_ctrls.avgGap 47559.41 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 19968 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 993862225.426918268204 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 351172156.662738919258 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 883 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 312 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23476250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 9789000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26586.92 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31375.00 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 849660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4448220 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 24871380 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 890400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 35806155 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 629.713776 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 2123000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 52918000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 806820 # Energy for activate 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overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71753.144703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71753.144703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72049.787724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72049.787724 # average overall mshr miss latency +system.cpu.dcache.replacements 60 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26851000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26851000 # number of ReadReq miss cycles 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cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 223.007274 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 9264 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.632653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 223.007274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 332 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.648438 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 20752 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 20752 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 56861000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/gobmk/capture.out b/TAGE_SC_L/gobmk/capture.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/gobmk/config.ini b/TAGE_SC_L/gobmk/config.ini new file mode 100644 index 000000000..0cc73df57 --- /dev/null +++ b/TAGE_SC_L/gobmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 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system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true 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+id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross --quiet --mode gtp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//data/ref/input/13x13.tst +kvmInSE=false +maxStackSize=67108864 +output=capture.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/gobmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/gobmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/gobmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/gobmk/config.json b/TAGE_SC_L/gobmk/config.json new file mode 100644 index 000000000..06ecb1047 --- /dev/null +++ b/TAGE_SC_L/gobmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/gobmk/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/gobmk/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/gobmk/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + 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+ "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/gobmk/fs/proc/cpuinfo b/TAGE_SC_L/gobmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/gobmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/gobmk/fs/proc/stat b/TAGE_SC_L/gobmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/gobmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/online b/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/gobmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/gobmk/stats.txt b/TAGE_SC_L/gobmk/stats.txt new file mode 100644 index 000000000..08004a031 --- /dev/null +++ b/TAGE_SC_L/gobmk/stats.txt @@ -0,0 +1,1342 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 463966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 102584 # Simulator instruction rate (inst/s) +host_mem_usage 858876 # Number of bytes of host memory used +host_op_rate 102967 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.75 # Real time elapsed on the host +host_tick_rate 47594389 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1003756 # Number of ops (including micro ops) simulated +sim_seconds 0.000464 # Number of seconds simulated +sim_ticks 463966500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.726161 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 173713 # Number of BTB hits +system.cpu.branchPred.BTBLookups 174190 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 844 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 175218 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 134 # Number of indirect misses. +system.cpu.branchPred.lookups 183670 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 9619 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 154197 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 4842 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 158974 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 65 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 763 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 46 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 40 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 275 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 136 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 60 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 145 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 215 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 206 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 108 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 36 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 61 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 62 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 79 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 269 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 10 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 159067 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 285 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 40 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 64 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 301 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 52 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 248 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 125 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 68 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 212 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 183 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 270 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 165 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 329 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 82 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 95 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 3403 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 40 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 100 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2727 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 507132 # number of cc regfile reads +system.cpu.cc_regfile_writes 507438 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 649 # The number of times a branch was mispredicted +system.cpu.commit.branches 171144 # Number of branches committed +system.cpu.commit.bw_lim_events 19230 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 40539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000213 # Number of instructions committed +system.cpu.commit.committedOps 1003967 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 891530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.126117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.219871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 650701 72.99% 72.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 52797 5.92% 78.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32204 3.61% 82.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21703 2.43% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7692 0.86% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7047 0.79% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99282 11.14% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 874 0.10% 97.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19230 2.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 891530 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2417 # Number of function calls committed. +system.cpu.commit.int_insts 840106 # Number of committed integer instructions. +system.cpu.commit.loads 310680 # Number of loads committed +system.cpu.commit.membars 16 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 533766 53.17% 53.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 449 0.04% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 310680 30.95% 84.16% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 159002 15.84% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1003967 # Class of committed instruction +system.cpu.commit.refs 469682 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 248 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1003756 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927932 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927932 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 713461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 170925 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1055068 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 40149 # Number of cycles decode is idle +system.cpu.decode.RunCycles 102411 # Number of cycles decode is running +system.cpu.decode.SquashCycles 990 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 670 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 40070 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 183670 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15255 # Number of cache lines fetched +system.cpu.fetch.Cycles 872161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1072586 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.197934 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 23707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 176441 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.155886 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 897081 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.201933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.336465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692458 77.19% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4126 0.46% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23115 2.58% 80.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1334 0.15% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25122 2.80% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 897 0.10% 83.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139169 15.51% 98.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2994 0.33% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7866 0.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 897081 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 30853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 729 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 177146 # Number of branches executed +system.cpu.iew.exec_nop 257 # number of nop insts executed +system.cpu.iew.exec_rate 1.156592 # Inst execution rate +system.cpu.iew.exec_refs 519344 # number of memory reference insts executed +system.cpu.iew.exec_stores 164447 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 5056 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 321924 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 164988 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1044518 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 354897 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1073241 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 17069 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 990 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 17094 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8383 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11235 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5981 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 446 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1269546 # num instructions consuming a value +system.cpu.iew.wb_count 1033965 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.530245 # average fanout of values written-back +system.cpu.iew.wb_producers 673170 # num instructions producing a value +system.cpu.iew.wb_rate 1.114266 # insts written-back per cycle +system.cpu.iew.wb_sent 1039294 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1392509 # number of integer regfile reads +system.cpu.int_regfile_writes 700174 # number of integer regfile writes +system.cpu.ipc 1.077665 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077665 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 553864 51.57% 51.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 501 0.05% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 25 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 355062 33.06% 84.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 164583 15.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1074097 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 18272 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017011 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 123 0.67% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18071 98.90% 99.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 75 0.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1092056 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3062983 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1033689 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1084351 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1044228 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1074097 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 40478 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 23290 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 897081 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.197324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 639583 71.30% 71.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 33403 3.72% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24407 2.72% 77.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 35269 3.93% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 51684 5.76% 87.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56013 6.24% 93.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5377 0.60% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43750 4.88% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7595 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 897081 # Number of insts issued each cycle +system.cpu.iq.rate 1.157514 # Inst issue rate +system.cpu.iq.vec_alu_accesses 308 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 619 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 276 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 424 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2492 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2394 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 321924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 164988 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 865847 # number of misc regfile reads +system.cpu.misc_regfile_writes 65 # number of misc regfile writes +system.cpu.numCycles 927934 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23218 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1166751 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3317 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 60184 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 8163 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1892164 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1047728 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1217345 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 122048 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 674293 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 990 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 686442 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 50538 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1368066 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4199 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.skidInsts 219619 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 409 # Number of vector rename lookups +system.cpu.rob.rob_reads 1912854 # The number of ROB reads +system.cpu.rob.rob_writes 2094604 # The number of ROB writes +system.cpu.timesIdled 311 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 318 # number of vector regfile reads +system.cpu.vec_regfile_writes 92 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 22125 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 21334 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 43517 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 464 # Transaction distribution +system.membus.trans_dist::ReadExReq 18836 # Transaction distribution +system.membus.trans_dist::ReadExResp 18835 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 464 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 22125 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 22125 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 22125 # Request fanout histogram +system.membus.reqLayer0.occupancy 31087500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 98420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 504 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 21206 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 51 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 77 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 18854 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 18851 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 385 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 119 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2825 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 821 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 64876 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 65697 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 2571264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2599168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 22183 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000045 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.006714 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 22182 100.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 22183 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 43015500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 9.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 29867500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 577500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 8 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 48 # number of demand (read+write) hits +system.l2.demand_hits::total 56 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 8 # number of overall hits +system.l2.overall_hits::.cpu.data 48 # number of overall hits +system.l2.overall_hits::total 56 # number of overall hits +system.l2.demand_misses::.cpu.inst 377 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 18925 # number of demand (read+write) misses +system.l2.demand_misses::total 19302 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 377 # number of overall misses +system.l2.overall_misses::.cpu.data 18925 # number of overall misses +system.l2.overall_misses::total 19302 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 30084500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1436692500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1466777000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 30084500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1436692500 # number of overall miss cycles +system.l2.overall_miss_latency::total 1466777000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 385 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 18973 # number of demand (read+write) accesses +system.l2.demand_accesses::total 19358 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 385 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 18973 # number of overall (read+write) accesses +system.l2.overall_accesses::total 19358 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.979221 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.997470 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.997107 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.979221 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.997470 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.997107 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 377 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 18925 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 19302 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 377 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 18925 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 19302 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 26314500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1247472500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1273787000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 26314500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1247472500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1273787000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.997107 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.997107 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 51 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 51 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 51 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 51 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 16 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 16 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 18838 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 18838 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19206.725664 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19206.725664 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 11222.269262 # Cycle average of tags in use +system.l2.tags.total_refs 40688 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 22124 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.839089 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 2583.087120 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 362.014998 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 8277.167144 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.078830 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.011048 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.252599 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.342476 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 22124 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 472 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4203 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 17449 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.675171 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 370252 # Number of tag accesses +system.l2.tags.data_accesses 370252 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 24128 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1211008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1235136 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 377 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 18922 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 19299 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 52003755 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2610119481 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2662123235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 52003755 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2610119481 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2662123235 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 377.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 18923.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000585000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 38666 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 19300 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 19300 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1250 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1163 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1166 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1206 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1234 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.19 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 115628000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 96500000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 477503000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5991.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24741.09 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 17926 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 19300 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5032 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 4929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 5539 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 3792 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1373 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 899.589221 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 780.016617 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 290.557773 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 61 4.44% 4.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 55 4.01% 8.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44 3.20% 11.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 0.66% 12.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 33 2.40% 14.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 0.44% 15.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 25 1.82% 16.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 0.44% 17.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1134 82.59% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1235200 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1235200 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2662.26 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2662.26 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 20.80 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 20.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 463952000 # Total gap between requests +system.mem_ctrls.avgGap 24038.96 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 24128 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1211072 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 52003754.581419132650 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2610257421.602637290955 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 377 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 18923 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 10808750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 466694250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28670.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24662.80 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 92.88 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 5069400 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2690655 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 70093380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 117849210 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 78922080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 310888485 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 670.066664 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank 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Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 85096800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 306839610 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 661.340011 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 216684000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states 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mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032973 # miss rate for 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mshr miss latency +system.cpu.dcache.replacements 21283 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 69376.068376 # average ReadReq mshr miss latency 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+system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 492.463211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 21795 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.001468 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 492.463211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 981503 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 981503 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 463966500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/h264ref/config.ini b/TAGE_SC_L/h264ref/config.ini new file mode 100644 index 000000000..8e7bd93ce --- /dev/null +++ b/TAGE_SC_L/h264ref/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 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opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 system.cpu.fuPool.FUList5.opList23 system.cpu.fuPool.FUList5.opList24 system.cpu.fuPool.FUList5.opList25 + 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+children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//exe/h264ref_base.amd64-armcross -d /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//exe/h264ref_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=foreman_ref_encoder_baseline.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/h264ref/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/h264ref/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/h264ref/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/h264ref/config.json b/TAGE_SC_L/h264ref/config.json new file mode 100644 index 000000000..3f1053627 --- /dev/null +++ b/TAGE_SC_L/h264ref/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/h264ref/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/h264ref/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/h264ref/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": 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"device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/h264ref/foreman_ref_encoder_baseline.out b/TAGE_SC_L/h264ref/foreman_ref_encoder_baseline.out new file mode 100644 index 000000000..52c97f4e8 --- /dev/null +++ b/TAGE_SC_L/h264ref/foreman_ref_encoder_baseline.out @@ -0,0 +1,3 @@ +Setting Default Parameters... +Parsing Configfile /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg..................................................................................................... + diff --git a/TAGE_SC_L/h264ref/fs/proc/cpuinfo b/TAGE_SC_L/h264ref/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/h264ref/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/h264ref/fs/proc/stat b/TAGE_SC_L/h264ref/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/h264ref/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/online b/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/h264ref/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/h264ref/stats.txt b/TAGE_SC_L/h264ref/stats.txt new file mode 100644 index 000000000..f6403ebc1 --- /dev/null +++ b/TAGE_SC_L/h264ref/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 182784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 116422 # Simulator instruction rate (inst/s) +host_mem_usage 854068 # Number of bytes of host memory used +host_op_rate 130295 # Simulator op (including micro ops) rate (op/s) +host_seconds 3.48 # Real time elapsed on the host +host_tick_rate 52523270 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 404970 # Number of instructions simulated +sim_ops 453431 # Number of ops (including micro ops) simulated +sim_seconds 0.000183 # Number of seconds simulated +sim_ticks 182784500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 96.009202 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 69695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 72592 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 8 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4076 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 102227 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 418 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1049 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 631 # Number of indirect misses. +system.cpu.branchPred.lookups 136457 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 66625 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 18738 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 44665 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 40698 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 57 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 9904 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1003 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 714 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 662 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2209 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 654 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 708 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 4799 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1081 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1832 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 825 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1857 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1058 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1044 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 424 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 757 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1046 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 773 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 950 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1657 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1011 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 156 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 335 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 46618 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 786 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3277 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 416 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 539 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 6416 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 599 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2356 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 888 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 887 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1797 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 4845 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1705 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1913 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 912 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1087 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 920 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1393 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1055 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 775 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1090 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1709 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 34908 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 168 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 947 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 8368 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 121 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 188694 # number of cc regfile reads +system.cpu.cc_regfile_writes 181404 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3081 # The number of times a branch was mispredicted +system.cpu.commit.branches 113779 # Number of branches committed +system.cpu.commit.bw_lim_events 9761 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 47211 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 405226 # Number of instructions committed +system.cpu.commit.committedOps 453687 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 282466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.606165 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.996099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108243 38.32% 38.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 63776 22.58% 60.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49902 17.67% 78.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20051 7.10% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13675 4.84% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 10042 3.56% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2156 0.76% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4860 1.72% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 9761 3.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 282466 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 7544 # Number of function calls committed. +system.cpu.commit.int_insts 391118 # Number of committed integer instructions. +system.cpu.commit.loads 53629 # Number of loads committed +system.cpu.commit.membars 246 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 11 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 373891 82.41% 82.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 128 0.03% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 4 0.00% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 9 0.00% 82.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 9 0.00% 82.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 375 0.08% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 33 0.01% 82.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 82.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 43 0.01% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 44 0.01% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 42 0.01% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 53629 11.82% 94.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 25468 5.61% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 453687 # Class of committed instruction +system.cpu.commit.refs 79097 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2794 # Number of committed Vector instructions. +system.cpu.committedInsts 404970 # Number of Instructions Simulated +system.cpu.committedOps 453431 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.902709 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.902709 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 46298 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1088 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 68885 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 519819 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 122615 # Number of cycles decode is idle +system.cpu.decode.RunCycles 115377 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3133 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3602 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2711 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 136457 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 92422 # Number of cache lines fetched +system.cpu.fetch.Cycles 152260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 485690 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 489 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 8418 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.373272 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 132898 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 78481 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.328583 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 290134 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.872717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.680965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 166227 57.29% 57.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 18234 6.28% 63.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23702 8.17% 71.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4941 1.70% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13532 4.66% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24530 8.45% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3154 1.09% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19336 6.66% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 16478 5.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 290134 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 75436 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3352 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 119652 # Number of branches executed +system.cpu.iew.exec_nop 412 # number of nop insts executed +system.cpu.iew.exec_rate 1.331813 # Inst execution rate +system.cpu.iew.exec_refs 90712 # number of memory reference insts executed +system.cpu.iew.exec_stores 27232 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 15288 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 61281 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 404 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 578 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 28437 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 500946 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 63480 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 486871 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 6948 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3133 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7222 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 480 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 655 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 7652 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2969 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2195 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 456972 # num instructions consuming a value +system.cpu.iew.wb_count 479571 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.549522 # average fanout of values written-back +system.cpu.iew.wb_producers 251116 # num instructions producing a value +system.cpu.iew.wb_rate 1.311845 # insts written-back per cycle +system.cpu.iew.wb_sent 480595 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 518416 # number of integer regfile reads +system.cpu.int_regfile_writes 336713 # number of integer regfile writes +system.cpu.ipc 1.107777 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.107777 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 92 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 397903 81.00% 81.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 141 0.03% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 12 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 15 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 9 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 504 0.10% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.01% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 45 0.01% 81.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.01% 81.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 51 0.01% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64796 13.19% 94.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 27598 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 491250 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5758 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011721 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3005 52.19% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.02% 52.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.03% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1119 19.43% 71.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1631 28.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 492538 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1270488 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 476500 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 543000 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 500130 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 491250 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 47102 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 391 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 137 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 34927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 290134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.693183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.849936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99883 34.43% 34.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 70212 24.20% 58.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 46683 16.09% 74.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19052 6.57% 81.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19950 6.88% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19386 6.68% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11922 4.11% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2114 0.73% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 932 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290134 # Number of insts issued each cycle +system.cpu.iq.rate 1.343792 # Inst issue rate +system.cpu.iq.vec_alu_accesses 4378 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 8295 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 3071 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 4664 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 207 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 153 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 61281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 28437 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 337755 # number of misc regfile reads +system.cpu.misc_regfile_writes 1378 # number of misc regfile writes +system.cpu.numCycles 365570 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23496 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 489437 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1748 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 125297 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 653 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 769495 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 512551 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 560059 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 115036 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 4963 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3133 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 8520 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 70622 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 542232 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 14652 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 836 # count of serializing insts renamed +system.cpu.rename.skidInsts 13164 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 3314 # Number of vector rename lookups +system.cpu.rob.rob_reads 773252 # The number of ROB reads +system.cpu.rob.rob_writes 1009500 # The number of ROB writes +system.cpu.timesIdled 1222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2634 # number of vector regfile reads +system.cpu.vec_regfile_writes 765 # number of vector regfile writes +system.cpu.workload.numSyscalls 20 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1886 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2788 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 6575 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1461 # Transaction distribution +system.membus.trans_dist::ReadExReq 363 # Transaction distribution +system.membus.trans_dist::ReadExResp 363 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1461 # Transaction distribution +system.membus.trans_dist::InvalidateReq 62 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3710 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 116736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116736 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1886 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1886 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1886 # Request fanout histogram +system.membus.reqLayer0.occupancy 2371500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9628750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3293 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 641 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1526 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 621 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 426 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 426 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2024 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1270 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 67 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 67 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 5573 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4788 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 10361 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 227136 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 376704 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3787 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000264 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.016250 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3786 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3787 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 5454500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2577500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3034500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1103 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 792 # number of demand (read+write) hits +system.l2.demand_hits::total 1895 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1103 # number of overall hits +system.l2.overall_hits::.cpu.data 792 # number of overall hits +system.l2.overall_hits::total 1895 # number of overall hits +system.l2.demand_misses::.cpu.inst 921 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 904 # number of demand (read+write) misses +system.l2.demand_misses::total 1825 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 921 # number of overall misses +system.l2.overall_misses::.cpu.data 904 # number of overall misses +system.l2.overall_misses::total 1825 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 72634500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 71937500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 144572000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 72634500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 71937500 # number of overall miss cycles +system.l2.overall_miss_latency::total 144572000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2024 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1696 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3720 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2024 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1696 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3720 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.455040 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.533019 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.490591 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.455040 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.533019 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.490591 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78864.820847 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79576.880531 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79217.534247 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78864.820847 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79576.880531 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79217.534247 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 921 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 904 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1825 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 921 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 904 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1825 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 63434500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 62897500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 126332000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 63434500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 62897500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 126332000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.533019 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.490591 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.533019 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.490591 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69576.880531 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69223.013699 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69576.880531 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69223.013699 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 641 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 641 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 641 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 641 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1526 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1526 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1526 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1526 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 63 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 63 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 363 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 363 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 28112500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 28112500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 426 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 426 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.852113 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.852113 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77444.903581 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77444.903581 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 363 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 363 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 24482500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 24482500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.852113 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.852113 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67444.903581 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67444.903581 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1103 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1103 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 921 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 921 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 72634500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 72634500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2024 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2024 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.455040 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.455040 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78864.820847 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78864.820847 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 921 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 921 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 63434500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 63434500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.455040 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68875.678610 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 729 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 729 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 541 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 541 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 43825000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 43825000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1270 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1270 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.425984 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.425984 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81007.393715 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81007.393715 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 541 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 541 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 38415000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 38415000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.425984 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.425984 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71007.393715 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71007.393715 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 5 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 5 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 62 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 62 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 67 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 67 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.925373 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.925373 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 62 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 62 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1179500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1179500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.925373 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.925373 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19024.193548 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19024.193548 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1322.433314 # Cycle average of tags in use +system.l2.tags.total_refs 6511 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1877 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.468833 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 39.648283 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 630.978547 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 651.806484 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001210 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.019256 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.019892 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.040357 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 192 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.057129 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 54469 # Number of tag accesses +system.l2.tags.data_accesses 54469 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 58880 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 57856 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 116736 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 58880 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 58880 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 920 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 904 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1824 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 322127970 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 316525745 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 638653715 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 322127970 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 322127970 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 322127970 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 316525745 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 638653715 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 920.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 904.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000580000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3628 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1824 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1824 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 189 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 197 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 155 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 101 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 127 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 89 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 17018000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 9120000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 51218000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9330.04 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28080.04 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1498 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 82.13 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1824 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 952 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 538 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 224 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 91 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 316 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 362.531646 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 212.877483 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 353.211294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 106 33.54% 33.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 61 19.30% 52.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 35 11.08% 63.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 24 7.59% 71.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 13 4.11% 75.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.80% 79.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 3.48% 82.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.58% 84.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 49 15.51% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 316 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 116736 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 116736 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 638.65 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 638.65 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.99 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.99 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 182676500 # Total gap between requests +system.mem_ctrls.avgGap 100151.59 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 58880 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 57856 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 322127970.369478821754 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 316525744.797835707664 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 920 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 904 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 25584250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 25633750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27808.97 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28355.92 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 792540 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 402270 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4441080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 14136720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 50495160 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 27667200 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 97934970 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 535.794720 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 71508750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 5980000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 105295750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1535100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 796950 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 8582280 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 14136720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 41640780 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 35123520 # Energy for precharge background per rank (pJ) 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(read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 103808498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 103808498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 92420 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 92420 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 92420 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 92420 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.024767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.024767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.024767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.024767 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 45351.025775 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45351.025775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 45351.025775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45351.025775 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1564 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1526 # number of writebacks +system.cpu.icache.writebacks::total 1526 # number of writebacks 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replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 90131 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 90131 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2289 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2289 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 103808498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 103808498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 92420 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 92420 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.024767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.024767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 45351.025775 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45351.025775 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 265 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 265 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 2024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 87359998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 87359998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.021900 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.021900 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 43162.054348 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43162.054348 # average ReadReq mshr miss latency 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per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 186863 # Number of tag accesses +system.cpu.icache.tags.data_accesses 186863 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states 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replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 55579 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 55579 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3076 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3076 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 130689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 130689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 58655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 58655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.052442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 42486.833550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42486.833550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 53189500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53189500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.021584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 42013.823065 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42013.823065 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 22834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22834 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 2333 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2333 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 123942720 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 123942720 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 25167 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 25167 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.092701 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.092701 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 53125.897985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53125.897985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 433 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 433 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 29591988 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29591988 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.017205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 68341.773672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68341.773672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 20 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 20 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 22 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 22 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.090909 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.090909 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.090909 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1920455 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1920455 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32007.583333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32007.583333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1860455 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1860455 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31007.583333 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31007.583333 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 258 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 258 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 214000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 214000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.019011 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.019011 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007605 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007605 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 246 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 246 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 246 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 246 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 433.592808 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 80700 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 45.774248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 433.592808 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.846861 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.846861 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 170589 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 170589 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 182784500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/hmmer/bombesin.out b/TAGE_SC_L/hmmer/bombesin.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/hmmer/config.ini b/TAGE_SC_L/hmmer/config.ini new file mode 100644 index 000000000..c1fe08b78 --- /dev/null +++ b/TAGE_SC_L/hmmer/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 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+response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross --fixed 0 --mean 325 --num 5000 --sd 200 --seed 0 /home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//data/ref/input/nph3.hmm +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=bombesin.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/hmmer/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/hmmer/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/hmmer/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/hmmer/config.json b/TAGE_SC_L/hmmer/config.json new file mode 100644 index 000000000..9037e185d --- /dev/null +++ b/TAGE_SC_L/hmmer/config.json @@ -0,0 +1,1821 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { 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"ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/hmmer/fs/proc/cpuinfo b/TAGE_SC_L/hmmer/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/hmmer/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/hmmer/fs/proc/stat b/TAGE_SC_L/hmmer/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/hmmer/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/online b/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/hmmer/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/hmmer/stats.txt b/TAGE_SC_L/hmmer/stats.txt new file mode 100644 index 000000000..39ba48161 --- /dev/null +++ b/TAGE_SC_L/hmmer/stats.txt @@ -0,0 +1,1345 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 371151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 98748 # Simulator instruction rate (inst/s) +host_mem_usage 855464 # Number of bytes of host memory used +host_op_rate 125908 # Simulator op (including micro ops) rate (op/s) +host_seconds 10.13 # Real time elapsed on the host +host_tick_rate 36649681 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1275067 # Number of ops (including micro ops) simulated +sim_seconds 0.000371 # Number of seconds simulated +sim_ticks 371151000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.606810 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 134690 # Number of BTB hits +system.cpu.branchPred.BTBLookups 136593 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7055 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 204306 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 469 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1143 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 674 # Number of indirect misses. +system.cpu.branchPred.lookups 261150 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95555 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 56119 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89830 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61844 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 277 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 66 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 11001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2901 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 666 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 346 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 6942 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1667 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1558 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 892 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1613 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 838 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1380 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2365 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1862 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1343 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2169 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 355 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1232 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 102898 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1036 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1952 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 472 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 6800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 7412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1147 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1856 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1332 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1037 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1444 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1142 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1280 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1072 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1398 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1571 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1970 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1994 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2018 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 3065 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39731 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 649 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 2829 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 19178 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 172 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 299295 # number of cc regfile reads +system.cpu.cc_regfile_writes 276253 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6404 # The number of times a branch was mispredicted +system.cpu.commit.branches 199789 # Number of branches committed +system.cpu.commit.bw_lim_events 86134 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 405 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 214441 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002214 # Number of instructions committed +system.cpu.commit.committedOps 1277279 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 626626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038343 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.814350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301756 48.16% 48.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 90275 14.41% 62.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51837 8.27% 70.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 43017 6.86% 77.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25180 4.02% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 11065 1.77% 83.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 12372 1.97% 85.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4990 0.80% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 86134 13.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 626626 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 15547 # Number of function calls committed. +system.cpu.commit.int_insts 1131445 # Number of committed integer instructions. +system.cpu.commit.loads 187072 # Number of loads committed +system.cpu.commit.membars 384 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 861 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756222 59.21% 59.27% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7535 0.59% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 23 0.00% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2196 0.17% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 10982 0.86% 60.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 10950 0.86% 61.75% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 15330 1.20% 62.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 2212 0.17% 63.13% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 16014 1.25% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1597 0.13% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 2100 0.16% 64.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 2000 0.16% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 3853 0.30% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 187072 14.65% 79.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 258328 20.22% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1277279 # Class of committed instruction +system.cpu.commit.refs 445400 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 96081 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1275067 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.742302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.742302 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 239022 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 662 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131096 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1597574 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 141803 # Number of cycles decode is idle +system.cpu.decode.RunCycles 249035 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6496 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2505 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 20755 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 261150 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157977 # Number of cache lines fetched +system.cpu.fetch.Cycles 467292 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2017 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1344580 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14294 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.351811 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 182557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 154337 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.811363 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 657111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.521428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.140176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 348325 53.01% 53.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23632 3.60% 56.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27656 4.21% 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30837 4.69% 65.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 31384 4.78% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30870 4.70% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 47784 7.27% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14171 2.16% 84.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102452 15.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 657111 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 85192 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 11895 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 212923 # Number of branches executed +system.cpu.iew.exec_nop 2687 # number of nop insts executed +system.cpu.iew.exec_rate 1.861834 # Inst execution rate +system.cpu.iew.exec_refs 480552 # number of memory reference insts executed +system.cpu.iew.exec_stores 266534 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 30022 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 229901 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 453 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 644 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 292791 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1492153 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 214018 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1382045 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 127 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 240 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6496 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 396 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 297 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 83 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 42824 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 34431 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2505 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 9390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1186513 # num instructions consuming a value +system.cpu.iew.wb_count 1367463 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.568161 # average fanout of values written-back +system.cpu.iew.wb_producers 674131 # num instructions producing a value +system.cpu.iew.wb_rate 1.842190 # insts written-back per cycle +system.cpu.iew.wb_sent 1374742 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1621778 # number of integer regfile reads +system.cpu.int_regfile_writes 838864 # number of integer regfile writes +system.cpu.ipc 1.347161 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.347161 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 998 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829308 59.28% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7609 0.54% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 28 0.00% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2197 0.16% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 4 0.00% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 10983 0.79% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 10950 0.78% 61.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 15330 1.10% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 2212 0.16% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 16097 1.15% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1811 0.13% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 2359 0.17% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2282 0.16% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 4283 0.31% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 219731 15.71% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 272755 19.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1398937 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 43962 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031425 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7219 16.42% 16.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 13 0.03% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 2190 4.98% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 52 0.12% 21.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 62 0.14% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7316 16.64% 38.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 27110 61.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1342253 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3302227 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1269728 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1600011 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1489013 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1398937 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 453 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 214328 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 193555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 657111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.128920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.441391 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278120 42.32% 42.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 72738 11.07% 53.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 50307 7.66% 61.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 80997 12.33% 73.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 55228 8.40% 81.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 38544 5.87% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28076 4.27% 91.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 24302 3.70% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28799 4.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 657111 # Number of insts issued each cycle +system.cpu.iq.rate 1.884590 # Inst issue rate +system.cpu.iq.vec_alu_accesses 99648 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 198960 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 97735 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 103851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1873 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21229 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 229901 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 292791 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1127954 # number of misc regfile reads +system.cpu.misc_regfile_writes 45403 # number of misc regfile writes +system.cpu.numCycles 742303 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 31082 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1164220 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 541 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 153081 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2573258 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1560444 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1380122 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 256102 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 146174 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6496 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 153264 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 215859 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1883723 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 57086 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3503 # count of serializing insts renamed +system.cpu.rename.skidInsts 60035 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 123940 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031718 # The number of ROB reads +system.cpu.rob.rob_writes 3014020 # The number of ROB writes +system.cpu.timesIdled 847 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 120536 # number of vector regfile reads +system.cpu.vec_regfile_writes 92784 # number of vector regfile writes +system.cpu.workload.numSyscalls 20 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1880 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1721 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4415 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1411 # Transaction distribution +system.membus.trans_dist::ReadExReq 456 # Transaction distribution +system.membus.trans_dist::ReadExResp 456 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1411 # Transaction distribution +system.membus.trans_dist::InvalidateReq 13 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1880 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1880 # Request fanout histogram +system.membus.reqLayer0.occupancy 2346500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 9886750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2054 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 580 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 821 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 320 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 467 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 467 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1313 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 741 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 173 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 173 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3447 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 3662 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 136576 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 114432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 251008 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2694 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000371 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.019266 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2693 99.96% 99.96% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.04% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2694 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 3608500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1898999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1969999 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 245 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 409 # number of demand (read+write) hits +system.l2.demand_hits::total 654 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 245 # number of overall hits +system.l2.overall_hits::.cpu.data 409 # number of overall hits +system.l2.overall_hits::total 654 # number of overall hits +system.l2.demand_misses::.cpu.inst 1068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 799 # number of demand (read+write) misses +system.l2.demand_misses::total 1867 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1068 # number of overall misses +system.l2.overall_misses::.cpu.data 799 # number of overall misses +system.l2.overall_misses::total 1867 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 83627500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 64742000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 148369500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 83627500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 64742000 # number of overall miss cycles +system.l2.overall_miss_latency::total 148369500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1313 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1208 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2521 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1313 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1208 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2521 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.813404 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.661424 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.740579 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.813404 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.661424 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.740579 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 799 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1867 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 799 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1867 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 72947500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 56752000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 129699500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 72947500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 56752000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 129699500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.740579 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.740579 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 580 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 580 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 820 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 820 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 820 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 820 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 11 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 11 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 456 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 456 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1313 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1313 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.813404 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.813404 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 160 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 160 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 13 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 13 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18961.538462 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18961.538462 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1571.392330 # Cycle average of tags in use +system.l2.tags.total_refs 4401 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2036 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.161591 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.498537 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 965.191752 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 599.702041 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000198 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.029455 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.018301 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047955 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1876 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.057251 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 37348 # Number of tag accesses +system.l2.tags.data_accesses 37348 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 68352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 119488 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 799 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1867 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 184162241 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 137776808 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 321939049 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 184162241 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 137776808 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 321939049 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 799.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000577500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3767 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1867 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1867 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 37 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 28 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 177 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 180 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 17820750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 9335000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 52827000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9545.13 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28295.13 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1446 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 77.45 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1867 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1121 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 532 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 420 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 284.190476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 185.885137 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 276.585457 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 132 31.43% 31.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 114 27.14% 58.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 62 14.76% 73.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 33 7.86% 81.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 26 6.19% 87.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 3.33% 90.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 0.95% 91.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 1.90% 93.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 27 6.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 420 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 119488 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 119488 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 321.94 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 321.94 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.52 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 369996500 # Total gap between requests +system.mem_ctrls.avgGap 198177.02 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 68352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51136 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 184162241.244129747152 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 137776807.822153240442 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 799 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 28999750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 23827250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27153.32 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 29821.34 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1692180 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 895620 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6525960 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 151671300 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14798880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 204472020 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 550.913294 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 37200500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 321730500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1313760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 698280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6804420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 90643680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 66190560 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 194538780 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 524.149955 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 171329000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 187602000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 156317 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 156317 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 156317 # number of overall hits +system.cpu.icache.overall_hits::total 156317 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1660 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1660 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1660 # number of overall misses +system.cpu.icache.overall_misses::total 1660 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 108308496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108308496 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 157977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 157977 # number of demand (read+write) accesses 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.086957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 821 # number of writebacks +system.cpu.icache.writebacks::total 821 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 347 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 347 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 347 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88219497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88219497 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.replacements 821 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 156317 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 156317 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1660 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1660 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 108308496 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 120.053313 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 461.614751 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 492 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.960938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 317267 # Number of tag accesses +system.cpu.icache.tags.data_accesses 317267 # Number of data accesses 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number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 4699 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4699 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 4709 # number of overall misses +system.cpu.dcache.overall_misses::total 4709 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 212942364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212942364 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 473203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 473203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 473486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 473486 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.009930 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009930 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.009945 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009945 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 45316.527772 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45316.527772 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 45220.293905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45220.293905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7524 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.258824 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 580 # number of writebacks +system.cpu.dcache.writebacks::total 580 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3323 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 1376 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.overall_mshr_miss_rate::total 0.002917 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 52900.795785 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52900.795785 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 53000.358436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000.358436 # average overall mshr miss latency +system.cpu.dcache.replacements 900 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 397.840327 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470952 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1381 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 341.022448 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 397.840327 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 481 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.939453 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 949941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 949941 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 371151000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/lbm/config.ini b/TAGE_SC_L/lbm/config.ini new file mode 100644 index 000000000..f84eeb865 --- /dev/null +++ b/TAGE_SC_L/lbm/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 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+type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross 20 reference.dat 0 1 /home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//data/ref/input/100_100_130_ldc.of +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lbm.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/lbm/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/lbm/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/lbm/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/lbm/config.json b/TAGE_SC_L/lbm/config.json new file mode 100644 index 000000000..1941aed5e --- /dev/null +++ b/TAGE_SC_L/lbm/config.json @@ -0,0 +1,1815 @@ +{ + "name": null, + "sim_quantum": 0, + "system": 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"static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/lbm/fs/proc/cpuinfo b/TAGE_SC_L/lbm/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/lbm/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/lbm/fs/proc/stat b/TAGE_SC_L/lbm/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/lbm/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/online b/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/lbm/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/lbm/lbm.out b/TAGE_SC_L/lbm/lbm.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/lbm/stats.txt b/TAGE_SC_L/lbm/stats.txt new file mode 100644 index 000000000..e0374e5d8 --- /dev/null +++ b/TAGE_SC_L/lbm/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 4902307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 29755 # Simulator instruction rate (inst/s) +host_mem_usage 854852 # Number of bytes of host memory used +host_op_rate 67666 # Simulator op (including micro ops) rate (op/s) +host_seconds 33.61 # Real time elapsed on the host +host_tick_rate 145868835 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 2274104 # Number of ops (including micro ops) simulated +sim_seconds 0.004902 # Number of seconds simulated +sim_ticks 4902307500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.321334 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 80345 # Number of BTB hits +system.cpu.branchPred.BTBLookups 80894 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 681 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 82458 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 184 # Number of indirect misses. +system.cpu.branchPred.lookups 83857 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 1019 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 71229 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 885 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71363 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 7 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 16 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 13 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 71818 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 11 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 6 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 6 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 3 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 382 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 224787 # number of cc regfile reads +system.cpu.cc_regfile_writes 224753 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 458 # The number of times a branch was mispredicted +system.cpu.commit.branches 72859 # Number of branches committed +system.cpu.commit.bw_lim_events 3268 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 25 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 117033 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000020 # Number of instructions committed +system.cpu.commit.committedOps 2274123 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 9747057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.233314 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.924085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8920827 91.52% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 211342 2.17% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 263671 2.71% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 192727 1.98% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 887 0.01% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26860 0.28% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99059 1.02% 99.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28416 0.29% 99.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3268 0.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9747057 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 212 # Number of function calls committed. +system.cpu.commit.int_insts 2202108 # Number of committed integer instructions. +system.cpu.commit.loads 1635 # Number of loads committed +system.cpu.commit.membars 14 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 18 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 856639 37.67% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 35 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 2 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 5 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 50 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 75 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 72 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 50 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1635 0.07% 37.75% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1415539 62.25% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2274123 # Class of committed instruction +system.cpu.commit.refs 1417174 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1343403 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 2274104 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 9.804606 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.804606 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 9350428 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 226 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 77569 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2473522 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 94627 # Number of cycles decode is idle +system.cpu.decode.RunCycles 91391 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3247 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 222392 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 83857 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 165626 # Number of cache lines fetched +system.cpu.fetch.Cycles 9580362 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 474 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1144257 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6940 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.008553 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 178206 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 80767 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.116706 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.265638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.361026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9355453 95.83% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 462 0.00% 95.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 81714 0.84% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 306 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 404 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 356 0.00% 96.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 80930 0.83% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 288 0.00% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 242172 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 536 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 76341 # Number of branches executed +system.cpu.iew.exec_nop 39 # number of nop insts executed +system.cpu.iew.exec_rate 0.247066 # Inst execution rate +system.cpu.iew.exec_refs 1509552 # number of memory reference insts executed +system.cpu.iew.exec_stores 1507002 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 12538 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2762 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1507465 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2424933 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2550 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 596 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2422384 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3565955 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3563309 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 138537 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 25 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1127 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 91926 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 431 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1315617 # num instructions consuming a value +system.cpu.iew.wb_count 2385368 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.470059 # average fanout of values written-back +system.cpu.iew.wb_producers 618418 # num instructions producing a value +system.cpu.iew.wb_rate 0.243290 # insts written-back per cycle +system.cpu.iew.wb_sent 2422037 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2500193 # number of integer regfile reads +system.cpu.int_regfile_writes 838779 # number of integer regfile writes +system.cpu.ipc 0.101993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.101993 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 912819 37.67% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 2 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 61 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 92 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 84 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2674 0.11% 37.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1507117 62.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2422980 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014892 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98 0.27% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.01% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 50 0.14% 0.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35929 99.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 994108 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 11750159 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 987126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1060881 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2424861 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2422980 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 138838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 9762085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.248203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.908083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8884365 91.01% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186986 1.92% 92.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 293038 3.00% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119100 1.22% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 160453 1.64% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73781 0.76% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 32145 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8705 0.09% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3512 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 9762085 # Number of insts issued each cycle +system.cpu.iq.rate 0.247126 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1464935 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2894045 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1398242 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1514819 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2762 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1507465 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 4684140 # number of misc regfile reads +system.cpu.misc_regfile_writes 60 # number of misc regfile writes +system.cpu.numCycles 9804616 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3576234 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1001630 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 196981 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 7051196 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2436342 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1070903 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 210854 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5679127 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3247 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5771799 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 69269 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2514763 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 102 # count of serializing insts renamed +system.cpu.rename.skidInsts 1791068 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1436706 # Number of vector rename lookups +system.cpu.rob.rob_reads 12098844 # The number of ROB reads +system.cpu.rob.rob_writes 4797353 # The number of ROB writes +system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1429226 # number of vector regfile reads +system.cpu.vec_regfile_writes 352 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 144291 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 321752 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 176581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 354068 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 391 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144072 # Transaction distribution +system.membus.trans_dist::CleanEvict 219 # Transaction distribution +system.membus.trans_dist::ReadExReq 173888 # Transaction distribution +system.membus.trans_dist::ReadExResp 173887 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 177461 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 177461 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 177461 # Request fanout histogram +system.membus.reqLayer0.occupancy 936460000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 19.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 907473250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 656 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 320411 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 151 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 701 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 173890 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 173887 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 542 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2941 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 530317 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 531552 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 44352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 22421760 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 22466112 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 144682 # Total snoops (count) +system.tol2bus.snoopTraffic 9220608 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 322169 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001217 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.034861 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 321777 99.88% 99.88% # Request fanout histogram +system.tol2bus.snoop_fanout::1 392 0.12% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 322169 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 353524000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.2 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 262472000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 813000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 23 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 24 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 23 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 24 # number of overall hits +system.l2.demand_misses::.cpu.inst 519 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 174003 # number of demand (read+write) misses +system.l2.demand_misses::total 174522 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 519 # number of overall misses +system.l2.overall_misses::.cpu.data 174003 # number of overall misses +system.l2.overall_misses::total 174522 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40762500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 17963265500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 18004028000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40762500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 17963265500 # number of overall miss cycles +system.l2.overall_miss_latency::total 18004028000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 542 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 174004 # number of demand (read+write) accesses +system.l2.demand_accesses::total 174546 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 542 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 174004 # number of overall (read+write) accesses +system.l2.overall_accesses::total 174546 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.957565 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999994 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.999863 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.957565 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999994 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.999863 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.demand_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.overall_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 144072 # number of writebacks +system.l2.writebacks::total 144072 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 174003 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 174522 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 174003 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 174522 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35572500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 16223265500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 16258838000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35572500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 16223265500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 16258838000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.999863 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.999863 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.replacements 144682 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 151 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 151 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 151 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 151 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 173890 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 173890 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18824.209453 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18824.209453 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 30365.095360 # Cycle average of tags in use +system.l2.tags.total_refs 351123 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 177450 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.978715 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 496.663908 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 68.643613 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 29799.787838 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.015157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.002095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.909417 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.926669 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 3120 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 29304 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 3009986 # Number of tag accesses +system.l2.tags.data_accesses 3009986 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 11136064 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11169280 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 9220608 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9220608 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 174001 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 174520 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 144072 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 144072 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 6775585 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2271596386 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2278371971 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1880870998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 6775585 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2271596386 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4159242969 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 144072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 174001.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000010576500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 9000 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 9000 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 438695 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 135333 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 174520 # Number of read requests accepted +system.mem_ctrls.writeReqs 144072 # Number of write requests accepted +system.mem_ctrls.readBursts 174520 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 144072 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 10869 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10878 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10850 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 10895 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 10938 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10907 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10846 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10863 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10898 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 11015 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10962 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10944 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 8964 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9014 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9013 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8966 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8980 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9024 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9067 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8960 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 23.69 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 5679206250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 872600000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 8951456250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 32541.86 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 51291.86 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 161227 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 132655 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.08 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 174520 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 144072 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 47549 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 46137 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 50896 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29930 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 365 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2640 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 8814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9125 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9139 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9752 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9591 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 10159 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 9576 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 10617 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13932 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14020 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 10969 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 10027 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 9450 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 171 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 24680 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 826.069368 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 676.795020 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 328.058619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1587 6.43% 6.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1443 5.85% 12.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 890 3.61% 15.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 501 2.03% 17.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 902 3.65% 21.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 405 1.64% 23.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1154 4.68% 27.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3458 14.01% 41.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 14340 58.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 24680 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 9000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.390222 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.723502 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 342.009805 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8999 99.99% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 9000 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 9000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.005111 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.004843 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.096479 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 8971 99.68% 99.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.16% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 13 0.14% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 0.02% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 9000 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 11169280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9218944 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11169280 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9220608 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2278.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1880.53 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2278.37 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1880.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 32.49 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 17.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.69 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 4902290500 # Total gap between requests +system.mem_ctrls.avgGap 15387.36 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 11136064 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 9218944 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 6775584.762889721431 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2271596385.987619400024 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1880531566.002336740494 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 174001 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 144072 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14227250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8937229000 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 108442678250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27412.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 51363.09 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 752697.81 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.24 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 88129020 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 46826505 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 624564360 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 377035380 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 1662343440 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 482617920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 3668125185 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 748.244614 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 1206855250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 3531912250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 88114740 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 46834095 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 621508440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 374884740 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 1648007370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 494690400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 3660648345 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 746.719447 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1234393250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 3504374250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 164918 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 164918 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 164918 # number of overall hits +system.cpu.icache.overall_hits::total 164918 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 708 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 708 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 708 # number of overall misses +system.cpu.icache.overall_misses::total 708 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 52243997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52243997 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 165626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 165626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 165626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 165626 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.004275 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004275 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.004275 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004275 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 73790.956215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73790.956215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 73790.956215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73790.956215 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.090909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 151 # number of writebacks +system.cpu.icache.writebacks::total 151 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 542 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 542 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 542 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 542 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41828997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41828997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41828997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41828997 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77175.271218 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77175.271218 # average overall mshr miss latency +system.cpu.icache.replacements 151 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 164918 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 164918 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 708 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 708 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 52243997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52243997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 165626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 165626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.004275 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004275 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 73790.956215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73790.956215 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 542 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 41828997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41828997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77175.271218 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 389.915117 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 165460 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 305.276753 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 389.915117 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.761553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.761553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 391 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 331794 # Number of tag accesses +system.cpu.icache.tags.data_accesses 331794 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 216139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 216163 # number of overall hits +system.cpu.dcache.overall_hits::total 216163 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1201775 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1201775 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1201777 # number of overall misses +system.cpu.dcache.overall_misses::total 1201777 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 91412553393 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91412553393 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 91412553393 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91412553393 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 1417914 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1417914 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 1417940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1417940 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.847566 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.847566 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.847551 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.847551 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 76064.615584 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76064.615584 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 76064.488997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76064.488997 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8299840 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 142444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.267389 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 176339 # number of writebacks +system.cpu.dcache.writebacks::total 176339 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1024832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1024832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1024832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1024832 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 176943 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176943 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 176945 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176945 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 18377267996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18377267996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 18377452996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18377452996 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.124791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.124791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.124790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.124790 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 103859.819241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103859.819241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 103859.690842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103859.690842 # average overall mshr miss latency +system.cpu.dcache.replacements 176430 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 2129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2129 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 260 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 260 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 19004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 2389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 214010 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 214010 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1201508 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1201508 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 91393326895 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91393326895 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 1415518 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1415518 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.848812 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.848812 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 76065.516746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76065.516746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1024683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1024683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 176825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 176825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 18367761998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18367761998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.124919 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.124919 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 103875.368291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103875.368291 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 24 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 24 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.076923 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.076923 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.076923 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.076923 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 509.260955 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 393134 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 176942 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 2.221824 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 509.260955 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3012882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3012882 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 4902307500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/leslie3d/config.ini b/TAGE_SC_L/leslie3d/config.ini new file mode 100644 index 000000000..b2f5844d6 --- /dev/null +++ b/TAGE_SC_L/leslie3d/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] 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+[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//data/ref/input/leslie3d.in +kvmInSE=false +maxStackSize=67108864 +output=leslie3d.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 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+type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/leslie3d/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/leslie3d/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/leslie3d/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/leslie3d/config.json b/TAGE_SC_L/leslie3d/config.json new file mode 100644 index 000000000..589ad4ae9 --- /dev/null +++ b/TAGE_SC_L/leslie3d/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": 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"system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/leslie3d/fs/proc/cpuinfo b/TAGE_SC_L/leslie3d/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/leslie3d/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/leslie3d/fs/proc/stat b/TAGE_SC_L/leslie3d/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/leslie3d/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/online b/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/leslie3d/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/leslie3d/leslie3d.stdout b/TAGE_SC_L/leslie3d/leslie3d.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/leslie3d/stats.txt b/TAGE_SC_L/leslie3d/stats.txt new file mode 100644 index 000000000..ea3e1834f --- /dev/null +++ b/TAGE_SC_L/leslie3d/stats.txt @@ -0,0 +1,1375 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 633191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 108548 # Simulator instruction rate (inst/s) +host_mem_usage 858084 # Number of bytes of host memory used +host_op_rate 111494 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.21 # Real time elapsed on the host +host_tick_rate 68729715 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1027168 # Number of ops (including micro ops) simulated +sim_seconds 0.000633 # Number of seconds simulated +sim_ticks 633191500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.331508 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 271326 # Number of BTB hits +system.cpu.branchPred.BTBLookups 273152 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4136 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 288777 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1729 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2702 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 973 # Number of indirect misses. +system.cpu.branchPred.lookups 303846 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 220585 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 15411 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14913 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 221083 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 71 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6676 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4222 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 97 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 176 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 7184 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 8627 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 175 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 149 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 14793 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 24269 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 123 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1754 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 31282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 50224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 45 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2133 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 12495 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 863 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 2717 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 4338 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 548 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 435 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 273 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 33753 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 811 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 5603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4512 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5240 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 7180 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 681 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2024 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 6802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 14803 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 126 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 24296 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 31283 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 31 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 50204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 14495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 315 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 830 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 7160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 176080 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 124 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1242 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 5816 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 229 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 741872 # number of cc regfile reads +system.cpu.cc_regfile_writes 745941 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3517 # The number of times a branch was mispredicted +system.cpu.commit.branches 247012 # Number of branches committed +system.cpu.commit.bw_lim_events 10828 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 105898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002022 # Number of instructions committed +system.cpu.commit.committedOps 1029189 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1184416 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.868942 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.633643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 852717 71.99% 71.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 86958 7.34% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26662 2.25% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38740 3.27% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 162261 13.70% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2540 0.21% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1651 0.14% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2059 0.17% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10828 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1184416 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 4620 # Number of function calls committed. +system.cpu.commit.int_insts 800492 # Number of committed integer instructions. +system.cpu.commit.loads 35378 # Number of loads committed +system.cpu.commit.membars 138 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 3 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756594 73.51% 73.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 384 0.04% 73.55% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 94 0.01% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 15 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 10 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 12 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 72 0.01% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 35378 3.44% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 236587 22.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1029189 # Class of committed instruction +system.cpu.commit.refs 271965 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2101 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1027168 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.266383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.266383 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 939021 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 633 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 256856 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1193254 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 81548 # Number of cycles decode is idle +system.cpu.decode.RunCycles 122138 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4010 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2198 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 52729 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 303846 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 33096 # Number of cache lines fetched +system.cpu.fetch.Cycles 1134130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1231249 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9258 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239932 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 60555 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 278871 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.972256 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.054599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.921750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 900384 75.07% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5040 0.42% 75.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4823 0.40% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6304 0.53% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 251564 20.97% 97.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5198 0.43% 97.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2375 0.20% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5224 0.44% 98.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18534 1.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 66938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4018 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 266820 # Number of branches executed +system.cpu.iew.exec_nop 3248 # number of nop insts executed +system.cpu.iew.exec_rate 0.883459 # Inst execution rate +system.cpu.iew.exec_refs 295165 # number of memory reference insts executed +system.cpu.iew.exec_stores 254519 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 11776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 41845 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 258911 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1147285 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40646 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1118798 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 5041 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4010 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5055 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 16436 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2895 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 6467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 22322 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1721 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1445197 # num instructions consuming a value +system.cpu.iew.wb_count 1105084 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.389950 # average fanout of values written-back +system.cpu.iew.wb_producers 563554 # num instructions producing a value +system.cpu.iew.wb_rate 0.872629 # insts written-back per cycle +system.cpu.iew.wb_sent 1116457 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1374875 # number of integer regfile reads +system.cpu.int_regfile_writes 605717 # number of integer regfile writes +system.cpu.ipc 0.789651 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.789651 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 827002 73.50% 73.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385 0.03% 73.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 96 0.01% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 43 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 21 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 14 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 79 0.01% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41481 3.69% 77.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 256057 22.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1125209 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3779 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003358 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1189 31.46% 31.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.03% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.03% 31.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.05% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1706 45.14% 76.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 880 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1126587 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3449247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1102914 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1258414 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1143825 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1125209 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 212 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 116860 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 269 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 67635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1199446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.938107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.588111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 834403 69.57% 69.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 57645 4.81% 74.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59296 4.94% 79.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 79441 6.62% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 149085 12.43% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9168 0.76% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6069 0.51% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2657 0.22% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1682 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1199446 # Number of insts issued each cycle +system.cpu.iq.rate 0.888521 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2397 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 4664 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2170 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2523 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1322 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 41845 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258911 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 837113 # number of misc regfile reads +system.cpu.misc_regfile_writes 561 # number of misc regfile writes +system.cpu.numCycles 1266384 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 17199 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1240714 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 76 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 110111 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1532 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2211765 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1167418 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1407025 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 145021 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 898782 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4010 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 902303 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 166281 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1427211 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20802 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 866 # count of serializing insts renamed +system.cpu.rename.skidInsts 403798 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 212 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 2276 # Number of vector rename lookups +system.cpu.rob.rob_reads 2302630 # The number of ROB reads +system.cpu.rob.rob_writes 2285280 # The number of ROB writes +system.cpu.timesIdled 955 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2115 # number of vector regfile reads +system.cpu.vec_regfile_writes 186 # number of vector regfile writes +system.cpu.workload.numSyscalls 35 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 27415 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 27242 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 55462 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 1 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 981 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1 # Transaction distribution +system.membus.trans_dist::CleanEvict 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 26347 # Transaction distribution +system.membus.trans_dist::ReadExResp 26347 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 981 # Transaction distribution +system.membus.trans_dist::InvalidateReq 81 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 27409 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 27409 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 27409 # Request fanout histogram +system.membus.reqLayer0.occupancy 38625500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 142095500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1786 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 26011 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1033 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 205 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 26353 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 26350 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1496 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 290 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 81 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 81 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4025 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 79654 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 83679 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 161856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 3369600 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 3531456 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 7 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 28227 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000177 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013308 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 28222 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 5 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 28227 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 54774000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 8.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 40000500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2244000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 663 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 147 # number of demand (read+write) hits +system.l2.demand_hits::total 810 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 663 # number of overall hits +system.l2.overall_hits::.cpu.data 147 # number of overall hits +system.l2.overall_hits::total 810 # number of overall hits +system.l2.demand_misses::.cpu.inst 833 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 26496 # number of demand (read+write) misses +system.l2.demand_misses::total 27329 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 833 # number of overall misses +system.l2.overall_misses::.cpu.data 26496 # number of overall misses +system.l2.overall_misses::total 27329 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 65230000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1988340500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 2053570500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 65230000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1988340500 # number of overall miss cycles +system.l2.overall_miss_latency::total 2053570500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1496 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 26643 # number of demand (read+write) accesses +system.l2.demand_accesses::total 28139 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1496 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 26643 # number of overall (read+write) accesses +system.l2.overall_accesses::total 28139 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.556818 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.994483 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.971214 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.556818 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.994483 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.971214 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1 # number of writebacks +system.l2.writebacks::total 1 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 833 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 26496 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 27329 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 833 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 26496 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 27329 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 56900000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1723390500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1780290500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 56900000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1723390500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1780290500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.971214 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.971214 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.replacements 7 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1031 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1031 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1031 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1031 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 5 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 5 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 26348 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 26348 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 81 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 81 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18827.160494 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18827.160494 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 12249.229006 # Cycle average of tags in use +system.l2.tags.total_refs 55376 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 27409 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.020358 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 68.558691 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 789.028674 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 11391.641641 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.002092 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.024079 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.347645 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.373817 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 27402 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4388 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 22522 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.836243 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 471073 # Number of tag accesses +system.l2.tags.data_accesses 471073 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 53312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1695680 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1748992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 64 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 64 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 833 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 26495 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 27328 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 84195698 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2677989202 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2762184900 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 101075 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 84195698 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2677989202 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2762285975 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 833.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 26495.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 54769 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 27328 # Number of read requests accepted +system.mem_ctrls.writeReqs 1 # Number of write requests accepted +system.mem_ctrls.readBursts 27328 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1772 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1704 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1666 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1604 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1597 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1622 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1620 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1697 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1766 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1832 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1740 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1725 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1755 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1692 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.76 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.09 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 140438500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 136640000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 652838500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5139.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 23889.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 25352 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.77 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 27328 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7425 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7778 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 9212 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 2906 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an 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does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 885.495441 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 752.763476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.372978 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 104 5.27% 5.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 85 4.31% 9.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 66 3.34% 12.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23 1.17% 14.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 46 2.33% 16.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.46% 16.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 33 1.67% 18.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 11 0.56% 19.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1597 80.90% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1748992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1748992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 64 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2762.18 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2762.18 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 21.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 633124500 # Total gap between requests +system.mem_ctrls.avgGap 23166.76 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 53312 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1695680 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 84195697.510152921081 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2677989202.318729877472 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 833 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 26495 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 22622500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 630216000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27157.86 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 23786.22 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 0.00 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.77 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 7339920 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 3901260 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 99817200 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 177114390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 93996960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 431955570 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 682.187885 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 236432000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 21060000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 375699500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6768720 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3590070 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 95304720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 172093830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 98224800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 425767980 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 672.415817 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 249295750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 21060000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 362835750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 31326 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 31326 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 31326 # number of overall hits +system.cpu.icache.overall_hits::total 31326 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1769 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1769 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1769 # number of overall misses +system.cpu.icache.overall_misses::total 1769 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 90817500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90817500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 90817500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90817500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 33095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 33095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 33095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 33095 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.053452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.053452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.053452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.053452 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 51338.326738 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51338.326738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 51338.326738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51338.326738 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 618 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1033 # number of writebacks +system.cpu.icache.writebacks::total 1033 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 273 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 273 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 273 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1496 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1496 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1496 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1496 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 74571000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74571000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 74571000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74571000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.045203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.045203 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.045203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.045203 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 49846.925134 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49846.925134 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 49846.925134 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49846.925134 # average overall mshr miss latency +system.cpu.icache.replacements 1033 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 31326 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 31326 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1769 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1769 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 90817500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 90817500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 33095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 33095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.053452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.053452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 51338.326738 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51338.326738 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 273 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1496 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1496 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 74571000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74571000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.045203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.045203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 49846.925134 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49846.925134 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 449.129917 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32822 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1496 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.939840 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 449.129917 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.877207 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.877207 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 463 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.904297 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 67686 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67686 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 61864 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 61864 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 62000 # number of overall hits +system.cpu.dcache.overall_hits::total 62000 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 210841 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 210841 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 210849 # number of overall misses +system.cpu.dcache.overall_misses::total 210849 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 13170301576 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13170301576 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 13170301576 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13170301576 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 272705 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 272705 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 272849 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 272849 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.773147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.773147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.772768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.772768 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 62465.562087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62465.562087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62463.192028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62463.192028 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 892592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.233188 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 26010 # number of writebacks +system.cpu.dcache.writebacks::total 26010 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 184126 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 184126 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 184126 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 184126 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 26715 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 26715 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 26723 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 26723 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 2038779468 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2038779468 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 2039394468 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2039394468 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.097963 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097963 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.097941 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097941 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 76315.907468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76315.907468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 76316.074842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76316.074842 # average overall mshr miss latency +system.cpu.dcache.replacements 26209 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 35615 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 35615 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 628 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 628 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 31112000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31112000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 36243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 36243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.017327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 49541.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49541.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 347 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 281 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 13819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.007753 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007753 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 49179.715302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49179.715302 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 26205 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 26205 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 210155 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 210155 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 13137349603 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13137349603 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 236360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 236360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.889131 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.889131 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 62512.667331 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62512.667331 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 183779 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 183779 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 26376 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 26376 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 144 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 144 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.055556 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.055556 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 8 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 8 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 615000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 615000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.477586 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 89018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 26721 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.331387 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.477586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 573017 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 573017 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 633191500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/libquantum/config.ini b/TAGE_SC_L/libquantum/config.ini new file mode 100644 index 000000000..8464759b4 --- /dev/null +++ b/TAGE_SC_L/libquantum/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 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"name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/libquantum/fs/proc/cpuinfo b/TAGE_SC_L/libquantum/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/libquantum/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/libquantum/fs/proc/stat b/TAGE_SC_L/libquantum/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/libquantum/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/online b/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/libquantum/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/libquantum/ref.out b/TAGE_SC_L/libquantum/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/libquantum/stats.txt b/TAGE_SC_L/libquantum/stats.txt new file mode 100644 index 000000000..15d4b2471 --- /dev/null +++ b/TAGE_SC_L/libquantum/stats.txt @@ -0,0 +1,1358 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 156283000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 144174 # Simulator instruction rate (inst/s) +host_mem_usage 850908 # Number of bytes of host memory used +host_op_rate 147016 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.94 # Real time elapsed on the host +host_tick_rate 22531359 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1019736 # Number of ops (including micro ops) simulated +sim_seconds 0.000156 # Number of seconds simulated +sim_ticks 156283000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.556468 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118292 # Number of BTB hits +system.cpu.branchPred.BTBLookups 118819 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 917 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 143507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 16 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 223 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 207 # Number of indirect misses. +system.cpu.branchPred.lookups 158035 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 35991 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 103468 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 35878 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 103581 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 86 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 9243 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 52 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 212 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 113 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8355 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 456 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 907 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 78 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 16839 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1144 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 605 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 26857 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 23350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 909 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 356 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 51 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 45800 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 413 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 76 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 373 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 74 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 29 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 8684 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 127 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 968 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 16840 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1250 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 688 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1102 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 27054 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 873 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1098 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 24756 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 92619 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 85 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 629 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 55 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 369735 # number of cc regfile reads +system.cpu.cc_regfile_writes 385833 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 671 # The number of times a branch was mispredicted +system.cpu.commit.branches 152825 # Number of branches committed +system.cpu.commit.bw_lim_events 48481 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 56 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14700 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000086 # Number of instructions committed +system.cpu.commit.committedOps 1019822 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 267479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.812718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.461220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92809 34.70% 34.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 26484 9.90% 44.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9629 3.60% 48.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 5117 1.91% 50.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2873 1.07% 51.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4221 1.58% 52.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6771 2.53% 55.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71094 26.58% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 48481 18.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267479 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 374 # Number of function calls committed. +system.cpu.commit.int_insts 810700 # Number of committed integer instructions. +system.cpu.commit.loads 256050 # Number of loads committed +system.cpu.commit.membars 48 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 10 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 571430 56.03% 56.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6238 0.61% 56.64% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.00% 56.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 4094 0.40% 57.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 15846 1.55% 58.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 6163 0.60% 59.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 21987 2.16% 61.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21987 2.16% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 22 0.00% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 2070 0.20% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 32 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 37 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 40 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2082 0.20% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 256050 25.11% 89.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 111727 10.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1019822 # Class of committed instruction +system.cpu.commit.refs 367777 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 110708 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1019736 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.312568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.312568 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 69648 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 118068 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1040742 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 47684 # Number of cycles decode is idle +system.cpu.decode.RunCycles 140140 # Number of cycles decode is running +system.cpu.decode.SquashCycles 713 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 839 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 11559 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 158035 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 42789 # Number of cache lines fetched +system.cpu.fetch.Cycles 215002 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 516 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1025109 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1918 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.505602 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 53749 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 118937 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.279635 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 269744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.883860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.387563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102170 37.88% 37.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9565 3.55% 41.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6294 2.33% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5938 2.20% 45.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5209 1.93% 47.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6036 2.24% 50.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12883 4.78% 54.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 93825 34.78% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27824 10.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269744 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 154172 # Number of branches executed +system.cpu.iew.exec_nop 130 # number of nop insts executed +system.cpu.iew.exec_rate 3.294656 # Inst execution rate +system.cpu.iew.exec_refs 371135 # number of memory reference insts executed +system.cpu.iew.exec_stores 112764 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2318 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 258513 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 113591 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1034781 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 258371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1104 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1029804 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2877 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 713 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2932 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 569 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 140 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 78 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2438 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 557 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1277106 # num instructions consuming a value +system.cpu.iew.wb_count 1027868 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.577195 # average fanout of values written-back +system.cpu.iew.wb_producers 737139 # num instructions producing a value +system.cpu.iew.wb_rate 3.288462 # insts written-back per cycle +system.cpu.iew.wb_sent 1028662 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1294575 # number of integer regfile reads +system.cpu.int_regfile_writes 665220 # number of integer regfile writes +system.cpu.ipc 3.199304 # IPC: Instructions Per Cycle +system.cpu.ipc_total 3.199304 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 578607 56.13% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6240 0.61% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 9 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4094 0.40% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15852 1.54% 58.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 6163 0.60% 59.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 21995 2.13% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 21995 2.13% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 22 0.00% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 2072 0.20% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 38 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2087 0.20% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 258670 25.09% 89.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 112972 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1030912 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5321 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005161 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 519 9.75% 9.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.02% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2475 46.51% 56.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 195 3.66% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 5 0.09% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.02% 60.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.04% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1818 34.17% 94.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 305 5.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 922482 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2112204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 917053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 937630 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1034581 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1030912 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11951 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 269744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.821816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.843448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 61206 22.69% 22.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17814 6.60% 29.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21088 7.82% 37.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22536 8.35% 45.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26893 9.97% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24003 8.90% 64.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18524 6.87% 71.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 56857 21.08% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 20823 7.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269744 # Number of insts issued each cycle +system.cpu.iq.rate 3.298201 # Inst issue rate +system.cpu.iq.vec_alu_accesses 113740 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 224805 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 110815 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 111851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2064 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2465 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 258513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 113591 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 948337 # number of misc regfile reads +system.cpu.misc_regfile_writes 70292 # number of misc regfile writes +system.cpu.numCycles 312568 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 5775 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1206644 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4616 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 53304 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 6698 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2146469 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1038011 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1225360 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 146000 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 40512 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 713 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 55711 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 18540 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1304214 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 8241 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 282 # count of serializing insts renamed +system.cpu.rename.skidInsts 60610 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 171953 # Number of vector rename lookups +system.cpu.rob.rob_reads 1253156 # The number of ROB reads +system.cpu.rob.rob_writes 2071426 # The number of ROB writes +system.cpu.timesIdled 418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 171247 # number of vector regfile reads +system.cpu.vec_regfile_writes 94563 # number of vector regfile writes +system.cpu.workload.numSyscalls 7 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1859 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 5706 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 12316 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 615 # Transaction distribution +system.membus.trans_dist::ReadExReq 698 # Transaction distribution +system.membus.trans_dist::ReadExResp 698 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 615 # Transaction distribution +system.membus.trans_dist::InvalidateReq 546 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1859 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1859 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1859 # Request fanout histogram +system.membus.reqLayer0.occupancy 2153000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 6928250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2880 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 5434 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 135 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 137 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2357 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 568 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 568 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1185 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 17739 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 18924 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 700736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 742976 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6610 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000151 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012300 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6609 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6610 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 11727000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.5 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8556500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 12 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4717 # number of demand (read+write) hits +system.l2.demand_hits::total 4729 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 12 # number of overall hits +system.l2.overall_hits::.cpu.data 4717 # number of overall hits +system.l2.overall_hits::total 4729 # number of overall hits +system.l2.demand_misses::.cpu.inst 513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 800 # number of demand (read+write) misses +system.l2.demand_misses::total 1313 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 513 # number of overall misses +system.l2.overall_misses::.cpu.data 800 # number of overall misses +system.l2.overall_misses::total 1313 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40757500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 61617000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 102374500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40757500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 61617000 # number of overall miss cycles +system.l2.overall_miss_latency::total 102374500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 525 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5517 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6042 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 525 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5517 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6042 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.977143 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.145006 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.217312 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.977143 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.145006 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.217312 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.demand_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.overall_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 800 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 800 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35627500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 53617000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 89244500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35627500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 53617000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 89244500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.217312 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.217312 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 135 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 135 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 135 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 135 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 2462 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 2462 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 698 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 698 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 22 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 22 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 546 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 546 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19130.036630 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19130.036630 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1068.548216 # Cycle average of tags in use +system.l2.tags.total_refs 11769 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1879 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 6.263438 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 265.121704 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 444.344216 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 359.082296 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.008091 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013560 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.010958 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.032610 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1857 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 954 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.056671 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 100399 # Number of tag accesses +system.l2.tags.data_accesses 100399 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51200 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 84032 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 800 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1313 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 210080431 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 327610809 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 537691240 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 210080431 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 327610809 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 537691240 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 800.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000574000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2616 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1313 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1313 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 157 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 117 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 104 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 142 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 41 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 103 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10714750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6565000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 35333500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8160.51 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26910.51 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1092 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 83.17 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1313 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 688 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 427 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 156 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 221 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 380.235294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 226.255947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 366.440593 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 64 28.96% 28.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 47 21.27% 50.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 38 17.19% 67.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 6 2.71% 70.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 2.71% 72.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 3.62% 76.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.71% 79.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.26% 81.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 18.55% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 221 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 84032 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 84032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 537.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 537.69 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 153415000 # Total gap between requests +system.mem_ctrls.avgGap 116843.11 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51200 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 210080431.012970060110 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 327610808.597224235535 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 800 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14512750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 20820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28289.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26025.94 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 642600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 341550 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 5776260 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 12292800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 37806390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 28176000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 85035600 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 544.112923 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 72846750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 5200000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 78236250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 935340 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 497145 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3598560 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 12292800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 30736680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 34129440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 82189965 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 525.904705 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 88357250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 5200000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 62725750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 42116 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 42116 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 42116 # number of overall hits +system.cpu.icache.overall_hits::total 42116 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 672 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 672 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 672 # number of overall misses +system.cpu.icache.overall_misses::total 672 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 51529999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51529999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 51529999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51529999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 42788 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 42788 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 42788 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 42788 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.015705 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015705 # miss rate for demand accesses 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+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 135 # number of writebacks +system.cpu.icache.writebacks::total 135 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 525 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 525 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41683999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41683999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41683999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41683999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.012270 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.012270 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.012270 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.012270 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79398.093333 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79398.093333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79398.093333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79398.093333 # average overall mshr miss latency +system.cpu.icache.replacements 135 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 42116 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 42116 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 672 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 672 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 51529999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51529999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 42788 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 42788 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.015705 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015705 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76681.546131 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76681.546131 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 41683999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41683999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.012270 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012270 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79398.093333 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79398.093333 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 344.224798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 42641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 81.220952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 344.224798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.672314 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.672314 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 357 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 86101 # Number of tag accesses +system.cpu.icache.tags.data_accesses 86101 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 318979 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 318979 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 319002 # number of overall hits +system.cpu.dcache.overall_hits::total 319002 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 50296 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 50296 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 50298 # number of overall misses +system.cpu.dcache.overall_misses::total 50298 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 928146470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 928146470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 928146470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 928146470 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 369275 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 369275 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 369300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 369300 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.136202 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.136202 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.136198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.136198 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 18453.683593 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18453.683593 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 18452.949819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18452.949819 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12602 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.450952 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 5434 # number of writebacks +system.cpu.dcache.writebacks::total 5434 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 44213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44213 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6083 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6083 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 6085 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 6085 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 137102554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137102554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 137265054 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137265054 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.016473 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016473 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.016477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016477 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 22538.641131 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22538.641131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 22557.938209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22557.938209 # average overall mshr miss latency +system.cpu.dcache.replacements 5571 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 250218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 250218 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 7375 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7375 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 89676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 257593 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 257593 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.028630 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.028630 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 12159.525424 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12159.525424 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 5020 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5020 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 2355 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2355 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 35938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.009142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 111118 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 111118 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.381198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 19372.725554 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19372.725554 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 39193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 39193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3165 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3165 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 83846993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83846993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.028483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.028483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 436.655859 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 325186 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6083 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 53.458162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 436.655859 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 450 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 744889 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 744889 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 156283000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/mcf/config.ini b/TAGE_SC_L/mcf/config.ini new file mode 100644 index 000000000..0adf5f92a --- /dev/null +++ b/TAGE_SC_L/mcf/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + 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+pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//data/ref/input/inp.in +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=inp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/mcf/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/mcf/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/mcf/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/mcf/config.json b/TAGE_SC_L/mcf/config.json new file mode 100644 index 000000000..5d3948919 --- /dev/null +++ b/TAGE_SC_L/mcf/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/mcf/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/mcf/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/mcf/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": 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"/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", + "cwd": "/home/min/a/bnwachuk/Final/gem5", + "pgid": 100, + "simpoint": 0, + "euid": 100, + "input": "cin", + "path": "system.cpu.workload", + "name": "workload", + "cmd": [ + "/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross", + "/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//data/ref/input/inp.in" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "release": "5.1.0", + "output": "inp.out" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "decodeToFetchDelay": 1, + "renameWidth": 8, + "numThreads": 1, + "syscallRetryLatency": 10000, + "squashWidth": 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"issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": 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"is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": 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"tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/mcf/fs/proc/cpuinfo b/TAGE_SC_L/mcf/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/mcf/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/mcf/fs/proc/stat b/TAGE_SC_L/mcf/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/mcf/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/online b/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/mcf/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/mcf/inp.out b/TAGE_SC_L/mcf/inp.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/mcf/stats.txt b/TAGE_SC_L/mcf/stats.txt new file mode 100644 index 000000000..c1114285c --- /dev/null +++ b/TAGE_SC_L/mcf/stats.txt @@ -0,0 +1,1361 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 500536000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 116814 # Simulator instruction rate (inst/s) +host_mem_usage 850896 # Number of bytes of host memory used +host_op_rate 132512 # Simulator op (including micro ops) rate (op/s) +host_seconds 8.56 # Real time elapsed on the host +host_tick_rate 58468041 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1134416 # Number of ops (including micro ops) simulated +sim_seconds 0.000501 # Number of seconds simulated +sim_ticks 500536000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.358374 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 92293 # Number of BTB hits +system.cpu.branchPred.BTBLookups 92889 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 809 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 181500 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3097 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3299 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 202 # Number of indirect misses. +system.cpu.branchPred.lookups 226647 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 118031 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60367 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 116682 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61716 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6619 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4134 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 2960 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 4214 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 600 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1232 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 602 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 594 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 563 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 69 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 31 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 23 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 154608 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 346 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1189 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 5426 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 4062 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 596 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1232 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 602 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 594 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 224 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 23041 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 38 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 11371 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 469065 # number of cc regfile reads +system.cpu.cc_regfile_writes 445002 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 567 # The number of times a branch was mispredicted +system.cpu.commit.branches 222072 # Number of branches committed +system.cpu.commit.bw_lim_events 63204 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14510 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000623 # Number of instructions committed +system.cpu.commit.committedOps 1135038 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 921910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.231181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320907 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 599089 64.98% 64.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 111489 12.09% 77.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 58121 6.30% 83.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 30329 3.29% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25620 2.78% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7612 0.83% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 14974 1.62% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11472 1.24% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63204 6.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 921910 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 10970 # Number of function calls committed. +system.cpu.commit.int_insts 986971 # Number of committed integer instructions. +system.cpu.commit.loads 170934 # Number of loads committed +system.cpu.commit.membars 1232 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 830 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 769661 67.81% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6011 0.53% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1895 0.17% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 1893 0.17% 68.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 1668 0.15% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2267 0.20% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 170934 15.06% 84.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 179876 15.85% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1135038 # Class of committed instruction +system.cpu.commit.refs 350810 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 19901 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1134416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.001072 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.001072 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 369143 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 245 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 92282 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1154444 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 337025 # Number of cycles decode is idle +system.cpu.decode.RunCycles 207687 # Number of cycles decode is running +system.cpu.decode.SquashCycles 679 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 9570 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 226647 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 151079 # Number of cache lines fetched +system.cpu.fetch.Cycles 515682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 503 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1024163 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1842 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.226404 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 407448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 106761 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.023065 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 924104 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.529422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 694266 75.13% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24064 2.60% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21313 2.31% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29222 3.16% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 37715 4.08% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20366 2.20% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6389 0.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 10142 1.10% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 80627 8.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 924104 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 76969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 223488 # Number of branches executed +system.cpu.iew.exec_nop 654 # number of nop insts executed +system.cpu.iew.exec_rate 1.165904 # Inst execution rate +system.cpu.iew.exec_refs 376201 # number of memory reference insts executed +system.cpu.iew.exec_stores 181843 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2328 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 172837 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1266 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 182525 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1150122 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 194358 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 818 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1167155 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 11080 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11091 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 1371 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10811 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16776 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1902 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 170 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1099277 # num instructions consuming a value +system.cpu.iew.wb_count 1144060 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.512096 # average fanout of values written-back +system.cpu.iew.wb_producers 562935 # num instructions producing a value +system.cpu.iew.wb_rate 1.142834 # insts written-back per cycle +system.cpu.iew.wb_sent 1144769 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1326039 # number of integer regfile reads +system.cpu.int_regfile_writes 763044 # number of integer regfile writes +system.cpu.ipc 0.998929 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.998929 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 848 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 776608 66.49% 66.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6014 0.51% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1951 0.17% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1948 0.17% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1706 0.15% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2303 0.20% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 194587 16.66% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 182006 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1167974 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 28747 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024613 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6136 21.34% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 21.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7980 27.76% 49.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 14627 50.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1174093 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3246005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1123907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1143560 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1148202 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1167974 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15046 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 924104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.263899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.974668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 558743 60.46% 60.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 87176 9.43% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72815 7.88% 77.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64315 6.96% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49642 5.37% 90.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39656 4.29% 94.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27197 2.94% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14287 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10273 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 924104 # Number of insts issued each cycle +system.cpu.iq.rate 1.166722 # Inst issue rate +system.cpu.iq.vec_alu_accesses 21780 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 42868 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 20153 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 20989 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 16339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7820 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 172837 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 182525 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 795052 # number of misc regfile reads +system.cpu.misc_regfile_writes 4929 # number of misc regfile writes +system.cpu.numCycles 1001073 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 10901 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1211210 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 5977 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 340701 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 119 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1857450 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1152162 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1227536 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 214110 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 97675 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 679 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 108200 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 16315 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1311537 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 249513 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3792 # count of serializing insts renamed +system.cpu.rename.skidInsts 38106 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 24991 # Number of vector rename lookups +system.cpu.rob.rob_reads 2007201 # The number of ROB reads +system.cpu.rob.rob_writes 2301310 # The number of ROB writes +system.cpu.timesIdled 7434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 24540 # number of vector regfile reads +system.cpu.vec_regfile_writes 10206 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4607 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15831 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 32533 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1281 # Transaction distribution +system.membus.trans_dist::ReadExReq 3311 # Transaction distribution +system.membus.trans_dist::ReadExResp 3311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1281 # Transaction distribution +system.membus.trans_dist::InvalidateReq 15 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4607 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4607 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4607 # Request fanout histogram +system.membus.reqLayer0.occupancy 5392000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 23805750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 13349 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4041 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 10990 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 800 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 11349 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2000 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 15 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 15 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 33688 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15547 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 49235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 1429696 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 600256 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2029952 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 16702 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000060 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.007738 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 16701 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 16702 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31297500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8014500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 17023500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 10829 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1266 # number of demand (read+write) hits +system.l2.demand_hits::total 12095 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 10829 # number of overall hits +system.l2.overall_hits::.cpu.data 1266 # number of overall hits +system.l2.overall_hits::total 12095 # number of overall hits +system.l2.demand_misses::.cpu.inst 520 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4072 # number of demand (read+write) misses +system.l2.demand_misses::total 4592 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 520 # number of overall misses +system.l2.overall_misses::.cpu.data 4072 # number of overall misses +system.l2.overall_misses::total 4592 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40890000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 355596000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 396486000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40890000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 355596000 # number of overall miss cycles +system.l2.overall_miss_latency::total 396486000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 11349 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5338 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16687 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 11349 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5338 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16687 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.045819 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.762833 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.275184 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.045819 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.762833 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.275184 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 520 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4072 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 4592 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 520 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4072 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 4592 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35690000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 314876000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 350566000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35690000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 314876000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 350566000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.275184 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.275184 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 10989 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 10989 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 10989 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 10989 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 27 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 27 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3311 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3311 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 15 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 15 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18966.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18966.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2520.152590 # Cycle average of tags in use +system.l2.tags.total_refs 32517 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 4605 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 7.061238 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 11.282538 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 502.340959 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2006.529093 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000344 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.015330 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.061234 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.076909 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4605 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 742 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 3779 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.140533 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 264861 # Number of tag accesses +system.l2.tags.data_accesses 264861 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33280 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 260608 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 293888 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 520 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4072 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 4592 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 66488724 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 520657855 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 587146579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 66488724 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 520657855 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 587146579 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 520.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000696500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 9183 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 4592 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 4592 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 322 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 275 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 310 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 422 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 261 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 286 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 312 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 257 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 301 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 208 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 273 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.53 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 74344250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 22960000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 160444250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16189.95 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34939.95 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4061 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.44 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 4592 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2205 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1063 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 694 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 619 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 529 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 553.981096 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 351.714124 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 410.059059 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 90 17.01% 17.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 113 21.36% 38.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 5.67% 44.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 28 5.29% 49.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 4.35% 53.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 17 3.21% 56.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 3.21% 60.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 32 6.05% 66.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 179 33.84% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 529 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 293888 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 293888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 587.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 587.15 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.59 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 500327000 # Total gap between requests +system.mem_ctrls.avgGap 108956.23 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33280 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 260608 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 66488724.087777905166 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 520657854.779676198959 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 520 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4072 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14303500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 146140750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27506.73 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 35889.18 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 88.44 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1899240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1001880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 14915460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 201196320 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 22777440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 281127300 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 561.652509 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 57508250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 16640000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 426387750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1892100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1005675 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 17871420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 153099150 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 63280320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 276485625 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 552.379100 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 163110250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 16640000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 320785750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 139575 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 139575 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 139575 # number of overall hits +system.cpu.icache.overall_hits::total 139575 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 11504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 11504 # number of overall misses +system.cpu.icache.overall_misses::total 11504 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 201794498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201794498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 201794498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201794498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 151079 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 151079 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 151079 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 151079 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.076146 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.076146 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.076146 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.076146 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 17541.246349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked 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+system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 349.312772 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.682252 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.682252 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 313507 # Number of tag accesses +system.cpu.icache.tags.data_accesses 313507 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 330363 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330363 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 330981 # number of overall hits +system.cpu.dcache.overall_hits::total 330981 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 9934 # number of demand (read+write) misses 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+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.470247 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 4041 # number of writebacks +system.cpu.dcache.writebacks::total 4041 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 4584 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 4584 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4584 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 5350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5350 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 70863.345981 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70863.345981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 70871.338004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70871.338004 # average overall mshr miss latency +system.cpu.dcache.replacements 4841 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 53073.277036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53073.277036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1669 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1669 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 2002 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2002 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 89929000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 89929000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.012384 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012384 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 44919.580420 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44919.580420 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 80085.484480 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80085.484480 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2915 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2915 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 288790906 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 288790906 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 86593.974813 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86593.974813 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.788749 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 338206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5353 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.180646 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.788749 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 692269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 692269 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 500536000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/milc/config.ini b/TAGE_SC_L/milc/config.ini new file mode 100644 index 000000000..e1281105f --- /dev/null +++ b/TAGE_SC_L/milc/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 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+eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//data/ref/input/su3imp.in +kvmInSE=false +maxStackSize=67108864 +output=su3imp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/milc/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/milc/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/milc/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/milc/config.json b/TAGE_SC_L/milc/config.json new file mode 100644 index 000000000..e8bf81812 --- /dev/null +++ b/TAGE_SC_L/milc/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/milc/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/milc/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/milc/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": 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+ "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/milc/fs/proc/cpuinfo b/TAGE_SC_L/milc/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/milc/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/milc/fs/proc/stat b/TAGE_SC_L/milc/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/milc/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/milc/fs/sys/devices/system/cpu/online b/TAGE_SC_L/milc/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/milc/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/milc/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/milc/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/milc/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/milc/stats.txt b/TAGE_SC_L/milc/stats.txt new file mode 100644 index 000000000..bf114da29 --- /dev/null +++ b/TAGE_SC_L/milc/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 771934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 89312 # Simulator instruction rate (inst/s) +host_mem_usage 852436 # Number of bytes of host memory used +host_op_rate 92462 # Simulator op (including micro ops) rate (op/s) +host_seconds 11.20 # Real time elapsed on the host +host_tick_rate 68941794 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000005 # Number of instructions simulated +sim_ops 1035288 # Number of ops (including micro ops) simulated +sim_seconds 0.000772 # Number of seconds simulated +sim_ticks 771934000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.792148 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 67887 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68717 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1100 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 42422 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 82 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 306 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 224 # Number of indirect misses. +system.cpu.branchPred.lookups 143579 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 21294 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 6454 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14513 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 13235 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 18 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 234 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 319 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 469 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 42 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 328 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 410 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 138 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 529 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 231 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 760 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 930 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 414 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1635 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 37 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 281 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 93 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 101 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 11 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 36 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 16937 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 387 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 174 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1951 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 71 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 8 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 323 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 409 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 59 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 350 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 231 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 530 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1869 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1647 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 687 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 196 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 10082 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 14 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 80 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 49901 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 68964 # number of cc regfile reads +system.cpu.cc_regfile_writes 68721 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 797 # The number of times a branch was mispredicted +system.cpu.commit.branches 89552 # Number of branches committed +system.cpu.commit.bw_lim_events 63878 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 169 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 505862 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000413 # Number of instructions committed +system.cpu.commit.committedOps 1035696 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1429782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.724373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.819359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1058409 74.03% 74.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 200068 13.99% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61768 4.32% 92.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9481 0.66% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20769 1.45% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6490 0.45% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5334 0.37% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3585 0.25% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63878 4.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1429782 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 30618 # Number of function calls committed. +system.cpu.commit.int_insts 1016144 # Number of committed integer instructions. +system.cpu.commit.loads 160773 # Number of loads committed +system.cpu.commit.membars 142 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 35 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 521896 50.39% 50.39% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 158304 15.28% 65.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 60283 5.82% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 83 0.01% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 138 0.01% 71.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 140 0.01% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 103 0.01% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160773 15.52% 87.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 133941 12.93% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1035696 # Class of committed instruction +system.cpu.commit.refs 294714 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1073 # Number of committed Vector instructions. +system.cpu.committedInsts 1000005 # Number of Instructions Simulated +system.cpu.committedOps 1035288 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.543861 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.543861 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1103566 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 305 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 67843 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1736058 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 125816 # Number of cycles decode is idle +system.cpu.decode.RunCycles 212734 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4634 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1033 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 49279 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 143579 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 215175 # Number of cache lines fetched +system.cpu.fetch.Cycles 1257140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1758524 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9874 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.092999 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 233891 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 117870 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.139037 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.215674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.571580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1160787 77.59% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24293 1.62% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 54513 3.64% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17903 1.20% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26423 1.77% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35114 2.35% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 27991 1.87% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 9593 0.64% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 139412 9.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 47840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2747 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 132264 # Number of branches executed +system.cpu.iew.exec_nop 464 # number of nop insts executed +system.cpu.iew.exec_rate 0.984822 # Inst execution rate +system.cpu.iew.exec_refs 473801 # number of memory reference insts executed +system.cpu.iew.exec_stores 198453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 332881 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 276092 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 214 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 228886 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1701929 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 275348 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1520436 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17214 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 49608 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4634 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75400 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 3665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 149 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 115309 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 94929 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2518 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1610580 # num instructions consuming a value +system.cpu.iew.wb_count 1454780 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.646638 # average fanout of values written-back +system.cpu.iew.wb_producers 1041462 # num instructions producing a value +system.cpu.iew.wb_rate 0.942295 # insts written-back per cycle +system.cpu.iew.wb_sent 1519421 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2248203 # number of integer regfile reads +system.cpu.int_regfile_writes 1261314 # number of integer regfile writes +system.cpu.ipc 0.647727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.647727 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 779760 51.22% 51.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 199683 13.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 67953 4.46% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 85 0.01% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 140 0.01% 68.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 140 0.01% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 107 0.01% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 275910 18.12% 86.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 198634 13.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1522447 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1173303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.770669 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7553 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 612118 52.17% 52.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 533999 45.51% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11437 0.97% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8193 0.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 2694513 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5738105 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1453690 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2366292 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1701251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1522447 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 666110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 26240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 514802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1496029 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.017659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.601098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 888614 59.40% 59.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200614 13.41% 72.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 178533 11.93% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95716 6.40% 91.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45502 3.04% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45883 3.07% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22769 1.52% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17602 1.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 796 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1496029 # Number of insts issued each cycle +system.cpu.iq.rate 0.986124 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1202 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2360 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1090 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1315 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 4086 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 166 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 276092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 228886 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 923178 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.numCycles 1543869 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 463634 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 914731 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 93277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 136560 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 125 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2724794 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1715294 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1498240 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239996 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 537737 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4634 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 638173 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 583452 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2637927 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 13032 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 390 # count of serializing insts renamed +system.cpu.rename.skidInsts 224398 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 223 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1492 # Number of vector rename lookups +system.cpu.rob.rob_reads 2857867 # The number of ROB reads +system.cpu.rob.rob_writes 3149444 # The number of ROB writes +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1321 # number of vector regfile reads +system.cpu.vec_regfile_writes 571 # number of vector regfile writes +system.cpu.workload.numSyscalls 26 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 13062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 29025 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 25 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 31663 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 25 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 753 # Transaction distribution +system.membus.trans_dist::WritebackDirty 13041 # Transaction distribution +system.membus.trans_dist::CleanEvict 21 # Transaction distribution +system.membus.trans_dist::ReadExReq 15203 # Transaction distribution +system.membus.trans_dist::ReadExResp 15202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 753 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 15963 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15963 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15963 # Request fanout histogram +system.membus.reqLayer0.occupancy 85449500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 11.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 83558250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 959 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 28109 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 412 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 59 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 15204 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 15202 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 816 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 143 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 7 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 7 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2044 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 45787 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 47831 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 78592 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 1946432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2025024 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 13087 # Total snoops (count) +system.tol2bus.snoopTraffic 834624 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 29257 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000889 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.029798 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 29231 99.91% 99.91% # Request fanout histogram +system.tol2bus.snoop_fanout::1 26 0.09% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 29257 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31311500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 23021000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 3.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1224000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 203 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4 # number of demand (read+write) hits +system.l2.demand_hits::total 207 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 203 # number of overall hits +system.l2.overall_hits::.cpu.data 4 # number of overall hits +system.l2.overall_hits::total 207 # number of overall hits +system.l2.demand_misses::.cpu.inst 613 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 15343 # number of demand (read+write) misses +system.l2.demand_misses::total 15956 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 613 # number of overall misses +system.l2.overall_misses::.cpu.data 15343 # number of overall misses +system.l2.overall_misses::total 15956 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 47921500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1333591000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1381512500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 47921500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1333591000 # number of overall miss cycles +system.l2.overall_miss_latency::total 1381512500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 816 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 15347 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16163 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 816 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 15347 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16163 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.751225 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999739 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.987193 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.751225 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999739 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.987193 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 13041 # number of writebacks +system.l2.writebacks::total 13041 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 613 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 15343 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 15956 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 613 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 15343 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 15956 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 41791500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1180181000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1221972500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 41791500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1180181000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1221972500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.987193 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.987193 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.replacements 13087 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 411 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 411 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 411 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 411 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 15203 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 15203 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2615.918231 # Cycle average of tags in use +system.l2.tags.total_refs 31653 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 15957 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.983644 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.225835 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 565.825416 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2048.866980 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000037 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.017268 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.062526 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.079831 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2870 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1846 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 822 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.087585 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 269253 # Number of tag accesses +system.l2.tags.data_accesses 269253 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 39232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 981952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1021184 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 834624 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 834624 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 613 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 15343 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 15956 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 13041 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 13041 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 50822998 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1272067301 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1322890299 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1081211606 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 50822998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1272067301 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2404101905 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 13041.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 613.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 15343.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000013500250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 813 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 813 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 43428 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 12201 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 15956 # Number of read requests accepted +system.mem_ctrls.writeReqs 13041 # Number of write requests accepted +system.mem_ctrls.readBursts 15956 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 13041 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 992 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1054 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 982 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 972 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1073 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 985 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1026 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 956 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 979 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1036 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1008 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 976 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 814 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 811 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 818 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 815 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 810 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.02 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 249603250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 79780000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 548778250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 15643.22 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34393.22 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 13782 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 11296 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.62 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 15956 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 13041 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7854 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7660 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 818 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 3886 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 476.557900 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 444.203406 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 118.434932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 147 3.78% 3.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 4.04% 7.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 28 0.72% 8.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 185 4.76% 13.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3341 85.98% 99.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 0.21% 99.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 0.08% 99.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 0.10% 99.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 0.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 3886 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 813 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.611316 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.109728 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 102.759447 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 812 99.88% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2944-3071 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 813 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 813 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.007380 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.006268 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.210429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 812 99.88% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.12% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 813 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 1021184 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 832896 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1021184 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 834624 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1322.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1078.97 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1322.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1081.21 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 18.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.34 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 8.43 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 771884000 # Total gap between requests +system.mem_ctrls.avgGap 26619.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 39232 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 981952 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 832896 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 50822997.821057237685 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1272067301.090507745743 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1078973072.827469587326 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 613 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 15343 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 13041 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 16555500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 532222750 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 15715577750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27007.34 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 34688.31 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 1205089.93 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 86.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 14080080 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 7460970 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 57398460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 33971760 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 334312410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14896800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 522969840 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 677.479992 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 36020250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 710173750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 13708800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 7286400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 33961320 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 335170830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 14173920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 521678010 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 675.806494 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 34169250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 712024750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 214182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 214182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 214182 # number of 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WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1344348498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.113621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.113621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 88420.711523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88420.711523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 264.979661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 295294 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 15352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.234888 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 264.979661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.529297 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 833190 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 833190 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 771934000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/milc/su3imp.out b/TAGE_SC_L/milc/su3imp.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/namd/config.ini b/TAGE_SC_L/namd/config.ini new file mode 100644 index 000000000..e5f3c9835 --- /dev/null +++ b/TAGE_SC_L/namd/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 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opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 system.cpu.fuPool.FUList5.opList23 system.cpu.fuPool.FUList5.opList24 system.cpu.fuPool.FUList5.opList25 + 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+opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross --input /home/min/a/ece565/benchspec-2020/CPU2006/444.namd//data/all/input/namd.input --iterations 1 --output namd.out +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=namd.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/namd/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/namd/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/namd/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/namd/config.json b/TAGE_SC_L/namd/config.json new file mode 100644 index 000000000..8425d62a1 --- /dev/null +++ b/TAGE_SC_L/namd/config.json @@ -0,0 +1,1816 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/namd/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/namd/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/namd/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + 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+ "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/namd/fs/proc/cpuinfo b/TAGE_SC_L/namd/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/namd/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/namd/fs/proc/stat b/TAGE_SC_L/namd/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/namd/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/namd/fs/sys/devices/system/cpu/online b/TAGE_SC_L/namd/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/namd/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/namd/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/namd/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/namd/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/namd/namd.stdout b/TAGE_SC_L/namd/namd.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/namd/stats.txt b/TAGE_SC_L/namd/stats.txt new file mode 100644 index 000000000..11e130cfe --- /dev/null +++ b/TAGE_SC_L/namd/stats.txt @@ -0,0 +1,1346 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 342062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 135418 # Simulator instruction rate (inst/s) +host_mem_usage 853404 # Number of bytes of host memory used +host_op_rate 150534 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.38 # Real time elapsed on the host +host_tick_rate 46320165 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1111649 # Number of ops (including micro ops) simulated +sim_seconds 0.000342 # Number of seconds simulated +sim_ticks 342062500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.672835 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118809 # Number of BTB hits +system.cpu.branchPred.BTBLookups 120407 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4928 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2833 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3243 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 410 # Number of indirect misses. +system.cpu.branchPred.lookups 252244 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 101918 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 65407 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 97895 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 69430 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 234 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3091 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1934 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 549 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 986 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1869 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1433 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 568 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 590 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1553 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 981 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1682 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1384 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 768 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 526 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 379 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 818 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 872 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1097 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 812 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1409 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 264 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 124175 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 959 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3431 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1422 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4096 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3051 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 5683 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2247 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1586 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1202 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 973 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1537 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 634 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1807 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 738 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 513 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 962 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1080 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1488 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 37083 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 680 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1093 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 12668 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 107 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 406413 # number of cc regfile reads +system.cpu.cc_regfile_writes 399910 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4465 # The number of times a branch was mispredicted +system.cpu.commit.branches 216048 # Number of branches committed +system.cpu.commit.bw_lim_events 53496 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 486 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 118898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001856 # Number of instructions committed +system.cpu.commit.committedOps 1113505 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 605513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.838945 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.532655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 255756 42.24% 42.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 143185 23.65% 65.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57737 9.54% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36800 6.08% 81.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21553 3.56% 85.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8832 1.46% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10972 1.81% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17182 2.84% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53496 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 605513 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 11108 # Number of function calls committed. +system.cpu.commit.int_insts 980744 # Number of committed integer instructions. +system.cpu.commit.loads 176934 # Number of loads committed +system.cpu.commit.membars 475 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 185 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 796966 71.57% 71.59% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3693 0.33% 71.92% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 912 0.08% 72.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 438 0.04% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 15 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 9 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1629 0.15% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 433 0.04% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 647 0.06% 72.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 598 0.05% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 526 0.05% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 176934 15.89% 88.28% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 130493 11.72% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1113505 # Class of committed instruction +system.cpu.commit.refs 307427 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 10353 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1111649 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.684126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.684126 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 123704 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 477 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117668 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1269158 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 241422 # Number of cycles decode is idle +system.cpu.decode.RunCycles 244786 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4577 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1653 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 8066 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 252244 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 191602 # Number of cache lines fetched +system.cpu.fetch.Cycles 351490 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1163577 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10080 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.368710 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 265962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 134310 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.700823 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 622555 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.077656 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.946208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 354909 57.01% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36395 5.85% 62.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35829 5.76% 68.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29315 4.71% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25782 4.14% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22071 3.55% 81.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22996 3.69% 84.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16066 2.58% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 79192 12.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 622555 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 61571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 226272 # Number of branches executed +system.cpu.iew.exec_nop 1973 # number of nop insts executed +system.cpu.iew.exec_rate 1.731738 # Inst execution rate +system.cpu.iew.exec_refs 336529 # number of memory reference insts executed +system.cpu.iew.exec_stores 137581 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 18776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199413 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 143076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1232740 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 198948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1184727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 75 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4577 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 13404 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 51 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11145 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 22474 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 12581 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 51 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3178 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1611 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1051584 # num instructions consuming a value +system.cpu.iew.wb_count 1169811 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.565495 # average fanout of values written-back +system.cpu.iew.wb_producers 594666 # num instructions producing a value +system.cpu.iew.wb_rate 1.709935 # insts written-back per cycle +system.cpu.iew.wb_sent 1171681 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1338795 # number of integer regfile reads +system.cpu.int_regfile_writes 842064 # number of integer regfile writes +system.cpu.ipc 1.461719 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.461719 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 205 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 843381 70.75% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3830 0.32% 71.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 913 0.08% 71.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 443 0.04% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 22 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 9 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1911 0.16% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 1 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 490 0.04% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 729 0.06% 71.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 662 0.06% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 561 0.05% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 200822 16.85% 88.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138126 11.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1192128 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19491 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016350 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7584 38.91% 38.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 286 1.47% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 16 0.08% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 1 0.01% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 37 0.19% 40.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 40.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 32 0.16% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3651 18.73% 59.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7880 40.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1198409 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3001822 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1158219 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1335839 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1230257 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1192128 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 119104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 604 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 91660 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 622555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.914896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.081400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 224872 36.12% 36.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 111647 17.93% 54.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 80394 12.91% 66.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 65833 10.57% 77.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57137 9.18% 86.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35638 5.72% 92.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25524 4.10% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9768 1.57% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11742 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 622555 # Number of insts issued each cycle +system.cpu.iq.rate 1.742556 # Inst issue rate +system.cpu.iq.vec_alu_accesses 13005 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 25084 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 11592 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 14079 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 11813 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10481 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 143076 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 814624 # number of misc regfile reads +system.cpu.misc_regfile_writes 2390 # number of misc regfile writes +system.cpu.numCycles 684126 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 20510 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1188200 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4829 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 245465 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1607 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 197 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1901749 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1255514 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1346306 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 248576 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 43450 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4577 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 52052 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 158085 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1414708 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 51375 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2390 # count of serializing insts renamed +system.cpu.rename.skidInsts 24882 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 512 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 11865 # Number of vector rename lookups +system.cpu.rob.rob_reads 1783497 # The number of ROB reads +system.cpu.rob.rob_writes 2481923 # The number of ROB writes +system.cpu.timesIdled 2175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 11159 # number of vector regfile reads +system.cpu.vec_regfile_writes 5976 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 3 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 3085 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 7097 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1021 # Transaction distribution +system.membus.trans_dist::ReadExReq 385 # Transaction distribution +system.membus.trans_dist::ReadExResp 385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1021 # Transaction distribution +system.membus.trans_dist::InvalidateReq 12 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1418 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1418 # Request fanout histogram +system.membus.reqLayer0.occupancy 1743000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 7466000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3603 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 123 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 98 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 397 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 397 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3346 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 257 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 12 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 12 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 9556 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1553 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 11109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 397440 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 49728 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 447168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 4012 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000748 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.027338 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 4009 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 4012 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 6535500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 987499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 5019000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2570 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 2594 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2570 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 2594 # number of overall hits +system.l2.demand_misses::.cpu.inst 776 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 630 # number of demand (read+write) misses +system.l2.demand_misses::total 1406 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 776 # number of overall misses +system.l2.overall_misses::.cpu.data 630 # number of overall misses +system.l2.overall_misses::total 1406 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61228500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 53298500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 114527000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61228500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 53298500 # number of overall miss cycles +system.l2.overall_miss_latency::total 114527000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3346 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 654 # number of demand (read+write) accesses +system.l2.demand_accesses::total 4000 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3346 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 654 # number of overall (read+write) accesses +system.l2.overall_accesses::total 4000 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.231919 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.963303 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.351500 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.231919 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.963303 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.351500 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.demand_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.overall_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 776 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 630 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1406 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 776 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 630 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1406 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53468500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 46998500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 100467000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53468500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 46998500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 100467000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.351500 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.351500 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 123 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 123 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2862 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2862 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2862 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2862 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 12 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 12 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 385 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 385 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 12 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 12 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19166.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19166.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1147.163949 # Cycle average of tags in use +system.l2.tags.total_refs 7082 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1414 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 5.008487 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 3.100039 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 718.567739 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 425.496172 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.021929 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.012985 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.035009 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1307 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.043152 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 58166 # Number of tag accesses +system.l2.tags.data_accesses 58166 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 49664 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 40320 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 89984 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 776 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 630 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1406 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 145189841 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 117873196 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 263063037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 145189841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 117873196 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 263063037 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 776.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 630.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000595500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2857 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1406 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1406 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 188 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.12 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 16247000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 7030000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 42609500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 11555.48 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 30305.48 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1036 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1406 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 925 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 309 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 119 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 366 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 244.459016 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 165.753947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 253.358390 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 108 29.51% 29.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 154 42.08% 71.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 34 9.29% 80.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21 5.74% 86.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 2.19% 88.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.28% 92.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 1.64% 93.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.09% 94.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 19 5.19% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 366 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 89984 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 89984 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 263.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 263.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.06 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.06 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 341590500 # Total gap between requests +system.mem_ctrls.avgGap 242951.99 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 49664 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 40320 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 145189841.037822037935 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 117873195.687922537327 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 776 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 630 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21553250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 21056250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27774.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33422.62 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 73.68 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1342320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 705870 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4219740 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 142332420 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 11493120 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 186522990 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 545.289209 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 28704750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 302177750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1299480 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5819100 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 102551550 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 44992800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 181775550 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 531.410342 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 116125500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 214757000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 188002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 188002 # number of overall hits +system.cpu.icache.overall_hits::total 188002 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3599 # number of demand (read+write) misses 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+system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 455.896294 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.890422 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.890422 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 482 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 479 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386548 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386548 # Number of data accesses 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number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 2484 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2484 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 2487 # number of overall misses +system.cpu.dcache.overall_misses::total 2487 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 191127451 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 191127451 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 191127451 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 191127451 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 303382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 303382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 304639 # number of overall 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cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.136986 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 123 # number of writebacks +system.cpu.dcache.writebacks::total 123 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1821 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1821 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 663 # number of demand (read+write) MSHR misses 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miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133892953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 344.568452 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 303779 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 666 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 456.124625 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 344.568452 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.869141 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 611866 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 611866 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 342062500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/omnetpp/config.ini b/TAGE_SC_L/omnetpp/config.ini new file mode 100644 index 000000000..716fda80b --- /dev/null +++ b/TAGE_SC_L/omnetpp/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + 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+clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//data/ref/input/omnetpp.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=omnetpp.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/omnetpp/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/omnetpp/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/omnetpp/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/omnetpp/config.json b/TAGE_SC_L/omnetpp/config.json new file mode 100644 index 000000000..4d3861746 --- /dev/null +++ b/TAGE_SC_L/omnetpp/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/omnetpp/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/omnetpp/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/omnetpp/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/omnetpp/fs/proc/cpuinfo b/TAGE_SC_L/omnetpp/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/omnetpp/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/omnetpp/fs/proc/stat b/TAGE_SC_L/omnetpp/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/omnetpp/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/online b/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/omnetpp/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/omnetpp/omnetpp.log b/TAGE_SC_L/omnetpp/omnetpp.log new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/omnetpp/stats.txt b/TAGE_SC_L/omnetpp/stats.txt new file mode 100644 index 000000000..a5ff6563d --- /dev/null +++ b/TAGE_SC_L/omnetpp/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 600830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 97276 # Simulator instruction rate (inst/s) +host_mem_usage 872264 # Number of bytes of host memory used +host_op_rate 104583 # Simulator op (including micro ops) rate (op/s) +host_seconds 10.28 # Real time elapsed on the host +host_tick_rate 58445384 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1075135 # Number of ops (including micro ops) simulated +sim_seconds 0.000601 # Number of seconds simulated +sim_ticks 600830500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.016583 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 148545 # Number of BTB hits +system.cpu.branchPred.BTBLookups 153113 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6561 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 256294 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1996 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3048 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 1052 # Number of indirect misses. +system.cpu.branchPred.lookups 344799 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 124051 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60754 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113162 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71643 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 344 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 45 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5324 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2167 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 57 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 329 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3284 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1458 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 3422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 757 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1066 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1083 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 405 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 765 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 867 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 766 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1241 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 905 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 993 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 494 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1436 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 209 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 568 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 152787 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 781 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1385 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 307 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 552 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 955 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1870 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2792 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1115 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 782 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 948 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 502 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 815 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 890 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1314 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1593 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1083 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 24677 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 269 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1362 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 31611 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 517 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 559188 # number of cc regfile reads +system.cpu.cc_regfile_writes 492774 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4887 # The number of times a branch was mispredicted +system.cpu.commit.branches 250422 # Number of branches committed +system.cpu.commit.bw_lim_events 61679 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 540 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 250346 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1003357 # Number of instructions committed +system.cpu.commit.committedOps 1078492 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1060509 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.016957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.129603 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 743853 70.14% 70.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104575 9.86% 80.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 71710 6.76% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25390 2.39% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28256 2.66% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8269 0.78% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10913 1.03% 93.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5864 0.55% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61679 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1060509 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 24973 # Number of function calls committed. +system.cpu.commit.int_insts 934829 # Number of committed integer instructions. +system.cpu.commit.loads 104843 # Number of loads committed +system.cpu.commit.membars 532 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 12 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 870934 80.75% 80.76% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 40054 3.71% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 38 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 47 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 49 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 47 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 104843 9.72% 94.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 62445 5.79% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1078492 # Class of committed instruction +system.cpu.commit.refs 167288 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 699 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1075135 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.201662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.201662 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 617643 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1684 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 144015 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1375078 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 199308 # Number of cycles decode is idle +system.cpu.decode.RunCycles 230164 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4951 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 7329 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 42522 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 344799 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 251042 # Number of cache lines fetched +system.cpu.fetch.Cycles 796828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3081 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1341720 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 13250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.286935 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 290887 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182152 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.116554 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.312222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 757448 69.20% 69.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52806 4.82% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72422 6.62% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 31200 2.85% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 29155 2.66% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36050 3.29% 89.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 20265 1.85% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35303 3.23% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59939 5.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 107074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 5288 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 292397 # Number of branches executed +system.cpu.iew.exec_nop 3630 # number of nop insts executed +system.cpu.iew.exec_rate 1.036673 # Inst execution rate +system.cpu.iew.exec_refs 190511 # number of memory reference insts executed +system.cpu.iew.exec_stores 68247 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 236197 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131642 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 697 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 72865 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1329304 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8709 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1245730 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1309 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1325 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4951 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5211 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 7688 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2529 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 10420 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2944 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1319747 # num instructions consuming a value +system.cpu.iew.wb_count 1234451 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.515417 # average fanout of values written-back +system.cpu.iew.wb_producers 680220 # num instructions producing a value +system.cpu.iew.wb_rate 1.027286 # insts written-back per cycle +system.cpu.iew.wb_sent 1237611 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1401236 # number of integer regfile reads +system.cpu.int_regfile_writes 922560 # number of integer regfile writes +system.cpu.ipc 0.832181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.832181 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1018643 81.20% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 40062 3.19% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 26 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 54 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 70 0.01% 84.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 69 0.01% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126059 10.05% 94.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 69382 5.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1254440 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 10878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008672 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8498 78.12% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.02% 78.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 6 0.06% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 685 6.30% 84.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1687 15.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1264404 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3613205 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1233634 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1575017 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1325083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1254440 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 591 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 250524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 671 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 145632 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1094588 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.146039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.729328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 605474 55.32% 55.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 173599 15.86% 71.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 126763 11.58% 82.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70125 6.41% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49712 4.54% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23222 2.12% 95.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 26221 2.40% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11120 1.02% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8352 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1094588 # Number of insts issued each cycle +system.cpu.iq.rate 1.043921 # Inst issue rate +system.cpu.iq.vec_alu_accesses 897 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1811 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 817 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1221 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 8896 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6565 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 131642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 72865 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 776684 # number of misc regfile reads +system.cpu.misc_regfile_writes 2121 # number of misc regfile writes +system.cpu.numCycles 1201662 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 386132 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1228037 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 116818 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 213486 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2867 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5124 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2147241 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1354877 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1542516 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 250910 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7919 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4951 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 144869 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 314451 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1523758 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 94240 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2166 # count of serializing insts renamed +system.cpu.rename.skidInsts 218820 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 593 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1144 # Number of vector rename lookups +system.cpu.rob.rob_reads 2327278 # The number of ROB reads +system.cpu.rob.rob_writes 2691796 # The number of ROB writes +system.cpu.timesIdled 1246 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 944 # number of vector regfile reads +system.cpu.vec_regfile_writes 295 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6851 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 6920 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 14864 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 5670 # Transaction distribution +system.membus.trans_dist::ReadExReq 1032 # Transaction distribution +system.membus.trans_dist::ReadExResp 1031 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5670 # Transaction distribution +system.membus.trans_dist::InvalidateReq 149 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 6851 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6851 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6851 # Request fanout histogram +system.membus.reqLayer0.occupancy 8063000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 35377250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 6743 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1272 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1208 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 4440 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1049 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1048 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1718 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 5026 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 151 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 151 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4644 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 18162 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 22806 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 187264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 470080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 657344 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 7944 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.011220 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 7943 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 7944 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9912000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 9185499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2577998 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 205 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 886 # number of demand (read+write) hits +system.l2.demand_hits::total 1091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 205 # number of overall hits +system.l2.overall_hits::.cpu.data 886 # number of overall hits +system.l2.overall_hits::total 1091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5189 # number of demand (read+write) misses +system.l2.demand_misses::total 6702 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1513 # number of overall misses +system.l2.overall_misses::.cpu.data 5189 # number of overall misses +system.l2.overall_misses::total 6702 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 118284000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 389913000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 508197000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 118284000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 389913000 # number of overall miss cycles +system.l2.overall_miss_latency::total 508197000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1718 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 6075 # number of demand (read+write) accesses +system.l2.demand_accesses::total 7793 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1718 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 6075 # number of overall (read+write) accesses +system.l2.overall_accesses::total 7793 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.880675 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.854156 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.860003 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.880675 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.854156 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.860003 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5189 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 6702 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5189 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 6702 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 103154000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 338033000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 441187000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 103154000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 338033000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 441187000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.860003 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.860003 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1208 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1208 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1208 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1208 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 17 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 17 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 1032 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 1032 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 149 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 149 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19114.093960 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19114.093960 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3524.172320 # Cycle average of tags in use +system.l2.tags.total_refs 14713 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 6852 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.147256 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 103.457419 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1250.327723 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2170.387178 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.038157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.066235 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.107549 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 6850 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1057 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 5723 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.209045 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 125756 # Number of tag accesses +system.l2.tags.data_accesses 125756 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 96832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 332032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 428864 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5188 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 6701 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 161163589 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 552621746 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 713785335 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 161163589 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 552621746 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 713785335 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5189.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000592250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 13490 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 6702 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 6702 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 366 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 531 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 375 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 552 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 486 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 454 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 472 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 373 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 387 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.18 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 40720500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 33510000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 166383000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6075.87 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24825.87 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 5865 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.51 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 6702 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5584 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 809 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 836 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 512.382775 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 327.950498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 396.797343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 152 18.18% 18.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 165 19.74% 37.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 89 10.65% 48.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 53 6.34% 54.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 52 6.22% 61.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 22 2.63% 63.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 21 2.51% 66.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 22 2.63% 68.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 260 31.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 836 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 428928 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 428928 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 713.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 713.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 600814000 # Total gap between requests +system.mem_ctrls.avgGap 89646.97 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 96832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 332096 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 161163589.398341149092 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 552728265.292790651321 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5189 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 40921500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 125461500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27046.60 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24178.36 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2977380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1578720 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24468780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 167296710 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 89837760 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 333486630 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 555.042778 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 231136500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 20020000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 349674000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 2998800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 23383500 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 169256370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 88187520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 332747370 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 553.812381 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 227066750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 20020000 # Time in different power states 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latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66346.123955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 66354.450498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66354.450498 # average overall mshr miss latency +system.cpu.dcache.replacements 5712 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 91292 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 91292 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 19596 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 19596 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 1208935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1208935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 110888 # number of ReadReq accesses(hits+misses) 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MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78893.383962 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78893.383962 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 472.929101 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156727 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6224 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.181073 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 472.929101 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 354060 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 354060 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 600830500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/povray/SPEC-benchmark-ref.stdout b/TAGE_SC_L/povray/SPEC-benchmark-ref.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/povray/config.ini b/TAGE_SC_L/povray/config.ini new file mode 100644 index 000000000..798f34684 --- /dev/null +++ b/TAGE_SC_L/povray/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc 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+type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/453.povray//data/ref/input/SPEC-benchmark-ref.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=SPEC-benchmark-ref.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/povray/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/povray/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/povray/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/povray/config.json b/TAGE_SC_L/povray/config.json new file mode 100644 index 000000000..0c33821fe --- /dev/null +++ b/TAGE_SC_L/povray/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": 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"static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/povray/fs/proc/cpuinfo b/TAGE_SC_L/povray/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/povray/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/povray/fs/proc/stat b/TAGE_SC_L/povray/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/povray/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/povray/fs/sys/devices/system/cpu/online b/TAGE_SC_L/povray/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/povray/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/povray/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/povray/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/povray/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/povray/stats.txt b/TAGE_SC_L/povray/stats.txt new file mode 100644 index 000000000..9f68ed31d --- /dev/null +++ b/TAGE_SC_L/povray/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 440535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 116481 # Simulator instruction rate (inst/s) +host_mem_usage 859796 # Number of bytes of host memory used +host_op_rate 137159 # Simulator op (including micro ops) rate (op/s) +host_seconds 8.59 # Real time elapsed on the host +host_tick_rate 51312504 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1177555 # Number of ops (including micro ops) simulated +sim_seconds 0.000441 # Number of seconds simulated +sim_ticks 440535000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.198572 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115989 # Number of BTB hits +system.cpu.branchPred.BTBLookups 119332 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7435 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 213239 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1230 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2181 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 951 # Number of indirect misses. +system.cpu.branchPred.lookups 290314 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 125053 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 46817 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113188 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 58682 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 918 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 207 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12467 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2851 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1409 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3608 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 980 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2217 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1418 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2515 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1455 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1565 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3315 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2539 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 724 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1115 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1141 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 664 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 235 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2236 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 375 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 687 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 118623 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2119 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2831 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 3677 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3364 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3420 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3217 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2153 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1816 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 2903 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 2587 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1068 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1492 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 2976 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1833 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 514 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 729 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 43932 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 362 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1603 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 29908 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 306 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 385761 # number of cc regfile reads +system.cpu.cc_regfile_writes 379620 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6003 # The number of times a branch was mispredicted +system.cpu.commit.branches 236171 # Number of branches committed +system.cpu.commit.bw_lim_events 73367 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 75 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 136896 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000964 # Number of instructions committed +system.cpu.commit.committedOps 1178517 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 736122 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.600981 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.554495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 393460 53.45% 53.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 135494 18.41% 71.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47723 6.48% 78.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 40908 5.56% 83.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13088 1.78% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12972 1.76% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 13065 1.77% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6045 0.82% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73367 9.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 736122 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 25599 # Number of function calls committed. +system.cpu.commit.int_insts 1058462 # Number of committed integer instructions. +system.cpu.commit.loads 219653 # Number of loads committed +system.cpu.commit.membars 58 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 85 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 803955 68.22% 68.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 43 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 8 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 3 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 24 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 211 0.02% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 346 0.03% 68.28% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 340 0.03% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 4 0.00% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 252 0.02% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 219653 18.64% 86.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 153553 13.03% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1178517 # Class of committed instruction +system.cpu.commit.refs 373206 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2565 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1177555 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.881069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881069 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 352277 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1467 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 112500 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1366665 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 166919 # Number of cycles decode is idle +system.cpu.decode.RunCycles 199841 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6169 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 5195 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 31333 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 290314 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 188047 # Number of cache lines fetched +system.cpu.fetch.Cycles 500939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3491 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1223026 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 15202 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.329501 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 247929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 147127 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.388113 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 756539 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.886749 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.851187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458670 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35950 4.75% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45265 5.98% 71.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36757 4.86% 76.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21735 2.87% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35827 4.74% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 17076 2.26% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19955 2.64% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85304 11.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 756539 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 124532 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 6907 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 248720 # Number of branches executed +system.cpu.iew.exec_nop 1123 # number of nop insts executed +system.cpu.iew.exec_rate 1.425137 # Inst execution rate +system.cpu.iew.exec_refs 396422 # number of memory reference insts executed +system.cpu.iew.exec_stores 160107 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 22254 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 246607 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1641 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 168064 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1316053 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 236315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1255647 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6169 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2685 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 324 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5311 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 52 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2782 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26945 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 14506 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 149 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 4240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2667 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1198971 # num instructions consuming a value +system.cpu.iew.wb_count 1244234 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.560166 # average fanout of values written-back +system.cpu.iew.wb_producers 671623 # num instructions producing a value +system.cpu.iew.wb_rate 1.412184 # insts written-back per cycle +system.cpu.iew.wb_sent 1248252 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1406014 # number of integer regfile reads +system.cpu.int_regfile_writes 902367 # number of integer regfile writes +system.cpu.ipc 1.134985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134985 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 98 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 864482 68.23% 68.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 28 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 42 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 235 0.02% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 384 0.03% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 387 0.03% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 4 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 266 0.02% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 239173 18.88% 87.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 161918 12.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1267085 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015362 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4588 23.57% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 5 0.03% 23.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 18 0.09% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525 33.52% 57.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8328 42.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1283510 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3305038 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1241483 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1448868 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1314816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1267085 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 114 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 137324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 746 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 104243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 756539 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.674844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.170087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360054 47.59% 47.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 105577 13.96% 61.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 70744 9.35% 70.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70123 9.27% 80.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57524 7.60% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29199 3.86% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28653 3.79% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15678 2.07% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18987 2.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 756539 # Number of insts issued each cycle +system.cpu.iq.rate 1.438119 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2942 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 5874 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2751 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 3525 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 3911 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5794 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 246607 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 168064 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 951083 # number of misc regfile reads +system.cpu.misc_regfile_writes 272 # number of misc regfile writes +system.cpu.numCycles 881071 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 35111 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1212533 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 12363 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 181263 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 453 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2001540 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1344395 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1383743 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 215925 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 24594 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6169 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 58674 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171123 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1509943 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 259397 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 14972 # count of serializing insts renamed +system.cpu.rename.skidInsts 139589 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 132 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 3983 # Number of vector rename lookups +system.cpu.rob.rob_reads 1977635 # The number of ROB reads +system.cpu.rob.rob_writes 2651412 # The number of ROB writes +system.cpu.timesIdled 1992 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 3332 # number of vector regfile reads +system.cpu.vec_regfile_writes 1671 # number of vector regfile writes +system.cpu.workload.numSyscalls 16 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2830 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10828 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2059 # Transaction distribution +system.membus.trans_dist::ReadExReq 761 # Transaction distribution +system.membus.trans_dist::ReadExResp 761 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2059 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2830 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2830 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2830 # Request fanout histogram +system.membus.reqLayer0.occupancy 3507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 14927500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4828 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1995 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2596 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 312 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3108 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1720 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 14 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 14 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 8812 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 7941 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16753 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 365056 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 307072 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 672128 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5925 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000169 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012991 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5924 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5925 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 10005000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 4211999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 4662000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1580 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1511 # number of demand (read+write) hits +system.l2.demand_hits::total 3091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1580 # number of overall hits +system.l2.overall_hits::.cpu.data 1511 # number of overall hits +system.l2.overall_hits::total 3091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1528 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1292 # number of demand (read+write) misses +system.l2.demand_misses::total 2820 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1528 # number of overall misses +system.l2.overall_misses::.cpu.data 1292 # number of overall misses +system.l2.overall_misses::total 2820 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 120129500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 101875000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 222004500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 120129500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 101875000 # number of overall miss cycles +system.l2.overall_miss_latency::total 222004500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3108 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2803 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5911 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3108 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2803 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5911 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.491634 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.460935 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.477077 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.491634 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.460935 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.477077 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78725 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78725 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1528 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1292 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2820 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1528 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1292 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2820 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 104849500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 88955000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 193804500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 104849500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 88955000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 193804500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.477077 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.477077 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2596 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2596 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2596 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2596 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 322 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 322 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 761 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 761 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 4 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 4 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18800 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18800 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1655.197760 # Cycle average of tags in use +system.l2.tags.total_refs 10817 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2833 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.818214 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.404433 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1024.255259 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 624.538068 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000195 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.031258 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.019059 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.050513 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2829 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 670 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2156 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.086334 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 89449 # Number of tag accesses +system.l2.tags.data_accesses 89449 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 97792 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 82688 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 180480 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1528 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1292 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2820 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 221984632 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 187699048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 409683680 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 221984632 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 187699048 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 409683680 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1528.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1292.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000578500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5675 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2820 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2820 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 134 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 298 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 133 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 216 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 289 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 221 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 141 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 130 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 137 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 179 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 183 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 24911000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 14100000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 77786000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8833.69 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27583.69 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2231 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.11 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2820 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1806 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 666 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 261 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 73 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 588 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 306.829932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 191.362404 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 311.414367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 186 31.63% 31.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 26.70% 58.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 86 14.63% 72.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 6.46% 79.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 3.91% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 1.36% 84.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 2.89% 87.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 18 3.06% 90.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 55 9.35% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 588 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 180480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 180480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 409.68 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 409.68 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 437498000 # Total gap between requests +system.mem_ctrls.avgGap 155141.13 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 97792 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 82688 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 221984632.322062969208 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 187699047.748760044575 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1528 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1292 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 41993750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 35792250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27482.82 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 27702.98 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 79.11 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2241960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1187835 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10695720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 144782850 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 47243040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 240571245 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 546.088835 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 121360750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 304614250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1963500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1043625 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 9439080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 141036240 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 50398080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 238300365 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 540.934012 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 129731500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 296243500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 184461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 184461 # number of overall hits +system.cpu.icache.overall_hits::total 184461 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3585 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3585 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3585 # number of overall misses +system.cpu.icache.overall_misses::total 3585 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 168059999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 168059999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 188046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 188046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 188046 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.019064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.019064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.019064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.019064 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 46878.660809 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46878.660809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 46878.660809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46878.660809 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1751 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 79.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2596 # number of writebacks +system.cpu.icache.writebacks::total 2596 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 477 # number of demand (read+write) MSHR hits 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# number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 184461 # number of ReadReq hits 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per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379200 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379200 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 122603988 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.007306 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007306 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 43679.629975 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43679.629975 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 43538.348011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43538.348011 # average overall mshr miss latency +system.cpu.dcache.replacements 2307 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 411.700494 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 375512 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 133.302094 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 411.700494 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 768119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 768119 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 440535000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/sjeng/config.ini b/TAGE_SC_L/sjeng/config.ini new file mode 100644 index 000000000..607a442e0 --- /dev/null +++ b/TAGE_SC_L/sjeng/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//data/ref/input/ref.txt +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + 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+app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/sjeng/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/sjeng/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] 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+ "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/sjeng/fs/proc/cpuinfo b/TAGE_SC_L/sjeng/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/sjeng/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/sjeng/fs/proc/stat b/TAGE_SC_L/sjeng/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/sjeng/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/online b/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/sjeng/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/sjeng/ref.out b/TAGE_SC_L/sjeng/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/sjeng/stats.txt b/TAGE_SC_L/sjeng/stats.txt new file mode 100644 index 000000000..59fd1bd5e --- /dev/null +++ b/TAGE_SC_L/sjeng/stats.txt @@ -0,0 +1,1415 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 980748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 83024 # Simulator instruction rate (inst/s) +host_mem_usage 855296 # Number of bytes of host memory used +host_op_rate 83598 # Simulator op (including micro ops) rate (op/s) +host_seconds 12.05 # Real time elapsed on the host +host_tick_rate 81422754 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1006944 # Number of ops (including micro ops) simulated +sim_seconds 0.000981 # Number of seconds simulated +sim_ticks 980748500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.766989 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 200381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 200849 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 660 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 202147 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 162 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 162 # Number of indirect misses. +system.cpu.branchPred.lookups 207743 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 3582 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 126240 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 3154 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 126668 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 824 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 236 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 591 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1040 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 362 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 238 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2732 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 10706 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 413 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 561 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 267 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 33 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 100795 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 291 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 581 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 242 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2000 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 18 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 916 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1438 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2770 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 201 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3784 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 171 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 10709 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 162 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 561 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 32 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 28293 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 9 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 41 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2330 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 763581 # number of cc regfile reads +system.cpu.cc_regfile_writes 763725 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 463 # The number of times a branch was mispredicted +system.cpu.commit.branches 134686 # Number of branches committed +system.cpu.commit.bw_lim_events 49449 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 31 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 198975 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000027 # Number of instructions committed +system.cpu.commit.committedOps 1006970 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1903352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.581430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1624847 85.37% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 85631 4.50% 89.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12379 0.65% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 49231 2.59% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 58284 3.06% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21793 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 971 0.05% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 767 0.04% 97.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 49449 2.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1903352 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2158 # Number of function calls committed. +system.cpu.commit.int_insts 879162 # Number of committed integer instructions. +system.cpu.commit.loads 161698 # Number of loads committed +system.cpu.commit.membars 20 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 625681 62.14% 62.14% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 633 0.06% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 19 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 23 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161698 16.06% 78.26% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 218868 21.74% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1006970 # Class of committed instruction +system.cpu.commit.refs 380566 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 339 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1006944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.961496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.961496 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1647816 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 185395 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1239183 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 79217 # Number of cycles decode is idle +system.cpu.decode.RunCycles 142072 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1988 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 753 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 57398 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 207743 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 64422 # Number of cache lines fetched +system.cpu.fetch.Cycles 1852627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 408 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1295277 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.105910 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 73603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 202711 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.660351 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.676031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.761491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1643977 85.25% 85.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3025 0.16% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25385 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1234 0.06% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 190628 9.88% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4849 0.25% 96.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6124 0.32% 97.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3430 0.18% 97.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 49839 2.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 33007 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 539 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 184716 # Number of branches executed +system.cpu.iew.exec_nop 50 # number of nop insts executed +system.cpu.iew.exec_rate 0.617105 # Inst execution rate +system.cpu.iew.exec_refs 432521 # number of memory reference insts executed +system.cpu.iew.exec_stores 268651 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 24614 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 162739 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 269164 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1211943 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 163870 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 682 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1210451 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 80974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1988 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 81014 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 79369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3749 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1041 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 50295 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 396 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 143 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1569905 # num instructions consuming a value +system.cpu.iew.wb_count 1161920 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.418041 # average fanout of values written-back +system.cpu.iew.wb_producers 656285 # num instructions producing a value +system.cpu.iew.wb_rate 0.592364 # insts written-back per cycle +system.cpu.iew.wb_sent 1208711 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1602908 # number of integer regfile reads +system.cpu.int_regfile_writes 757605 # number of integer regfile writes +system.cpu.ipc 0.509815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.509815 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 777546 64.20% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 635 0.05% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 164047 13.54% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 268787 22.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1211134 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 23303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019241 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 569 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21971 94.28% 96.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 758 3.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1233956 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4373200 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1161517 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1416130 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1211854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1211134 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 204944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 237898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1928491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.628022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.395842 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1513888 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 121000 6.27% 84.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31671 1.64% 86.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 101187 5.25% 91.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 108415 5.62% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28444 1.47% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 20642 1.07% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2453 0.13% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 791 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1928491 # Number of insts issued each cycle +system.cpu.iq.rate 0.617454 # Inst issue rate +system.cpu.iq.vec_alu_accesses 474 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 946 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 403 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 719 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2216 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 162739 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 269164 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1877143 # number of misc regfile reads +system.cpu.misc_regfile_writes 81 # number of misc regfile writes +system.cpu.numCycles 1961498 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 106316 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1270067 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 7588 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 100412 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 180 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2955535 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1213947 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1526987 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 176735 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1527719 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1988 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1538180 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 256905 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1606307 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4860 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 99 # count of serializing insts renamed +system.cpu.rename.skidInsts 379312 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 640 # Number of vector rename lookups +system.cpu.rob.rob_reads 3040140 # The number of ROB reads +system.cpu.rob.rob_writes 2437041 # The number of ROB writes +system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 458 # number of vector regfile reads +system.cpu.vec_regfile_writes 126 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 65557 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 164732 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 98357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 350 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 197581 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 350 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 537 # Transaction distribution +system.membus.trans_dist::WritebackDirty 65372 # Transaction distribution +system.membus.trans_dist::CleanEvict 168 # Transaction distribution +system.membus.trans_dist::ReadExReq 2717 # Transaction distribution +system.membus.trans_dist::ReadExResp 2717 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 537 # Transaction distribution +system.membus.trans_dist::InvalidateReq 95921 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 99175 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 99175 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 99175 # Request fanout histogram +system.membus.reqLayer0.occupancy 436705000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 44.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17318250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 563 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 163555 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 71 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 624 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 421 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 142 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 95925 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 95922 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 913 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 295889 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 296802 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 6467712 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 6499200 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 65893 # Total snoops (count) +system.tol2bus.snoopTraffic 4184000 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 165117 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.046057 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 164766 99.79% 99.79% # Request fanout histogram +system.tol2bus.snoop_fanout::1 351 0.21% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 165117 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 197041500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 20.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 52278000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 631500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 6 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 45 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 6 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 45 # number of overall hits +system.l2.demand_misses::.cpu.inst 415 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2839 # number of demand (read+write) misses +system.l2.demand_misses::total 3254 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 415 # number of overall misses +system.l2.overall_misses::.cpu.data 2839 # number of overall misses +system.l2.overall_misses::total 3254 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 32613000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 227186000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 259799000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 32613000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 227186000 # number of overall miss cycles +system.l2.overall_miss_latency::total 259799000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 421 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2878 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3299 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 421 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2878 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3299 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.985748 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.986449 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.986360 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.985748 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.986449 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.986360 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 65375 # number of writebacks +system.l2.writebacks::total 65375 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 415 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2839 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3254 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 415 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2839 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3254 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 28463000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 198796000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 227259000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 28463000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 198796000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 227259000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.986360 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.986360 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.replacements 65893 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 71 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 71 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 71 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 71 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 19 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 19 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 2717 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2717 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19466.567282 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19466.567282 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 23292.165447 # Cycle average of tags in use +system.l2.tags.total_refs 101656 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 98662 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.030346 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 22101.183594 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 161.770983 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1029.210870 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.674475 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.004937 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.031409 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.710820 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 1194 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 10740 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 20834 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1679302 # Number of tag accesses +system.l2.tags.data_accesses 1679302 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 26560 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 181696 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 208256 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 4183808 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4183808 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 415 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2839 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 3254 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 65372 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 65372 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 27081357 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 185262583 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 212343939 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 4265933621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 27081357 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 185262583 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4478277560 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 65372.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 415.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2839.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000056666500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 592 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 592 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 16022 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 67132 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3254 # Number of read requests accepted +system.mem_ctrls.writeReqs 65372 # Number of write requests accepted +system.mem_ctrls.readBursts 3254 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 65372 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 274 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 191 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 189 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 176 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 217 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 178 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 308 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 302 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 4057 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 4030 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 3888 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3947 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 4046 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 4088 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 4091 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 4144 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 4157 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 4156 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 4121 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 4102 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 4228 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 4107 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 16.38 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 31713500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 16270000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 92726000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9746.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28496.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 17 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2870 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 61148 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.20 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 93.54 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3254 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 65372 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1468 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1234 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 491 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length 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275 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 260 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 266 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 202 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 299 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 277 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 304 # What write queue length does an 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215.926431 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 106 2.31% 2.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 81 1.77% 4.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 52 1.13% 5.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 90 1.96% 7.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 37 0.81% 7.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 38 0.83% 8.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 32 0.70% 9.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 64 1.40% 10.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4087 89.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4587 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 592 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 5.496622 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 133.738576 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 591 99.83% 99.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::3200-3327 1 0.17% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 592 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 592 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 110.395270 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 97.326672 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 53.606284 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16-23 9 1.52% 1.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24-31 17 2.87% 4.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32-39 10 1.69% 6.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40-47 3 0.51% 6.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48-55 73 12.33% 18.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::56-63 2 0.34% 19.26% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::64-71 7 1.18% 20.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::72-79 2 0.34% 20.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::80-87 108 18.24% 39.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::88-95 3 0.51% 39.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::96-103 6 1.01% 40.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::104-111 8 1.35% 41.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::112-119 104 17.57% 59.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::120-127 2 0.34% 59.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::128-135 172 29.05% 88.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::168-175 13 2.20% 91.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::176-183 9 1.52% 92.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::184-191 6 1.01% 93.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::192-199 9 1.52% 95.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::200-207 3 0.51% 95.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::216-223 1 0.17% 95.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::248-255 2 0.34% 96.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::256-263 2 0.34% 96.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::264-271 3 0.51% 96.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::272-279 8 1.35% 98.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::288-295 1 0.17% 98.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::296-303 4 0.68% 99.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::304-311 2 0.34% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::312-319 3 0.51% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 592 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 208256 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 4182656 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 208256 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4183808 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 212.34 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 4264.76 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 212.34 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 4265.93 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 34.98 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.66 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 33.32 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 980732500 # Total gap between requests +system.mem_ctrls.avgGap 14290.98 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 26560 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 181696 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 4182656 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 27081356.739265978336 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 185262582.609099060297 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 4264759008.043346405029 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 415 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2839 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 65372 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 11386750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 81339250 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 18580665500 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27437.95 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28650.67 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 284229.72 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 93.29 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 16529100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 8774040 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 12580680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 172578420 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 76830000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 274550760 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 145406880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 707249880 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 721.132767 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 366755250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 32500000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 581493250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 16243500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 8629830 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 10652880 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 168559020 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 76830000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 263855280 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 154413600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 699184110 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 712.908671 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 389815250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 32500000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 558433250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 63866 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 63866 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 63866 # number of overall hits +system.cpu.icache.overall_hits::total 63866 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 556 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 556 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 556 # number of overall misses +system.cpu.icache.overall_misses::total 556 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 41925996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41925996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 41925996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41925996 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 64422 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 64422 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 64422 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 64422 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.008631 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008631 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.008631 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008631 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 75406.467626 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75406.467626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 75406.467626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75406.467626 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 750 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 71 # number of writebacks +system.cpu.icache.writebacks::total 71 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 135 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 135 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 135 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 135 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 421 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 421 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 421 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 33317496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33317496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 33317496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33317496 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.006535 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006535 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.006535 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006535 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79138.945368 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79138.945368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79138.945368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79138.945368 # average overall mshr miss latency +system.cpu.icache.replacements 71 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 63866 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 63866 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 556 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 556 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 41925996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41925996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 64422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 64422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.008631 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008631 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 75406.467626 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75406.467626 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 135 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 135 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 421 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 33317496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33317496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.006535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79138.945368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79138.945368 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 342.131404 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64287 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 152.700713 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 342.131404 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.668225 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.668225 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 350 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 129265 # Number of tag accesses +system.cpu.icache.tags.data_accesses 129265 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 259100 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 259100 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 259105 # number of overall hits +system.cpu.dcache.overall_hits::total 259105 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 118319 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 118319 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 118322 # number of overall misses +system.cpu.dcache.overall_misses::total 118322 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 4566099668 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4566099668 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 4566099668 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4566099668 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 377419 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 377419 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 377427 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 377427 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.313495 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.313495 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.313496 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.313496 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 38591.432213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38591.432213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 38590.453745 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38590.453745 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1475466 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91881 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.058445 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 98182 # number of writebacks +system.cpu.dcache.writebacks::total 98182 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 19519 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 19519 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 19519 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 19519 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 98800 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 98800 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 98803 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 98803 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 3303197052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3303197052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 3303459052 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3303459052 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.261778 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.261778 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.261780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.261780 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 33433.168543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33433.168543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 33434.805137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33434.805137 # average overall mshr miss latency +system.cpu.dcache.replacements 98288 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 158208 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 158208 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 390 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 390 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 158598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.002459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 67152.564103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67152.564103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10303500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10303500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 74663.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74663.043478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 100892 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 100892 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 22008 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22008 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 1372654102 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1372654102 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 122900 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 122900 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.179072 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.179072 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 62370.688023 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62370.688023 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 19267 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19267 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 2741 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2741 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 221554486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 221554486 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.022303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.022303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 80829.801532 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80829.801532 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 500.623213 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 357948 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 98800 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.622955 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 500.623213 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 512 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 853742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 853742 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 980748500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L/xalancbmk/config.ini b/TAGE_SC_L/xalancbmk/config.ini new file mode 100644 index 000000000..3d95bf859 --- /dev/null +++ b/TAGE_SC_L/xalancbmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 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+type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 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+clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross -v /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/t5.xml /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/xalanc.xsl +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L/xalancbmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L/xalancbmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L/xalancbmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L/xalancbmk/config.json b/TAGE_SC_L/xalancbmk/config.json new file mode 100644 index 000000000..eb00f21f7 --- /dev/null +++ b/TAGE_SC_L/xalancbmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L/xalancbmk/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L/xalancbmk/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L/xalancbmk/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + 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1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[2]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.itb", + "type": "ArmTLB", + "size": 64 + }, + "fetchWidth": 8, + "cpu_id": 0, + "fetchToDecodeDelay": 1, + "renameToDecodeDelay": 1, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [ + "ON", + "CLK_GATED", + "OFF" + ], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.power_state", + "type": "PowerState", + "leaders": [] + }, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": [], + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "Process", + "executable": "/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", + "cwd": "/home/min/a/bnwachuk/Final/gem5", + "pgid": 100, + "simpoint": 0, + "euid": 100, + "input": "cin", + "path": "system.cpu.workload", + "name": "workload", + "cmd": [ + "/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross", + "-v", + "/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/t5.xml", + "/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/xalanc.xsl" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + 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"name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L/xalancbmk/fs/proc/cpuinfo b/TAGE_SC_L/xalancbmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L/xalancbmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L/xalancbmk/fs/proc/stat b/TAGE_SC_L/xalancbmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L/xalancbmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/online b/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/possible b/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L/xalancbmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L/xalancbmk/ref.out b/TAGE_SC_L/xalancbmk/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L/xalancbmk/stats.txt b/TAGE_SC_L/xalancbmk/stats.txt new file mode 100644 index 000000000..e6077d6a0 --- /dev/null +++ b/TAGE_SC_L/xalancbmk/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 579856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 94885 # Simulator instruction rate (inst/s) +host_mem_usage 890804 # Number of bytes of host memory used +host_op_rate 115368 # Simulator op (including micro ops) rate (op/s) +host_seconds 10.54 # Real time elapsed on the host +host_tick_rate 55018206 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1215895 # Number of ops (including micro ops) simulated +sim_seconds 0.000580 # Number of seconds simulated +sim_ticks 579856000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 92.857196 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 125269 # Number of BTB hits +system.cpu.branchPred.BTBLookups 134905 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 107 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 11090 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 208840 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2001 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 5384 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 3383 # Number of indirect misses. +system.cpu.branchPred.lookups 273110 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 99747 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 76380 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 95577 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80550 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 1187 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 233 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 19143 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3731 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1461 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2431 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1071 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 834 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2172 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2216 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3513 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1300 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1037 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 983 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1106 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1086 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 406 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 255 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 39 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 17 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2272 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 369 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 806 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 125944 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2445 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2345 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 11110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1906 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3138 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 862 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4631 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1319 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1155 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 629 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 847 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 575 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 23 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39556 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 358 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1467 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 22387 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 987 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 419976 # number of cc regfile reads +system.cpu.cc_regfile_writes 419014 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 7417 # The number of times a branch was mispredicted +system.cpu.commit.branches 221019 # Number of branches committed +system.cpu.commit.bw_lim_events 61414 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 571 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 143338 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001904 # Number of instructions committed +system.cpu.commit.committedOps 1217799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 902904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.338428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 554856 61.45% 61.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 105154 11.65% 73.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72671 8.05% 81.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36450 4.04% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25173 2.79% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23567 2.61% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17219 1.91% 92.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6400 0.71% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61414 6.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902904 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 16953 # Number of function calls committed. +system.cpu.commit.int_insts 1112699 # Number of committed integer instructions. +system.cpu.commit.loads 173888 # Number of loads committed +system.cpu.commit.membars 554 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 844574 69.35% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1323 0.11% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 95 0.01% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 2 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 21 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 22 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 55 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 173888 14.28% 83.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 197792 16.24% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1217799 # Class of committed instruction +system.cpu.commit.refs 371680 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1107 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1215895 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.159715 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.159715 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 374344 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 3766 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 125047 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1416652 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 260178 # Number of cycles decode is idle +system.cpu.decode.RunCycles 263754 # Number of cycles decode is running +system.cpu.decode.SquashCycles 7605 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 14784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 19324 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 273110 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 214136 # Number of cache lines fetched +system.cpu.fetch.Cycles 589369 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5867 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1237549 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 165 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 22604 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.235498 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 324221 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 149657 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.067115 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 925205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.614934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.765819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 597384 64.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 80324 8.68% 73.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34451 3.72% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27811 3.01% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24777 2.68% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24101 2.60% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15521 1.68% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17941 1.94% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102895 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 925205 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 234510 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9099 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 236093 # Number of branches executed +system.cpu.iew.exec_nop 2122 # number of nop insts executed +system.cpu.iew.exec_rate 1.139700 # Inst execution rate +system.cpu.iew.exec_refs 411841 # number of memory reference insts executed +system.cpu.iew.exec_stores 208001 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 23049 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199610 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 629 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4062 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 215816 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1362258 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 203840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11775 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1321727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 48124 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 7605 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 48219 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 4300 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 26 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11458 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25721 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 18022 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 108 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 5522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3577 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1201356 # num instructions consuming a value +system.cpu.iew.wb_count 1299572 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.538563 # average fanout of values written-back +system.cpu.iew.wb_producers 647006 # num instructions producing a value +system.cpu.iew.wb_rate 1.120596 # insts written-back per cycle +system.cpu.iew.wb_sent 1304297 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1618351 # number of integer regfile reads +system.cpu.int_regfile_writes 892161 # number of integer regfile writes +system.cpu.ipc 0.862281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.862281 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 32 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 915262 68.64% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1337 0.10% 68.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 103 0.01% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 2 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 23 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 24 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 65 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 206702 15.50% 84.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 209919 15.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1333503 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 11914 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008934 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3953 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4390 36.85% 70.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3571 29.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1343852 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3602156 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1298270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1502413 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1359507 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1333503 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 629 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 144232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 58 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 86393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 925205 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.441305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.054051 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 498135 53.84% 53.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 118576 12.82% 66.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 83984 9.08% 75.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64521 6.97% 82.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52354 5.66% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39145 4.23% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42831 4.63% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14003 1.51% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11656 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 925205 # Number of insts issued each cycle +system.cpu.iq.rate 1.149854 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1533 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3047 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1302 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2061 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 9744 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13227 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 215816 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 935747 # number of misc regfile reads +system.cpu.misc_regfile_writes 2172 # number of misc regfile writes +system.cpu.numCycles 1159715 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 76994 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1229281 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 8458 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 273167 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 4162 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2182900 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1394927 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1400311 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 268873 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 102227 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 7605 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 124732 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171018 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1710175 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 173834 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.skidInsts 98664 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 639 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1643 # Number of vector rename lookups +system.cpu.rob.rob_reads 2201236 # The number of ROB reads +system.cpu.rob.rob_writes 2744762 # The number of ROB writes +system.cpu.timesIdled 3555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1296 # number of vector regfile reads +system.cpu.vec_regfile_writes 152 # number of vector regfile writes +system.cpu.workload.numSyscalls 28 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 7702 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 8 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 10142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 21309 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 4080 # Transaction distribution +system.membus.trans_dist::ReadExReq 3453 # Transaction distribution +system.membus.trans_dist::ReadExResp 3453 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4080 # Transaction distribution +system.membus.trans_dist::InvalidateReq 169 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7702 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7702 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7702 # Request fanout histogram +system.membus.reqLayer0.occupancy 9544500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 39849750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 7371 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 3884 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 5199 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1059 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 5712 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1659 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 172 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 172 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 16622 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15853 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 32475 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 698240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 586688 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1284928 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 11167 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000716 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.026757 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 11159 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 8 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 11167 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 19737500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8012496 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 8568499 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2643 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 818 # number of demand (read+write) hits +system.l2.demand_hits::total 3461 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2643 # number of overall hits +system.l2.overall_hits::.cpu.data 818 # number of overall hits +system.l2.overall_hits::total 3461 # number of overall hits +system.l2.demand_misses::.cpu.inst 3068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4465 # number of demand (read+write) misses +system.l2.demand_misses::total 7533 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 3068 # number of overall misses +system.l2.overall_misses::.cpu.data 4465 # number of overall misses +system.l2.overall_misses::total 7533 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 244130500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 348269000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 592399500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 244130500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 348269000 # number of overall miss cycles +system.l2.overall_miss_latency::total 592399500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 5711 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5283 # number of demand (read+write) accesses +system.l2.demand_accesses::total 10994 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 5711 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5283 # number of overall (read+write) accesses +system.l2.overall_accesses::total 10994 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.537209 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.845164 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.685192 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.537209 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.845164 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.685192 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 3068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4465 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 7533 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 3068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4465 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 7533 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 213450500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 303619000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 517069500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 213450500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 303619000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 517069500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.685192 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.685192 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 5196 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 5196 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 5196 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 5196 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 171 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 171 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3453 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3453 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1659 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1659 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.610006 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.610006 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81765.810277 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81765.810277 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1012 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1012 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 72627000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 72627000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.610006 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.610006 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 3 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 3 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 169 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 169 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19147.928994 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19147.928994 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3795.325559 # Cycle average of tags in use +system.l2.tags.total_refs 21134 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 7705 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.742894 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 104.826620 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1882.074184 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1808.424755 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003199 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.057436 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.055189 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.115824 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 7702 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 6364 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.235046 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 178129 # Number of tag accesses +system.l2.tags.data_accesses 178129 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 196352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 285760 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 482112 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 3068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4465 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 7533 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 338622003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 492812008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 831434011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 338622003 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 492812008 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 831434011 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 3068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4465.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000681500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 15052 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 7533 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 7533 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 615 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 664 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 376 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 668 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 653 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 381 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 361 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 344 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 303 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 438 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 468 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 542 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 626 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.48 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 65889750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 37665000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 207133500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8746.81 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27496.81 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 6067 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.54 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 7533 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 4675 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 2113 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 553 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1463 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 328.136705 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 196.673606 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 334.671504 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 480 32.81% 32.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 368 25.15% 57.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 159 10.87% 68.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 110 7.52% 76.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 46 3.14% 79.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 53 3.62% 83.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 33 2.26% 85.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 19 1.30% 86.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 195 13.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1463 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 482112 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 482112 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 831.43 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 831.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 6.50 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 579750500 # Total gap between requests +system.mem_ctrls.avgGap 76961.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 196352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 285760 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 338622002.704119622707 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 492812008.498661696911 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 3068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4465 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 87227000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 119906500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28431.23 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26854.76 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.54 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3991260 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2117610 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24782940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 209475570 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46264320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 332115060 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 572.754373 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 118055750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 19240000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 442560250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6475980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3434475 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 29002680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 254494740 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 8353440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 347244675 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 598.846395 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 18199250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 19240000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 542416750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 207011 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 207011 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 207011 # number of overall hits +system.cpu.icache.overall_hits::total 207011 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 7122 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7122 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 7122 # number of overall misses +system.cpu.icache.overall_misses::total 7122 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 351779497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351779497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 351779497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351779497 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 214133 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 214133 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 214133 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 214133 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.033260 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.033260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.033260 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033260 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1632 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 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latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.708463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 67960.186319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67960.186319 # average overall mshr miss latency +system.cpu.dcache.replacements 4943 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 185501 # number of ReadReq accesses(hits+misses) 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accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 197185 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 57500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 57500 # average SoftPFReq mshr miss latency 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average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32179.958333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 476.083078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348169 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5455 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.825665 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 476.083078 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 774617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 774617 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 579856000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/config.ini b/TAGE_SC_L_benchmarks/GemsFDTD/config.ini new file mode 100644 index 000000000..968b36d1d --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 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+[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/GemsFDTD/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/GemsFDTD/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/GemsFDTD/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/config.json b/TAGE_SC_L_benchmarks/GemsFDTD/config.json new file mode 100644 index 000000000..f5ac214b2 --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/GemsFDTD/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/GemsFDTD/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/GemsFDTD/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 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"power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + 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"numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + 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+ "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/stat b/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/ref.log b/TAGE_SC_L_benchmarks/GemsFDTD/ref.log new file mode 100644 index 000000000..f40519fd2 --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/ref.log @@ -0,0 +1,5 @@ + Welcome to GemsFDTD + + EXECUTION HALTED ! (in Check_open) + Application could not open file yee.dat + The value of ios was: 2 diff --git a/TAGE_SC_L_benchmarks/GemsFDTD/stats.txt b/TAGE_SC_L_benchmarks/GemsFDTD/stats.txt new file mode 100644 index 000000000..a61a85370 --- /dev/null +++ b/TAGE_SC_L_benchmarks/GemsFDTD/stats.txt @@ -0,0 +1,1357 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 61962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 85781 # Simulator instruction rate (inst/s) +host_mem_usage 855276 # Number of bytes of host memory used +host_op_rate 104713 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.34 # Real time elapsed on the host +host_tick_rate 180977878 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 29355 # Number of instructions simulated +sim_ops 35849 # Number of ops (including micro ops) simulated +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 61962500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.723205 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 4252 # Number of BTB hits +system.cpu.branchPred.BTBLookups 5542 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 10 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8981 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 497 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 457 # Number of indirect misses. +system.cpu.branchPred.lookups 12734 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2775 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 2242 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2728 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 2289 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 99 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 265 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 82 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 24 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 20 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 56 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 9 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 16 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 48 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 19 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 157 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 4 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 50 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 3609 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 603 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 184 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 27 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 43 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 61 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 14 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 358 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 24 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1041 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 131 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 10477 # number of cc regfile reads +system.cpu.cc_regfile_writes 10350 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 934 # The number of times a branch was mispredicted +system.cpu.commit.branches 6765 # Number of branches committed +system.cpu.commit.bw_lim_events 1464 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 48 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14283 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 29435 # Number of instructions committed +system.cpu.commit.committedOps 35929 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 47276 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.759984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.826531 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36313 76.81% 76.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3795 8.03% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1998 4.23% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1237 2.62% 91.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 892 1.89% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 730 1.54% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 432 0.91% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 415 0.88% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1464 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 47276 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 609 # Number of function calls committed. +system.cpu.commit.int_insts 32730 # Number of committed integer instructions. +system.cpu.commit.loads 5438 # Number of loads committed +system.cpu.commit.membars 24 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 24199 67.35% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 53 0.15% 67.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 6 0.02% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.07% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 32 0.09% 67.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.08% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 38 0.11% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 5438 15.14% 83.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6102 16.98% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 35929 # Class of committed instruction +system.cpu.commit.refs 11540 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 477 # Number of committed Vector instructions. +system.cpu.committedInsts 29355 # Number of Instructions Simulated +system.cpu.committedOps 35849 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.221632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.221632 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 15232 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 516 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4408 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 55880 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23119 # Number of cycles decode is idle +system.cpu.decode.RunCycles 9540 # Number of cycles decode is running +system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1797 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 778 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 12734 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7861 # Number of cache lines fetched +system.cpu.fetch.Cycles 20839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 901 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 55013 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2968 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.102755 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 5333 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.443918 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 49646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.316078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.623215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 37422 75.38% 75.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1043 2.10% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1301 2.62% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1176 2.37% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1493 3.01% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 985 1.98% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 951 1.92% 89.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 638 1.29% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4637 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 49646 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 74280 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1117 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 8135 # Number of branches executed +system.cpu.iew.exec_nop 169 # number of nop insts executed +system.cpu.iew.exec_rate 0.366243 # Inst execution rate +system.cpu.iew.exec_refs 14525 # number of memory reference insts executed +system.cpu.iew.exec_stores 6953 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2520 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 7866 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8014 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 50287 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 7572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 45387 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 734 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 752 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 105 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2428 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1912 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 897 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 38852 # num instructions consuming a value +system.cpu.iew.wb_count 43582 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.561155 # average fanout of values written-back +system.cpu.iew.wb_producers 21802 # num instructions producing a value +system.cpu.iew.wb_rate 0.351678 # insts written-back per cycle +system.cpu.iew.wb_sent 44447 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 50533 # number of integer regfile reads +system.cpu.int_regfile_writes 31002 # number of integer regfile writes +system.cpu.ipc 0.236875 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.236875 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 31303 67.04% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 54 0.12% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.01% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.07% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.09% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 36 0.08% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 45 0.10% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 7886 16.89% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7275 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 46692 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 660 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014135 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 201 30.45% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.30% 30.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.45% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 201 30.45% 61.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 253 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 46706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 142541 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 43022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 63464 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 50040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 46692 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 49646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.940499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 34591 69.68% 69.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3579 7.21% 76.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 3204 6.45% 83.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2742 5.52% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2133 4.30% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1590 3.20% 96.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1016 2.05% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 427 0.86% 99.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 364 0.73% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 49646 # Number of insts issued each cycle +system.cpu.iq.rate 0.376773 # Inst issue rate +system.cpu.iq.vec_alu_accesses 637 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1294 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 560 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 945 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 112 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 7866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8014 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 35114 # number of misc regfile reads +system.cpu.misc_regfile_writes 97 # number of misc regfile writes +system.cpu.numCycles 123926 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3665 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 33835 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 210 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 24047 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 128 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 76045 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 53101 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 49590 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 9354 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1484 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2164 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15755 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 59261 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9439 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 343 # count of serializing insts renamed +system.cpu.rename.skidInsts 3984 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 80 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 803 # Number of vector rename lookups +system.cpu.rob.rob_reads 95673 # The number of ROB reads +system.cpu.rob.rob_writes 102806 # The number of ROB writes +system.cpu.timesIdled 740 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 621 # number of vector regfile reads +system.cpu.vec_regfile_writes 183 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1306 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 648 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 2137 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1064 # Transaction distribution +system.membus.trans_dist::ReadExReq 178 # Transaction distribution +system.membus.trans_dist::ReadExResp 178 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1065 # Transaction distribution +system.membus.trans_dist::InvalidateReq 63 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1306 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1306 # Request fanout histogram +system.membus.reqLayer0.occupancy 1614000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 6586250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1243 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 50 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 543 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 54 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 182 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 182 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1029 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 216 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 63 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 63 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2599 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1026 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3625 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 100480 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 129152 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1490 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001342 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.036625 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1488 99.87% 99.87% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1490 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1661500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 628500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1540500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 144 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 183 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 144 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 183 # number of overall hits +system.l2.demand_misses::.cpu.inst 885 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 359 # number of demand (read+write) misses +system.l2.demand_misses::total 1244 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 885 # number of overall misses +system.l2.overall_misses::.cpu.data 359 # number of overall misses +system.l2.overall_misses::total 1244 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69107000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 30532500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 99639500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69107000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 30532500 # number of overall miss cycles +system.l2.overall_miss_latency::total 99639500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1029 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 398 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1427 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1029 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 398 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1427 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.860058 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.902010 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.871759 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.860058 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.902010 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.871759 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 885 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 359 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1244 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 885 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 359 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1244 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60277000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 26942001 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 87219001 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60277000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 26942001 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 87219001 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.871759 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.871759 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 50 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 50 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 543 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 543 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 543 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 543 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 4 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 4 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 178 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 178 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 63 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 63 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19015.873016 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19015.873016 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 674.522414 # Cycle average of tags in use +system.l2.tags.total_refs 2071 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1248 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.659455 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.805164 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 455.337647 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 217.379603 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013896 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006634 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.020585 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1248 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.038086 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 18336 # Number of tag accesses +system.l2.tags.data_accesses 18336 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56576 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 22976 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 79552 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 884 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 359 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1243 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 913068388 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 370804922 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1283873310 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 913068388 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 370804922 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1283873310 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 884.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 359.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000554500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2436 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1243 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1243 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 151 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 25 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 12775500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6215000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 36081750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10277.96 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29027.96 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 971 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.12 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1243 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 698 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 361 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 260 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 297.107692 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.423498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.377322 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 30.00% 30.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 65 25.00% 55.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45 17.31% 72.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 19 7.31% 79.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 6.15% 85.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 3.46% 89.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 1.92% 91.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 2.31% 93.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 6.54% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 260 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 79552 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 79552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1283.87 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1283.87 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.03 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 61929000 # Total gap between requests +system.mem_ctrls.avgGap 49822.20 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56576 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 22976 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 913068388.137986779213 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 370804922.332055687904 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 884 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 359 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23954000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 12127750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27097.29 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33782.03 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1185240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 607200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4976580 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 27790920 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 390720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 39253140 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 633.498326 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 824000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 59318500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 756840 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3898440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 27598260 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 552960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 37488480 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 605.018842 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1232500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 58910000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6542 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6542 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6542 # number of overall hits +system.cpu.icache.overall_hits::total 6542 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1319 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1319 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1319 # number of overall misses +system.cpu.icache.overall_misses::total 1319 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 91010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 91010500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7861 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.167790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.167790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.167790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.167790 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 543 # number of writebacks +system.cpu.icache.writebacks::total 543 # number of writebacks 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296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5082 # number of WriteReq hits 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358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 231.645691 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12141 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 461 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.336226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 231.645691 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 26849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 26849 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 61962500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/astar/config.ini b/TAGE_SC_L_benchmarks/astar/config.ini new file mode 100644 index 000000000..e7e9d3130 --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 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+eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/473.astar/data/ref/input/rivers.cfg +cwd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lake.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/astar/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/astar/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/astar/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/astar/config.json b/TAGE_SC_L_benchmarks/astar/config.json new file mode 100644 index 000000000..0830c29b6 --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/astar/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/astar/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/astar/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": 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+ "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/astar/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/astar/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/astar/fs/proc/stat b/TAGE_SC_L_benchmarks/astar/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/astar/lake.out b/TAGE_SC_L_benchmarks/astar/lake.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/astar/stats.txt b/TAGE_SC_L_benchmarks/astar/stats.txt new file mode 100644 index 000000000..734b07300 --- /dev/null +++ b/TAGE_SC_L_benchmarks/astar/stats.txt @@ -0,0 +1,1343 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 442981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 154853 # Simulator instruction rate (inst/s) +host_mem_usage 855464 # Number of bytes of host memory used +host_op_rate 155465 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.46 # Real time elapsed on the host +host_tick_rate 68595096 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1003978 # Number of ops (including micro ops) simulated +sim_seconds 0.000443 # Number of seconds simulated +sim_ticks 442981000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.317962 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 134261 # Number of BTB hits +system.cpu.branchPred.BTBLookups 135183 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1145 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 138678 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 6 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 205 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 199 # Number of indirect misses. +system.cpu.branchPred.lookups 140939 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 79284 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 37376 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2331 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 114329 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 63 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 10 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 380 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 17819 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 50 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1562 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1678 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3130 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3913 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 5853 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 20479 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 18538 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 26408 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 222 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 5 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 82 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 14960 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 460 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 346 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 17819 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 22 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 811 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1560 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 173 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1672 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3130 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 3918 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 5853 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 20477 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 18538 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 26408 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 128 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 100569 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 73 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 24 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 551 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 66 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 387693 # number of cc regfile reads +system.cpu.cc_regfile_writes 387595 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 800 # The number of times a branch was mispredicted +system.cpu.commit.branches 117621 # Number of branches committed +system.cpu.commit.bw_lim_events 92202 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 84 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 64674 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000203 # Number of instructions committed +system.cpu.commit.committedOps 1004181 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 819030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.226061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.598946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 613257 74.88% 74.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47765 5.83% 80.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19692 2.40% 83.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15401 1.88% 84.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25173 3.07% 88.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2202 0.27% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1855 0.23% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1483 0.18% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 92202 11.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 819030 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 280 # Number of function calls committed. +system.cpu.commit.int_insts 888121 # Number of committed integer instructions. +system.cpu.commit.loads 355397 # Number of loads committed +system.cpu.commit.membars 58 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 531746 52.95% 52.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 11 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 6 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 16 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 8 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 11 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 18 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 18 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 2 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 15 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 355397 35.39% 88.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 116855 11.64% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1004181 # Class of committed instruction +system.cpu.commit.refs 472252 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 465 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1003978 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.885963 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.885963 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 625945 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 360 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 130316 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1082831 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 33701 # Number of cycles decode is idle +system.cpu.decode.RunCycles 131525 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1250 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1261 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 35198 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 140939 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7771 # Number of cache lines fetched +system.cpu.fetch.Cycles 802963 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 650 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1100160 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3190 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.159080 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22986 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 134818 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.241767 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 827619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.336913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590994 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 599084 72.39% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 747 0.09% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 88472 10.69% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 713 0.09% 83.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44145 5.33% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 569 0.07% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1714 0.21% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 484 0.06% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 91691 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 827619 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 58344 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 978 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 131695 # Number of branches executed +system.cpu.iew.exec_nop 325 # number of nop insts executed +system.cpu.iew.exec_rate 1.217345 # Inst execution rate +system.cpu.iew.exec_refs 502146 # number of memory reference insts executed +system.cpu.iew.exec_stores 130059 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 13495 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 359106 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 111 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 131145 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1070563 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 372087 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1078523 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 32025 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 32094 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 20859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 129 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 154 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3691 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 14285 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 701 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 277 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1229053 # num instructions consuming a value +system.cpu.iew.wb_count 1051267 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.619020 # average fanout of values written-back +system.cpu.iew.wb_producers 760808 # num instructions producing a value +system.cpu.iew.wb_rate 1.186581 # insts written-back per cycle +system.cpu.iew.wb_sent 1063740 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1483049 # number of integer regfile reads +system.cpu.int_regfile_writes 803389 # number of integer regfile writes +system.cpu.ipc 1.128715 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.128715 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 6 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 576727 53.42% 53.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 12 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 11 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 6 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 16 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 8 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 11 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 22 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 23 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 2 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 372388 34.49% 87.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 130245 12.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1079565 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 17838 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016523 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205 1.15% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 14 0.08% 1.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 21 0.12% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 16007 89.74% 91.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1587 8.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1096789 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3003537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1050764 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1135810 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1070127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1079565 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 111 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 66214 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 70706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 827619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.304423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.251098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 572164 69.13% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35200 4.25% 73.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11291 1.36% 74.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 50931 6.15% 80.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47784 5.77% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 42357 5.12% 91.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25411 3.07% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 26245 3.17% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 16236 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 827619 # Number of insts issued each cycle +system.cpu.iq.rate 1.218522 # Inst issue rate +system.cpu.iq.vec_alu_accesses 608 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1152 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 503 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 675 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 137 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 638 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 359106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 131145 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1016138 # number of misc regfile reads +system.cpu.misc_regfile_writes 288 # number of misc regfile writes +system.cpu.numCycles 885963 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 45738 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1118217 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 598 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 50400 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 207676 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2022680 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1073704 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1201363 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 149539 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 355124 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1250 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 571580 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 83084 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1480169 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9112 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 248 # count of serializing insts renamed +system.cpu.rename.skidInsts 143419 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 112 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 677 # Number of vector rename lookups +system.cpu.rob.rob_reads 1790197 # The number of ROB reads +system.cpu.rob.rob_writes 2146359 # The number of ROB writes +system.cpu.timesIdled 548 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 583 # number of vector regfile reads +system.cpu.vec_regfile_writes 187 # number of vector regfile writes +system.cpu.workload.numSyscalls 25 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 26907 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 29802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 2 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 60582 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 2 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2178 # Transaction distribution +system.membus.trans_dist::CleanEvict 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 147 # Transaction distribution +system.membus.trans_dist::ReadExResp 147 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2178 # Transaction distribution +system.membus.trans_dist::InvalidateReq 24580 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 29232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 29232 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 148800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 148800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 26905 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 26905 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 26905 # Request fanout histogram +system.membus.reqLayer0.occupancy 28748000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 12279750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2277 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 28182 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 315 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1309 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3923 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3922 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 780 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1497 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 24580 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 24580 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1875 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 89486 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 91361 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 70080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 2150464 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2220544 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 4 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 30784 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000097 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.009872 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 30781 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 30784 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 58788000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 13.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 20418500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 4.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1170000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 75 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 3800 # number of demand (read+write) hits +system.l2.demand_hits::total 3875 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 75 # number of overall hits +system.l2.overall_hits::.cpu.data 3800 # number of overall hits +system.l2.overall_hits::total 3875 # number of overall hits +system.l2.demand_misses::.cpu.inst 705 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1620 # number of demand (read+write) misses +system.l2.demand_misses::total 2325 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 705 # number of overall misses +system.l2.overall_misses::.cpu.data 1620 # number of overall misses +system.l2.overall_misses::total 2325 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 55807000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 122184500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 177991500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 55807000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 122184500 # number of overall miss cycles +system.l2.overall_miss_latency::total 177991500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 780 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5420 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6200 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 780 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5420 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6200 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.903846 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.298893 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.375000 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.903846 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.298893 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.375000 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79158.865248 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75422.530864 # average overall miss latency +system.l2.demand_avg_miss_latency::total 76555.483871 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79158.865248 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75422.530864 # average overall miss latency +system.l2.overall_avg_miss_latency::total 76555.483871 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 705 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1620 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2325 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 705 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1620 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2325 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 48757000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 105984500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 154741500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 48757000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 105984500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 154741500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.298893 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.375000 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.298893 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.375000 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65422.530864 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 66555.483871 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65422.530864 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 66555.483871 # average overall mshr miss latency +system.l2.replacements 4 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 28182 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 28182 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 28182 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 28182 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 315 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 315 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 315 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 315 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3776 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3776 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 147 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 147 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 12044500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 12044500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3923 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3923 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.037471 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.037471 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 81935.374150 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 81935.374150 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 147 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 147 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 10574500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 10574500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.037471 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.037471 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 71935.374150 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 71935.374150 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 75 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 75 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 705 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 705 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 55807000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 55807000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 780 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 780 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.903846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.903846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79158.865248 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79158.865248 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 705 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 705 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 48757000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 48757000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.903846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69158.865248 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 24 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 24 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1473 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1473 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 110140000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 110140000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1497 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1497 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.983968 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.983968 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 74772.572980 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 74772.572980 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1473 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1473 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 95410000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 95410000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.983968 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.983968 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 64772.572980 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 64772.572980 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 24580 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 24580 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 24580 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 24580 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 24580 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 24580 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 476098500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 476098500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19369.344996 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19369.344996 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 17279.685171 # Cycle average of tags in use +system.l2.tags.total_refs 36001 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 26905 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.338078 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 16079.129966 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 666.131927 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 534.423278 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.490696 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.020329 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.016309 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.527334 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 26901 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 657 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 26170 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.820953 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 511553 # Number of tag accesses +system.l2.tags.data_accesses 511553 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 45120 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 103680 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 148800 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 45120 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 45120 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 705 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1620 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2325 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 101855384 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 234050670 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 335906055 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 101855384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 101855384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 101855384 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 234050670 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 335906055 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 705.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1620.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000577000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4716 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2325 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2325 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 214 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 209 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 83 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 83 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 163 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 167 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 226 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 287 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.08 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15889750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 11625000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 59483500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6834.30 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 25584.30 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2005 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.24 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2325 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1884 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 289 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 108 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 318 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 464.301887 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 281.376593 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 394.299199 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 75 23.58% 23.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 69 21.70% 45.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 27 8.49% 53.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 12 3.77% 57.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 27 8.49% 66.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 3.46% 69.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 1.89% 71.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.57% 72.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 86 27.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 318 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 148800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 148800 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 335.91 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 335.91 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.62 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.62 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 442858500 # Total gap between requests +system.mem_ctrls.avgGap 190476.77 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 45120 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 103680 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 101855384.316708847880 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 234050670.344777762890 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 705 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1620 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 19741000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 39742500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28001.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24532.41 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.24 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1285200 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10217340 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 82309140 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 100791840 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 229706460 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 518.546981 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 260843000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 167578000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 999600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 523710 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6383160 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 57325470 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 121830720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 221482500 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 499.981941 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 316042750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 112378250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6788 # number of overall hits +system.cpu.icache.overall_hits::total 6788 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 982 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 982 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 982 # number of overall misses +system.cpu.icache.overall_misses::total 982 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 69824999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69824999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 69824999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69824999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7770 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7770 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7770 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7770 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.126384 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.126384 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses 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latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 28629.705979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28629.705979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378769 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 24316 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.576945 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.066667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 28182 # number of writebacks +system.cpu.dcache.writebacks::total 28182 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 40978 # number of demand (read+write) MSHR hits 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number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 58306 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 33914 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 33914 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 314729727 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 314729727 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 92220 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 92220 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.367751 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.367751 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 9280.230200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9280.230200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 29988 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 29988 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 59258770 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59258770 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.042572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.042572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 15093.930209 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15093.930209 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 24577 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 24577 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 808982544 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 808982544 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 24577 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 24577 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32916.244619 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32916.244619 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 24577 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 24577 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 784405544 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 784405544 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31916.244619 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31916.244619 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 475.104284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 433945 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 29999 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.465316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 475.104284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.927938 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.927938 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 979847 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 979847 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 442981000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/bwaves/config.ini b/TAGE_SC_L_benchmarks/bwaves/config.ini new file mode 100644 index 000000000..b500d53d6 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 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+host_paths=TAGE_SC_L_benchmarks/bwaves/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/bwaves/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/bwaves/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/bwaves/config.json b/TAGE_SC_L_benchmarks/bwaves/config.json new file mode 100644 index 000000000..914c8bb25 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], 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[ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": 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"cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + 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"True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { 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0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/bwaves/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/bwaves/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/bwaves/fs/proc/stat b/TAGE_SC_L_benchmarks/bwaves/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/bwaves/stats.txt b/TAGE_SC_L_benchmarks/bwaves/stats.txt new file mode 100644 index 000000000..39c1fa9af --- /dev/null +++ b/TAGE_SC_L_benchmarks/bwaves/stats.txt @@ -0,0 +1,1397 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2378369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 71183 # Simulator instruction rate (inst/s) +host_mem_usage 858380 # Number of bytes of host memory used +host_op_rate 73597 # Simulator op (including micro ops) rate (op/s) +host_seconds 14.05 # Real time elapsed on the host +host_tick_rate 169297449 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1033929 # Number of ops (including micro ops) simulated +sim_seconds 0.002378 # Number of seconds simulated +sim_ticks 2378369000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.771953 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 136892 # Number of BTB hits +system.cpu.branchPred.BTBLookups 138594 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 7 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 18533 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 177123 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 588 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1472 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 884 # Number of indirect misses. +system.cpu.branchPred.lookups 185561 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 75581 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 21590 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 22365 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 74806 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 196 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 679 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 359 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 100 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 51 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 354 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 127 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 104 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 72 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 165 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 54 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 164 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 112 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 153 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 344 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 266 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 286 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 401 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 613 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 854 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2699 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 9454 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 24079 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1815 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1553 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1204 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 27614 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 844 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 192 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 384 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 157 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 184 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 109 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 443 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 148 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 60 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 63 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 139 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 108 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 164 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 300 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 141 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 256 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 343 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 397 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 922 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1456 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 5601 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 29809 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 30659 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 775 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 7812 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2833 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 205 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 328677 # number of cc regfile reads +system.cpu.cc_regfile_writes 340566 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 17987 # The number of times a branch was mispredicted +system.cpu.commit.branches 102118 # Number of branches committed +system.cpu.commit.bw_lim_events 26782 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 162 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 353315 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000217 # Number of instructions committed +system.cpu.commit.committedOps 1034146 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 4632570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.223234 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.967467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 4299727 92.82% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103235 2.23% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 28445 0.61% 95.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72389 1.56% 97.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 82558 1.78% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9442 0.20% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4788 0.10% 99.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5204 0.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 26782 0.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4632570 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1944 # Number of function calls committed. +system.cpu.commit.int_insts 938116 # Number of committed integer instructions. +system.cpu.commit.loads 14759 # Number of loads committed +system.cpu.commit.membars 100 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 396501 38.34% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 174 0.02% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 4 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2813 0.27% 38.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 2810 0.27% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3 0.00% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 15 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 52 0.01% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14759 1.43% 40.34% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 616942 59.66% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1034146 # Class of committed instruction +system.cpu.commit.refs 631701 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 28978 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1033929 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.756740 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.756740 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 4241372 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 563 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117396 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1586891 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 180067 # Number of cycles decode is idle +system.cpu.decode.RunCycles 197238 # Number of cycles decode is running +system.cpu.decode.SquashCycles 19249 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1992 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 49495 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 185561 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 287663 # Number of cache lines fetched +system.cpu.fetch.Cycles 4350270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7143 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1826015 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 39590 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.039010 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 317304 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 140313 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.383880 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 4687421 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.402776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.590550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 4348825 92.78% 92.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16824 0.36% 93.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 8205 0.18% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100126 2.14% 95.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9726 0.21% 95.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 28561 0.61% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8618 0.18% 96.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11338 0.24% 96.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 155198 3.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4687421 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 69319 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 19707 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 119498 # Number of branches executed +system.cpu.iew.exec_nop 293 # number of nop insts executed +system.cpu.iew.exec_rate 0.266983 # Inst execution rate +system.cpu.iew.exec_refs 764673 # number of memory reference insts executed +system.cpu.iew.exec_stores 745527 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 36303 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 19462 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 195 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2418 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 822533 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1387610 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 19146 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 61691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1269971 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2119830 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 19249 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2117384 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 47215 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 497 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 4703 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 205591 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 9167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 10540 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 834910 # num instructions consuming a value +system.cpu.iew.wb_count 1244931 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.370368 # average fanout of values written-back +system.cpu.iew.wb_producers 309224 # num instructions producing a value +system.cpu.iew.wb_rate 0.261719 # insts written-back per cycle +system.cpu.iew.wb_sent 1267715 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2693361 # number of integer regfile reads +system.cpu.int_regfile_writes 401477 # number of integer regfile writes +system.cpu.ipc 0.210228 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210228 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 514474 38.63% 38.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 181 0.01% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 32 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3498 0.26% 38.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 3007 0.23% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 23 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 23 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 19807 1.49% 40.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 790514 59.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1331662 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 90929 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.068282 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 987 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 12 0.01% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 355 0.39% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 89574 98.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1383514 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 7384267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1207905 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1689028 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1387122 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1331662 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 195 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 353388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 359181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 4687421 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.284093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.096581 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4289827 91.52% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107593 2.30% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 58099 1.24% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 45950 0.98% 96.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43828 0.94% 96.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 87848 1.87% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35663 0.76% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7413 0.16% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11200 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4687421 # Number of insts issued each cycle +system.cpu.iq.rate 0.279953 # Inst issue rate +system.cpu.iq.vec_alu_accesses 39073 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 78578 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 37026 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 51706 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 70 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 286 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 19462 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 822533 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1324545 # number of misc regfile reads +system.cpu.misc_regfile_writes 6031 # number of misc regfile writes +system.cpu.numCycles 4756740 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 2153805 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 605959 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 59 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 202563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3686396 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1479083 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 871657 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 220703 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 2069360 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 19249 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2070152 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 265698 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 3143972 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20949 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 667 # count of serializing insts renamed +system.cpu.rename.skidInsts 372322 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 197 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 45801 # Number of vector rename lookups +system.cpu.rob.rob_reads 5977064 # The number of ROB reads +system.cpu.rob.rob_writes 2829843 # The number of ROB writes +system.cpu.timesIdled 878 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 37736 # number of vector regfile reads +system.cpu.vec_regfile_writes 6435 # number of vector regfile writes +system.cpu.workload.numSyscalls 61 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 41715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 116674 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 75274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 151539 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 475 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 991 # Transaction distribution +system.membus.trans_dist::WritebackDirty 41216 # Transaction distribution +system.membus.trans_dist::CleanEvict 499 # Transaction distribution +system.membus.trans_dist::ReadExReq 73861 # Transaction distribution +system.membus.trans_dist::ReadExResp 73860 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 991 # Transaction distribution +system.membus.trans_dist::InvalidateReq 107 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 191525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 191525 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 7428288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 7428288 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 74959 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 74959 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 74959 # Request fanout histogram +system.membus.reqLayer0.occupancy 300234000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 12.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 389480500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1611 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 115521 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 865 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1078 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 74547 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 74543 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1340 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 271 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 107 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 107 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3545 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 224255 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 227800 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 141120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 9543616 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 9684736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 42190 # Total snoops (count) +system.tol2bus.snoopTraffic 2637824 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 118455 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.004018 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.063264 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 117979 99.60% 99.60% # Request fanout histogram +system.tol2bus.snoop_fanout::1 476 0.40% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 118455 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 150939500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 112274500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2010000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 467 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 836 # number of demand (read+write) hits +system.l2.demand_hits::total 1303 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 467 # number of overall hits +system.l2.overall_hits::.cpu.data 836 # number of overall hits +system.l2.overall_hits::total 1303 # number of overall hits +system.l2.demand_misses::.cpu.inst 873 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 73982 # number of demand (read+write) misses +system.l2.demand_misses::total 74855 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 873 # number of overall misses +system.l2.overall_misses::.cpu.data 73982 # number of overall misses +system.l2.overall_misses::total 74855 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69165000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 6999555500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 7068720500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69165000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 6999555500 # number of overall miss cycles +system.l2.overall_miss_latency::total 7068720500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1340 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 74818 # number of demand (read+write) accesses +system.l2.demand_accesses::total 76158 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1340 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 74818 # number of overall (read+write) accesses +system.l2.overall_accesses::total 76158 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.651493 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.988826 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.982891 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.651493 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.988826 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.982891 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79226.804124 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 94611.601471 # average overall miss latency +system.l2.demand_avg_miss_latency::total 94432.175539 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79226.804124 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 94611.601471 # average overall miss latency +system.l2.overall_avg_miss_latency::total 94432.175539 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 41216 # number of writebacks +system.l2.writebacks::total 41216 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 873 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 73982 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 74855 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 873 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 73982 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 74855 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60435000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 6259775500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 6320210500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60435000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 6259775500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 6320210500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.988826 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.982891 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.988826 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.982891 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 84612.142143 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 84432.709906 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 84612.142143 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 84432.709906 # average overall mshr miss latency +system.l2.replacements 42190 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 74305 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 74305 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 74305 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 74305 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 865 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 865 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 865 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 865 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 683 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 683 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 73864 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 73864 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 6989304500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 6989304500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 74547 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 74547 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990838 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990838 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 94623.964313 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 94623.964313 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 73864 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 73864 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 6250704500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 6250704500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990838 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990838 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 84624.505849 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 84624.505849 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 467 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 467 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 873 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 873 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69165000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69165000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1340 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1340 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.651493 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.651493 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79226.804124 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79226.804124 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 873 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 873 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60435000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60435000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.651493 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69226.804124 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 153 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 153 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 118 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 118 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10251000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10251000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 271 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 271 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.435424 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.435424 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86872.881356 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86872.881356 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 118 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 118 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9071000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9071000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.435424 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.435424 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76872.881356 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76872.881356 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 107 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 107 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 107 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 107 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 107 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 107 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2034500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2034500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19014.018692 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19014.018692 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 26084.782711 # Cycle average of tags in use +system.l2.tags.total_refs 151427 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 74958 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.020158 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 38.053228 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 310.191124 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 25736.538359 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001161 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.009466 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.785417 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.796044 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 2582 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 25922 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::3 3978 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1287262 # Number of tag accesses +system.l2.tags.data_accesses 1287262 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 55872 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 4734592 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 4790464 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 55872 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 55872 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 2637824 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 2637824 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 873 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 73978 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 74851 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 41216 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 41216 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 23491729 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1990688577 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2014180306 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 23491729 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 23491729 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1109089464 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1109089464 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1109089464 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 23491729 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1990688577 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3123269770 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 41216.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 873.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 73979.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000174410500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 2554 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 2554 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 172973 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 38701 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 74852 # Number of read requests accepted +system.mem_ctrls.writeReqs 41216 # Number of write requests accepted +system.mem_ctrls.readBursts 74852 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 41216 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 4674 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 4665 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 4710 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 4726 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 4740 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4803 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 4820 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 4712 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 4566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 4635 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 4584 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 4570 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 4719 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 4585 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 4706 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 4637 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 2595 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 2603 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 2624 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 2562 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 2634 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 2683 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 2682 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 2560 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 2499 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 2499 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2472 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 2469 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 2557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 2507 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 2661 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 2580 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 17.09 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 1781946000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 374260000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 3185421000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 23806.26 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 42556.26 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 63077 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 34486 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 84.27 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 83.67 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 74852 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 41216 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 23533 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 18550 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 17494 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 15264 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 84 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 532 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1427 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 1986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2588 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2900 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2596 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2585 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2581 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2643 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2590 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2603 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2738 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2796 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 5008 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2816 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 18465 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 402.082210 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 283.705525 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 301.849556 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3011 16.31% 16.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3435 18.60% 34.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3612 19.56% 54.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1735 9.40% 63.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1357 7.35% 71.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1709 9.26% 80.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1843 9.98% 90.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 201 1.09% 91.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1562 8.46% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 18465 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2554 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 29.302662 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.457594 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 634.033065 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 2553 99.96% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2554 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2554 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.126468 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.116603 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.601001 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2419 94.71% 94.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 34 1.33% 96.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 37 1.45% 97.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 53 2.08% 99.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.23% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.04% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.04% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 3 0.12% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2554 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 4790528 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2635968 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 4790528 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 2637824 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2014.21 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1108.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2014.21 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1109.09 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 24.39 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 15.74 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 8.66 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 2378355500 # Total gap between requests +system.mem_ctrls.avgGap 20491.05 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 55872 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 4734656 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 2635968 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 23491728.995795018971 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1990715486.116746425629 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1108309097.537009716034 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 873 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 73979 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 41216 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 24503500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 3160917500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 38198167750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28068.16 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 42727.23 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 926780.08 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 84.06 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 69143760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 36728010 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 264194280 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 105673680 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 187465200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 1035260220 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 41496000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 1739961150 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 731.577459 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 96474000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 79300000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 2202595000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 62774880 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 33346665 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 270249000 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 109322460 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 187465200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 974878410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 92343840 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 1730380455 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 727.549197 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 229260750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 79300000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states 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50442.748092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50442.748092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 259 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 11620500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11620500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.015470 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015470 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 43850.943396 # average ReadReq mshr miss latency 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number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3218954 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3218954 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 121 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 121 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.834711 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.834711 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31870.831683 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31870.831683 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 101 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 101 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3117954 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3117954 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.834711 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.834711 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30870.831683 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30870.831683 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 128 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 128 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.007812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.007812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007812 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007812 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 100 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 100 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 502.584179 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 548170 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 74921 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.316640 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 502.584179 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.981610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.981610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1343429 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1343429 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 2378369000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/bzip2/config.ini b/TAGE_SC_L_benchmarks/bzip2/config.ini new file mode 100644 index 000000000..0fbfb2528 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2/data/ref/input/input.source 1 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=input.source.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/bzip2/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/bzip2/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/bzip2/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/bzip2/config.json b/TAGE_SC_L_benchmarks/bzip2/config.json new file mode 100644 index 000000000..4ed9dfd38 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/bzip2/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/bzip2/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/bzip2/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + 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+cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/bzip2/fs/proc/stat b/TAGE_SC_L_benchmarks/bzip2/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/bzip2/input.source.out b/TAGE_SC_L_benchmarks/bzip2/input.source.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/bzip2/stats.txt b/TAGE_SC_L_benchmarks/bzip2/stats.txt new file mode 100644 index 000000000..a3b273d65 --- /dev/null +++ b/TAGE_SC_L_benchmarks/bzip2/stats.txt @@ -0,0 +1,1385 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 378669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 129920 # Simulator instruction rate (inst/s) +host_mem_usage 851152 # Number of bytes of host memory used +host_op_rate 136847 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.70 # Real time elapsed on the host +host_tick_rate 49195641 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1053339 # Number of ops (including micro ops) simulated +sim_seconds 0.000379 # Number of seconds simulated +sim_ticks 378669000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.503404 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115614 # Number of BTB hits +system.cpu.branchPred.BTBLookups 116191 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 2464 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 165497 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 7 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 226 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 219 # Number of indirect misses. +system.cpu.branchPred.lookups 215070 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95597 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 25234 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89459 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 31372 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 77 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 17 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1398 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3995 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1548 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2699 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 4225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 691 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1062 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1543 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1073 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1096 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1741 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2997 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1489 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 3809 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2871 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1179 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1383 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 91 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 510 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 72520 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 390 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1150 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 613 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3333 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 828 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5300 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1929 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4449 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 886 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1064 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 936 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 872 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1487 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1877 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1646 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 4123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 2434 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2290 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1615 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 44496 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 359 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1004 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1255 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 58 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 313770 # number of cc regfile reads +system.cpu.cc_regfile_writes 314274 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2236 # The number of times a branch was mispredicted +system.cpu.commit.branches 166034 # Number of branches committed +system.cpu.commit.bw_lim_events 89784 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 186372 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000753 # Number of instructions committed +system.cpu.commit.committedOps 1054092 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 689773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.528172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.731295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417532 60.53% 60.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116341 16.87% 77.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 28634 4.15% 81.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 17254 2.50% 84.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4031 0.58% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6864 1.00% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5326 0.77% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4007 0.58% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89784 13.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 689773 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 949 # Number of function calls committed. +system.cpu.commit.int_insts 932693 # Number of committed integer instructions. +system.cpu.commit.loads 381890 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 9 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 499972 47.43% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 23 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 29 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 34 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 36 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 26 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 381890 36.23% 83.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 172070 16.32% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1054092 # Class of committed instruction +system.cpu.commit.refs 553960 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 224 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1053339 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.757339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.757339 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 360461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 238 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 107076 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1267054 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 119405 # Number of cycles decode is idle +system.cpu.decode.RunCycles 192717 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3090 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 38933 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 215070 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157254 # Number of cache lines fetched +system.cpu.fetch.Cycles 542149 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1264248 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6636 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.283981 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 169064 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 116876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.669329 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 714606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.851436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.916258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 423481 59.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 93221 13.05% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14864 2.08% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3790 0.53% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24832 3.47% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40621 5.68% 84.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2761 0.39% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18559 2.60% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 92477 12.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 714606 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2409 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 196664 # Number of branches executed +system.cpu.iew.exec_nop 1021 # number of nop insts executed +system.cpu.iew.exec_rate 1.740594 # Inst execution rate +system.cpu.iew.exec_refs 722788 # number of memory reference insts executed +system.cpu.iew.exec_stores 202589 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 32308 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 426666 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 208592 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1244237 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 520199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1318220 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 23397 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3090 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 22831 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2201 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 114 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 72 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 57119 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 44776 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 36521 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 72 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1520 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 889 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1296071 # num instructions consuming a value +system.cpu.iew.wb_count 1190532 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.595900 # average fanout of values written-back +system.cpu.iew.wb_producers 772329 # num instructions producing a value +system.cpu.iew.wb_rate 1.571994 # insts written-back per cycle +system.cpu.iew.wb_sent 1216310 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1585569 # number of integer regfile reads +system.cpu.int_regfile_writes 864051 # number of integer regfile writes +system.cpu.ipc 1.320413 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.320413 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 596296 45.14% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 26 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 38 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 40 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 28 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 521557 39.48% 84.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 203026 15.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1321063 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 25708 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019460 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1956 7.61% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22214 86.41% 94.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1533 5.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1346476 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3382155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1190281 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1432674 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1243135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1321063 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 189873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 300 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 119405 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 714606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.848659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.064894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 293888 41.13% 41.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78022 10.92% 52.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 110896 15.52% 67.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 75702 10.59% 78.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 71454 10.00% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35453 4.96% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22686 3.17% 96.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17094 2.39% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9411 1.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 714606 # Number of insts issued each cycle +system.cpu.iq.rate 1.744348 # Inst issue rate +system.cpu.iq.vec_alu_accesses 285 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 585 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 251 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 478 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 106597 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65049 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 426666 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 208592 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1050401 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 757339 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 82529 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 994060 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 9884 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 138535 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 71021 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1546 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1838328 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1257405 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1218260 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 211199 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 176346 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3090 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 269320 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 224182 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1510334 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9933 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 206 # count of serializing insts renamed +system.cpu.rename.skidInsts 227667 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 486 # Number of vector rename lookups +system.cpu.rob.rob_reads 1830001 # The number of ROB reads +system.cpu.rob.rob_writes 2505786 # The number of ROB writes +system.cpu.timesIdled 374 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 333 # number of vector regfile reads +system.cpu.vec_regfile_writes 167 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1159 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6744 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4866 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 16 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10619 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 16 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2017 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1151 # Transaction distribution +system.membus.trans_dist::CleanEvict 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 3561 # Transaction distribution +system.membus.trans_dist::ReadExResp 3561 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2017 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 5585 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5585 # Request fanout histogram +system.membus.reqLayer0.occupancy 12181000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 28800250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2150 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4546 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 142 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1353 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 517 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1633 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 8 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 8 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1176 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15196 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16372 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 551872 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 594048 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1175 # Total snoops (count) +system.tol2bus.snoopTraffic 73664 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6928 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002454 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.049479 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6911 99.75% 99.75% # Request fanout histogram +system.tol2bus.snoop_fanout::1 17 0.25% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6928 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8846500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 7846000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 775500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 9 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 158 # number of demand (read+write) hits +system.l2.demand_hits::total 167 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 9 # number of overall hits +system.l2.overall_hits::.cpu.data 158 # number of overall hits +system.l2.overall_hits::total 167 # number of overall hits +system.l2.demand_misses::.cpu.inst 508 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5070 # number of demand (read+write) misses +system.l2.demand_misses::total 5578 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 508 # number of overall misses +system.l2.overall_misses::.cpu.data 5070 # number of overall misses +system.l2.overall_misses::total 5578 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40426500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 445531000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 485957500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40426500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 445531000 # number of overall miss cycles +system.l2.overall_miss_latency::total 485957500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 517 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5228 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5745 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 517 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5228 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5745 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.982592 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.969778 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.970931 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.982592 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.969778 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.970931 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.demand_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.overall_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1151 # number of writebacks +system.l2.writebacks::total 1151 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 508 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5070 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 5578 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 508 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5070 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 5578 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35346500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 394831000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 430177500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35346500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 394831000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 430177500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.970931 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.970931 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.replacements 1175 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 142 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 142 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 142 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 142 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 34 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 34 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3561 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3561 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3219.497523 # Cycle average of tags in use +system.l2.tags.total_refs 10611 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 5590 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.898211 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 7.025790 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 423.809713 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2788.662020 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000214 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.012934 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.085103 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.098251 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 4119 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.134705 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 90534 # Number of tag accesses +system.l2.tags.data_accesses 90534 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32512 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 324480 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 356992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 73664 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 73664 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 508 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5070 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 5578 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1151 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1151 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 85858626 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 856896128 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 942754754 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 194534013 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 85858626 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 856896128 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1137288767 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1151.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 508.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5070.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000326398500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 70 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 70 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 11431 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 1054 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 5578 # Number of read requests accepted +system.mem_ctrls.writeReqs 1151 # Number of write requests accepted +system.mem_ctrls.readBursts 5578 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1151 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 353 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 445 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 432 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 309 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 285 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 70 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 71 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 65 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 20.52 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 94535750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 27890000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 199123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16947.97 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 35697.97 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4807 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 945 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.18 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.10 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 5578 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1151 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1928 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1431 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1215 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 984 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 129 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 138 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 945 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 453.079365 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 384.495920 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 199.503629 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 8.25% 8.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 87 9.21% 17.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48 5.08% 22.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 4.02% 26.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 630 66.67% 93.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.95% 94.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 20 2.12% 96.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.21% 96.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 33 3.49% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 945 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 70 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 76.500000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 21.987624 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.513517 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 64 91.43% 91.43% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-255 1 1.43% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::256-383 4 5.71% 98.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2560-2687 1 1.43% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 70 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 70 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 70 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 70 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 356992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 71680 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 356992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 73664 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 942.75 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 189.29 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 942.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 194.53 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.84 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 7.37 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 378545500 # Total gap between requests +system.mem_ctrls.avgGap 56255.83 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 324480 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 71680 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 85858625.871143400669 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 856896128.280899643898 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 189294608.219843715429 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 508 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5070 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1151 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14431750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 184691500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 3158337250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28408.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 36428.30 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 2743994.14 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 85.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3127320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1658415 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 20149080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 2949300 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 165006450 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 6456480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 228849765 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 604.353050 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 15482250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 350706750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3627120 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1927860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 19677840 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 2897100 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 77622600 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 80042880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 215298120 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 568.565475 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 207448500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 158740500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 156559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 156559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 156559 # number of overall hits +system.cpu.icache.overall_hits::total 156559 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 694 # number of overall misses +system.cpu.icache.overall_misses::total 694 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 52763999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52763999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 52763999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52763999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 157253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 157253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 157253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 157253 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.004413 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004413 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.004413 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004413 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76028.817003 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76028.817003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76028.817003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76028.817003 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 506 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 142 # number of writebacks +system.cpu.icache.writebacks::total 142 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 177 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 517 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 517 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 517 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 517 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41303999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41303999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.003288 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003288 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.003288 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003288 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.replacements 142 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 156559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 156559 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 694 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 52763999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52763999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 157253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 157253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.004413 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004413 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76028.817003 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76028.817003 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 517 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 517 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 41303999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41303999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.003288 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003288 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79891.680851 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 345.595783 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 157076 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 517 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 303.822050 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 345.595783 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.674992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.674992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 375 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 315023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 315023 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 464703 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 464703 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 464720 # number of overall hits +system.cpu.dcache.overall_hits::total 464720 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 8891 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8891 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 8894 # number of overall misses +system.cpu.dcache.overall_misses::total 8894 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 664679305 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 664679305 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 664679305 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 664679305 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 473594 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 473594 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 473614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 473614 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.018773 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018773 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.018779 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018779 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 74758.666629 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74758.666629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 74733.450079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74733.450079 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188958 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 380 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2233 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.620690 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 3395 # number of writebacks +system.cpu.dcache.writebacks::total 3395 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3658 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3658 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3658 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3658 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 5233 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5233 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 86964.356010 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86964.356010 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 86976.026547 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86976.026547 # average overall mshr miss latency +system.cpu.dcache.replacements 4724 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 298404 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 298404 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3154 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3154 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 209001000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 209001000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 301558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 301558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.010459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 66265.377299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66265.377299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1631 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1631 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 123516000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 123516000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.005409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75730.226855 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.226855 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 166299 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166299 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 5730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5730 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 455455807 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 455455807 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 172029 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172029 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 79486.179232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.179232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3595 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3595 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 331352977 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 331352977 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 399.938493 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 89.770053 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 399.938493 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 174 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 952628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 952628 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 378669000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/cactusADM/benchADM.out b/TAGE_SC_L_benchmarks/cactusADM/benchADM.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/cactusADM/config.ini b/TAGE_SC_L_benchmarks/cactusADM/config.ini new file mode 100644 index 000000000..6cf8383e4 --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + 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+clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//data/ref/input/benchADM.par +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=benchADM.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/cactusADM/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/cactusADM/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/cactusADM/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/cactusADM/config.json b/TAGE_SC_L_benchmarks/cactusADM/config.json new file mode 100644 index 000000000..f4f2114e7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + 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+ "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/cactusADM/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/cactusADM/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/cactusADM/fs/proc/stat b/TAGE_SC_L_benchmarks/cactusADM/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/cactusADM/stats.txt b/TAGE_SC_L_benchmarks/cactusADM/stats.txt new file mode 100644 index 000000000..a16977a77 --- /dev/null +++ b/TAGE_SC_L_benchmarks/cactusADM/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 468934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 144656 # Simulator instruction rate (inst/s) +host_mem_usage 858000 # Number of bytes of host memory used +host_op_rate 161351 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.91 # Real time elapsed on the host +host_tick_rate 67832424 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1115434 # Number of ops (including micro ops) simulated +sim_seconds 0.000469 # Number of seconds simulated +sim_ticks 468934500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.262346 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 141471 # Number of BTB hits +system.cpu.branchPred.BTBLookups 145453 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 9391 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 220443 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3812 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 4741 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 929 # Number of indirect misses. +system.cpu.branchPred.lookups 302124 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95777 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 77037 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 92105 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80709 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 741 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 220 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 20202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1973 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 864 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1733 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3428 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1457 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 3210 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3917 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 4292 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 4162 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 2969 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1781 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 638 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1316 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 3060 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 386 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 314 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 142 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1900 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 617 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 883 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 108110 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2099 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3520 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4793 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1956 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1090 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4841 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 4720 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2582 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 3607 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 3667 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 4716 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4073 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1191 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 2928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 887 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4328 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 515 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 637 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 510 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 348 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 54309 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 445 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1757 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 30296 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 519 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 359643 # number of cc regfile reads +system.cpu.cc_regfile_writes 343424 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 8332 # The number of times a branch was mispredicted +system.cpu.commit.branches 231894 # Number of branches committed +system.cpu.commit.bw_lim_events 61305 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 150260 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001506 # Number of instructions committed +system.cpu.commit.committedOps 1116940 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 825652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.352798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.277638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 431090 52.21% 52.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 199057 24.11% 76.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 65640 7.95% 84.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25941 3.14% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18585 2.25% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7816 0.95% 90.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8606 1.04% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7612 0.92% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61305 7.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825652 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 22009 # Number of function calls committed. +system.cpu.commit.int_insts 1003889 # Number of committed integer instructions. +system.cpu.commit.loads 188126 # Number of loads committed +system.cpu.commit.membars 234 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 8 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 793381 71.03% 71.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 444 0.04% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 14 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 20 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 54 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 61 0.01% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 188126 16.84% 87.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 134785 12.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1116940 # Class of committed instruction +system.cpu.commit.refs 322911 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1515 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1115434 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.937870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.937870 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 351151 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1084 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131130 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1328223 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 235007 # Number of cycles decode is idle +system.cpu.decode.RunCycles 224796 # Number of cycles decode is running +system.cpu.decode.SquashCycles 8407 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4080 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 29047 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 302124 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 222644 # Number of cache lines fetched +system.cpu.fetch.Cycles 535575 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1285656 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18932 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.322138 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 303270 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 175579 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.370825 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 848408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.699079 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 525019 61.88% 61.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42918 5.06% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 73846 8.70% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28765 3.39% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26350 3.11% 82.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30088 3.55% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28164 3.32% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8804 1.04% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 84454 9.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 848408 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 89462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9865 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 251794 # Number of branches executed +system.cpu.iew.exec_nop 1869 # number of nop insts executed +system.cpu.iew.exec_rate 1.303190 # Inst execution rate +system.cpu.iew.exec_refs 355366 # number of memory reference insts executed +system.cpu.iew.exec_stores 146931 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 16550 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 213838 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 154189 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1267807 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 208435 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1222223 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 4213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8407 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4294 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2777 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 50 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 62 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25707 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 19402 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 62 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 6197 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3668 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1106565 # num instructions consuming a value +system.cpu.iew.wb_count 1213951 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.582876 # average fanout of values written-back +system.cpu.iew.wb_producers 644990 # num instructions producing a value +system.cpu.iew.wb_rate 1.294370 # insts written-back per cycle +system.cpu.iew.wb_sent 1218084 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1420776 # number of integer regfile reads +system.cpu.int_regfile_writes 874576 # number of integer regfile writes +system.cpu.ipc 1.066246 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.066246 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 871958 70.78% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480 0.04% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 14 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 58 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 18 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 68 0.01% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 210407 17.08% 87.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 148868 12.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1231948 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14526 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011791 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4852 33.40% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 33.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4991 34.36% 67.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4678 32.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1244743 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3323953 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1212381 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1414639 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1265632 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1231948 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150480 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 495 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 78863 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 848408 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 393727 46.41% 46.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150412 17.73% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 105051 12.38% 76.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72755 8.58% 85.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52873 6.23% 91.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32913 3.88% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 19751 2.33% 97.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8802 1.04% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12124 1.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 848408 # Number of insts issued each cycle +system.cpu.iq.rate 1.313559 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1722 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3369 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1570 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1837 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 5612 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9134 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 213838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 154189 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1000136 # number of misc regfile reads +system.cpu.misc_regfile_writes 957 # number of misc regfile writes +system.cpu.numCycles 937870 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 21506 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1121395 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 249451 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 444 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1970254 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1295032 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1298125 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239899 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5945 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 8407 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 30468 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 176678 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1507674 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 298677 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 18843 # count of serializing insts renamed +system.cpu.rename.skidInsts 135698 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 311 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1703 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031157 # The number of ROB reads +system.cpu.rob.rob_writes 2557380 # The number of ROB writes +system.cpu.timesIdled 2383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1549 # number of vector regfile reads +system.cpu.vec_regfile_writes 238 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2163 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4766 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10513 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1294 # Transaction distribution +system.membus.trans_dist::ReadExReq 793 # Transaction distribution +system.membus.trans_dist::ReadExResp 793 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1294 # Transaction distribution +system.membus.trans_dist::InvalidateReq 76 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2163 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2163 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2163 # Request fanout histogram +system.membus.reqLayer0.occupancy 2694500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 11077500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4801 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 781 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 3742 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 243 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 868 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 868 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 4213 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 588 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 78 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 78 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 12168 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4092 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16260 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 509120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 143168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 652288 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5747 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000174 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013191 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5746 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5747 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9779500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2223499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 6319500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 3199 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 383 # number of demand (read+write) hits +system.l2.demand_hits::total 3582 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 3199 # number of overall hits +system.l2.overall_hits::.cpu.data 383 # number of overall hits +system.l2.overall_hits::total 3582 # number of overall hits +system.l2.demand_misses::.cpu.inst 1014 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1073 # number of demand (read+write) misses +system.l2.demand_misses::total 2087 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1014 # number of overall misses +system.l2.overall_misses::.cpu.data 1073 # number of overall misses +system.l2.overall_misses::total 2087 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 79654500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 85698500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 165353000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 79654500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 85698500 # number of overall miss cycles +system.l2.overall_miss_latency::total 165353000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 4213 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1456 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5669 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 4213 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1456 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5669 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.240684 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.736951 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.368143 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.240684 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.736951 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.368143 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1014 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1073 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2087 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1014 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1073 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2087 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 69514500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 74968500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 144483000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 69514500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 74968500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 144483000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.368143 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.368143 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 781 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 781 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 3742 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 3742 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 3742 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 3742 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 75 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 75 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 793 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 793 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 76 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 76 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18907.894737 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18907.894737 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1545.070072 # Cycle average of tags in use +system.l2.tags.total_refs 10436 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2145 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 4.865268 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 34.455603 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 823.783092 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 686.831377 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001052 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.025140 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.020960 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047152 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1854 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.065399 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 86241 # Number of tag accesses +system.l2.tags.data_accesses 86241 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 64896 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 68672 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 133568 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1014 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1073 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2087 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 138390330 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 146442627 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 284832956 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 138390330 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 146442627 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 284832956 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1014.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1073.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4241 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2087 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2087 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 116 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 98 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 121 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 89 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 19480500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 10435000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 58611750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9334.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28084.21 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1636 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.39 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2087 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1462 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 439 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 295.537778 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 184.185643 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 301.373367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 148 32.89% 32.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 130 28.89% 61.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 47 10.44% 72.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 6.67% 78.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 20 4.44% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 16 3.56% 86.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 18 4.00% 90.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.11% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 36 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 133568 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 133568 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 284.83 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 284.83 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.23 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 468792000 # Total gap between requests +system.mem_ctrls.avgGap 224624.82 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 64896 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 68672 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 138390329.566282719374 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 146442626.848738998175 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1014 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1073 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 27791000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 30820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27407.30 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28723.90 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.39 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1570800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 834900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6418860 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 127052430 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 73079520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 245834910 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 524.241467 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 188810000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 264524500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1649340 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 872850 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 8482320 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 181366590 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 27341280 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 256590780 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 547.178295 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 69488250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 15600000 # Time in different power states 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accesses +system.cpu.icache.demand_miss_rate::total 0.021514 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.021514 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.021514 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 29480.166806 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29480.166806 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 29480.166806 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29480.166806 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 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latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28426.536910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 28426.536910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28426.536910 # average overall mshr miss latency +system.cpu.icache.replacements 3742 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 217852 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217852 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 4790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4790 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 141209999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 141209999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 222642 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.tags.occ_blocks::.cpu.inst 432.493594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.844714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.844714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 471 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.919922 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 449497 # Number of tag accesses +system.cpu.icache.tags.data_accesses 449497 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states 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+system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 61939.292876 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61939.292876 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 61973.957839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61973.957839 # average overall mshr miss latency +system.cpu.dcache.replacements 1024 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 202892 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 202892 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1153 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 57372500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57372500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 204045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 204045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.005651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 49759.323504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49759.323504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 26961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 47300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47300 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67858.667159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67858.667159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 65281995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65281995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.006623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 73268.232323 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73268.232323 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 518 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 518 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 520 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 520 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.003846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.003846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 27 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 27 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 55 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 55 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 454.875030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 336606 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 219.430248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 454.875030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 680902 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 680902 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 468934500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/calculix/beampic.log b/TAGE_SC_L_benchmarks/calculix/beampic.log new file mode 100644 index 000000000..f2915065d --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/beampic.log @@ -0,0 +1,2 @@ + *ERROR in openfile: input file /data/ref/input/hyperviscoplastic.inp.inp + does not exist diff --git a/TAGE_SC_L_benchmarks/calculix/config.ini b/TAGE_SC_L_benchmarks/calculix/config.ini new file mode 100644 index 000000000..476d6b22d --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] 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+opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross -i /data/ref/input/hyperviscoplastic.inp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=beampic.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/calculix/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/calculix/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/calculix/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/calculix/config.json b/TAGE_SC_L_benchmarks/calculix/config.json new file mode 100644 index 000000000..6be4f702d --- /dev/null +++ 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"cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/calculix/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/calculix/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/calculix/fs/proc/stat b/TAGE_SC_L_benchmarks/calculix/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/calculix/stats.txt b/TAGE_SC_L_benchmarks/calculix/stats.txt new file mode 100644 index 000000000..0fea89914 --- /dev/null +++ b/TAGE_SC_L_benchmarks/calculix/stats.txt @@ -0,0 +1,1359 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 56861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 71921 # Simulator instruction rate (inst/s) +host_mem_usage 856880 # Number of bytes of host memory used +host_op_rate 86905 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.33 # Real time elapsed on the host +host_tick_rate 173677852 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 23532 # Number of instructions simulated +sim_ops 28450 # Number of ops (including micro ops) simulated +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56861000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.498652 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 3688 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4821 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8019 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 34 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 465 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 431 # Number of indirect misses. +system.cpu.branchPred.lookups 11185 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2360 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 1810 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2273 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 1897 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 124 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 31 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 112 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 37 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 2916 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 558 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 93 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 66 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 347 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 15 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 859 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 8625 # number of cc regfile reads +system.cpu.cc_regfile_writes 8679 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 834 # The number of times a branch was mispredicted +system.cpu.commit.branches 5605 # Number of branches committed +system.cpu.commit.bw_lim_events 1239 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 54 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 23588 # Number of instructions committed +system.cpu.commit.committedOps 28506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 39891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.714597 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.779156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30973 77.64% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3276 8.21% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1731 4.34% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 879 2.20% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 598 1.50% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 551 1.38% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 436 1.09% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208 0.52% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1239 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39891 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 490 # Number of function calls committed. +system.cpu.commit.int_insts 25886 # Number of committed integer instructions. +system.cpu.commit.loads 4020 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 19666 68.99% 69.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.15% 69.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.01% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.09% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 26 0.09% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.10% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 30 0.11% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 4020 14.10% 83.66% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4658 16.34% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 28506 # Class of committed instruction +system.cpu.commit.refs 8678 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 413 # Number of committed Vector instructions. +system.cpu.committedInsts 23532 # Number of Instructions Simulated +system.cpu.committedOps 28450 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.832696 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.832696 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 13004 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 460 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3802 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 47302 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 19734 # Number of cycles decode is idle +system.cpu.decode.RunCycles 7777 # Number of cycles decode is running +system.cpu.decode.SquashCycles 869 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1546 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 710 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 11185 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6474 # Number of cache lines fetched +system.cpu.fetch.Cycles 17733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 47366 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2642 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.098353 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22801 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4581 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.416503 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 42094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.317646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 31882 75.74% 75.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1052 2.50% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1015 2.41% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 717 1.70% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1034 2.46% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 1.74% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1010 2.40% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 843 2.00% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3810 9.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 42094 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 71629 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 997 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 6864 # Number of branches executed +system.cpu.iew.exec_nop 122 # number of nop insts executed +system.cpu.iew.exec_rate 0.326908 # Inst execution rate +system.cpu.iew.exec_refs 11357 # number of memory reference insts executed +system.cpu.iew.exec_stores 5453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2304 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 6339 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 89 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6321 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 42090 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 5904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1114 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 37177 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 869 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1371 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 86 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1663 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 188 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 31510 # num instructions consuming a value +system.cpu.iew.wb_count 35773 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.563504 # average fanout of values written-back +system.cpu.iew.wb_producers 17756 # num instructions producing a value +system.cpu.iew.wb_rate 0.314563 # insts written-back per cycle +system.cpu.iew.wb_sent 36351 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 41177 # number of integer regfile reads +system.cpu.int_regfile_writes 25395 # number of integer regfile writes +system.cpu.ipc 0.206924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.206924 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 8 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 26234 68.51% 68.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.11% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.01% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 28 0.07% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.07% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 32 0.08% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.09% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 6191 16.17% 85.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5691 14.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 38291 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 555 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189 34.05% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.18% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.36% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 118 21.26% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 245 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 38309 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 118302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 35311 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 54736 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 41879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 38291 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13517 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 42094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.909655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29929 71.10% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2997 7.12% 78.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2546 6.05% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2071 4.92% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1657 3.94% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1133 2.69% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 951 2.26% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 490 1.16% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 320 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42094 # Number of insts issued each cycle +system.cpu.iq.rate 0.336704 # Inst issue rate +system.cpu.iq.vec_alu_accesses 529 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1074 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 462 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 769 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 6339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6321 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 28736 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 113723 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3701 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 26781 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 202 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 20563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 64176 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 44669 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 42396 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 7626 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 751 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 869 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1430 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15615 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 49589 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 7905 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 302 # count of serializing insts renamed +system.cpu.rename.skidInsts 3721 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 688 # Number of vector rename lookups +system.cpu.rob.rob_reads 80411 # The number of ROB reads +system.cpu.rob.rob_writes 86307 # The number of ROB writes +system.cpu.timesIdled 663 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 512 # number of vector regfile reads +system.cpu.vec_regfile_writes 137 # number of vector regfile writes +system.cpu.workload.numSyscalls 17 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1251 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 502 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1817 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1026 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution +system.membus.trans_dist::ReadExResp 168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1027 # Transaction distribution +system.membus.trans_dist::InvalidateReq 56 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1251 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1251 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1251 # Request fanout histogram +system.membus.reqLayer0.occupancy 1533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 6321500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1089 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 27 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 440 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 33 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 171 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 171 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 925 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 165 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 56 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 56 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2289 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 844 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3133 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 87296 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 23232 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 110528 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001519 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.038954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1315 99.85% 99.85% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.15% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1375500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 532000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1386000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 42 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 66 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 42 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 66 # number of overall hits +system.l2.demand_misses::.cpu.inst 883 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 312 # number of demand (read+write) misses +system.l2.demand_misses::total 1195 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 883 # number of overall misses +system.l2.overall_misses::.cpu.data 312 # number of overall misses +system.l2.overall_misses::total 1195 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 68520500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 25782500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 94303000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 68520500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 25782500 # number of overall miss cycles +system.l2.overall_miss_latency::total 94303000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 925 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 336 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1261 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 925 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 336 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1261 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.954595 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.928571 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.947661 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.954595 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.928571 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.947661 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 883 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 312 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1195 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 883 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 312 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1195 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 59700500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 22662500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 82363000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 59700500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 22662500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 82363000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.947661 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.947661 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 27 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 27 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 440 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 440 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 440 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 440 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 168 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 168 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 56 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 56 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19000 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19000 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 638.816237 # Cycle average of tags in use +system.l2.tags.total_refs 1760 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1196 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.471572 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 0.787737 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 434.030626 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 203.997874 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000024 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013246 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006226 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.019495 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1196 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1019 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.036499 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 15732 # Number of tag accesses +system.l2.tags.data_accesses 15732 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56448 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 19968 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 76416 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 882 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 312 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1194 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 992736674 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 351172157 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1343908830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 992736674 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 351172157 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1343908830 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 883.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 312.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000542000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2358 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1195 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1195 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 126 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 91 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.77 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10859000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 5975000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 33265250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9087.03 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27837.03 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 963 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.59 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1195 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 132 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 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activation +system.mem_ctrls.bytesPerActivate::256-383 32 14.22% 67.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 7.56% 74.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 4.44% 79.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 15 6.67% 85.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.67% 88.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 3.56% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 18 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 225 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 76480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 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read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 19968 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 993862225.426918268204 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 351172156.662738919258 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 883 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 312 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23476250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 9789000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26586.92 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31375.00 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 849660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4448220 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 24871380 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 890400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 35806155 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 629.713776 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 2123000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 52918000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 806820 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 4076940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) 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different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 55029500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 5295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 5295 # number of overall hits +system.cpu.icache.overall_hits::total 5295 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1177 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1177 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1177 # number of 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accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.181860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.181860 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1005 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 440 # number of writebacks +system.cpu.icache.writebacks::total 440 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 252 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 252 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 925 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 925 # number of overall MSHR misses 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overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 76075.131892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76075.131892 # average overall mshr miss latency +system.cpu.icache.replacements 440 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 6472 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6472 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.tags.occ_percent::.cpu.inst 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13868 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13868 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states 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+system.cpu.dcache.overall_miss_rate::.cpu.data 0.129371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129371 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 65539.884025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65539.884025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 65339.149311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65339.149311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3235 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.010204 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 27 # number of writebacks +system.cpu.dcache.writebacks::total 27 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 915 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 915 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 915 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 915 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 391 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 391 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 27768467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27768467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 28171467 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28171467 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71753.144703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71753.144703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72049.787724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72049.787724 # average overall mshr miss latency +system.cpu.dcache.replacements 60 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26851000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26851000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 5439 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 5439 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.072991 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.072991 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 67634.760705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67634.760705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 223.007274 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 9264 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.632653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 223.007274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 332 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.648438 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 20752 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 20752 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 56861000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/gobmk/capture.out b/TAGE_SC_L_benchmarks/gobmk/capture.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/gobmk/config.ini b/TAGE_SC_L_benchmarks/gobmk/config.ini new file mode 100644 index 000000000..ae09d1c0f --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] 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+children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross --quiet --mode gtp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//data/ref/input/13x13.tst +kvmInSE=false +maxStackSize=67108864 +output=capture.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false 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+[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 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+clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/gobmk/config.json b/TAGE_SC_L_benchmarks/gobmk/config.json new file mode 100644 index 000000000..df028138e --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 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"system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/gobmk/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/gobmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/gobmk/fs/proc/stat b/TAGE_SC_L_benchmarks/gobmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/gobmk/stats.txt b/TAGE_SC_L_benchmarks/gobmk/stats.txt new file mode 100644 index 000000000..e8ff53e1e --- /dev/null +++ b/TAGE_SC_L_benchmarks/gobmk/stats.txt @@ -0,0 +1,1342 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 463966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 146000 # Simulator instruction rate (inst/s) +host_mem_usage 859124 # Number of bytes of host memory used +host_op_rate 146544 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.85 # Real time elapsed on the host +host_tick_rate 67737000 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1003756 # Number of ops (including micro ops) simulated +sim_seconds 0.000464 # Number of seconds simulated +sim_ticks 463966500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.726161 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 173713 # Number of BTB hits +system.cpu.branchPred.BTBLookups 174190 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 844 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 175218 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 134 # Number of indirect misses. +system.cpu.branchPred.lookups 183670 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 9619 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 154197 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 4842 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 158974 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 65 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 763 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 46 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 40 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 275 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 136 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 60 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 145 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 215 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 206 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 108 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 36 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 61 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 62 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 79 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 269 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 10 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 159067 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 285 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 40 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 64 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 301 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 52 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 248 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 125 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 68 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 212 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 183 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 270 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 165 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 329 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 82 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 95 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 3403 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 40 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 100 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2727 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 507132 # number of cc regfile reads +system.cpu.cc_regfile_writes 507438 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 649 # The number of times a branch was mispredicted +system.cpu.commit.branches 171144 # Number of branches committed +system.cpu.commit.bw_lim_events 19230 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 40539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000213 # Number of instructions committed +system.cpu.commit.committedOps 1003967 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 891530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.126117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.219871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 650701 72.99% 72.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 52797 5.92% 78.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32204 3.61% 82.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21703 2.43% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7692 0.86% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7047 0.79% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99282 11.14% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 874 0.10% 97.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19230 2.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 891530 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2417 # Number of function calls committed. +system.cpu.commit.int_insts 840106 # Number of committed integer instructions. +system.cpu.commit.loads 310680 # Number of loads committed +system.cpu.commit.membars 16 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 533766 53.17% 53.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 449 0.04% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 310680 30.95% 84.16% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 159002 15.84% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1003967 # Class of committed instruction +system.cpu.commit.refs 469682 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 248 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1003756 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927932 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927932 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 713461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 170925 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1055068 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 40149 # Number of cycles decode is idle +system.cpu.decode.RunCycles 102411 # Number of cycles decode is running +system.cpu.decode.SquashCycles 990 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 670 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 40070 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 183670 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15255 # Number of cache lines fetched +system.cpu.fetch.Cycles 872161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1072586 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.197934 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 23707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 176441 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.155886 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 897081 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.201933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.336465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692458 77.19% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4126 0.46% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23115 2.58% 80.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1334 0.15% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25122 2.80% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 897 0.10% 83.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139169 15.51% 98.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2994 0.33% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7866 0.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 897081 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 30853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 729 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 177146 # Number of branches executed +system.cpu.iew.exec_nop 257 # number of nop insts executed +system.cpu.iew.exec_rate 1.156592 # Inst execution rate +system.cpu.iew.exec_refs 519344 # number of memory reference insts executed +system.cpu.iew.exec_stores 164447 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 5056 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 321924 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 164988 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1044518 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 354897 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1073241 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 17069 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 990 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 17094 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8383 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11235 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5981 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 446 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1269546 # num instructions consuming a value +system.cpu.iew.wb_count 1033965 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.530245 # average fanout of values written-back +system.cpu.iew.wb_producers 673170 # num instructions producing a value +system.cpu.iew.wb_rate 1.114266 # insts written-back per cycle +system.cpu.iew.wb_sent 1039294 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1392509 # number of integer regfile reads +system.cpu.int_regfile_writes 700174 # number of integer regfile writes +system.cpu.ipc 1.077665 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077665 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 553864 51.57% 51.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 501 0.05% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 25 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 355062 33.06% 84.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 164583 15.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1074097 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 18272 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017011 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 123 0.67% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18071 98.90% 99.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 75 0.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1092056 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3062983 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1033689 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1084351 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1044228 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1074097 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 40478 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 23290 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 897081 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.197324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 639583 71.30% 71.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 33403 3.72% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24407 2.72% 77.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 35269 3.93% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 51684 5.76% 87.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56013 6.24% 93.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5377 0.60% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43750 4.88% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7595 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 897081 # Number of insts issued each cycle +system.cpu.iq.rate 1.157514 # Inst issue rate +system.cpu.iq.vec_alu_accesses 308 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 619 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 276 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 424 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2492 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2394 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 321924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 164988 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 865847 # number of misc regfile reads +system.cpu.misc_regfile_writes 65 # number of misc regfile writes +system.cpu.numCycles 927934 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23218 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1166751 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3317 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 60184 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 8163 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1892164 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1047728 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1217345 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 122048 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 674293 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 990 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 686442 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 50538 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1368066 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4199 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.skidInsts 219619 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 409 # Number of vector rename lookups +system.cpu.rob.rob_reads 1912854 # The number of ROB reads +system.cpu.rob.rob_writes 2094604 # The number of ROB writes +system.cpu.timesIdled 311 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 318 # number of vector regfile reads +system.cpu.vec_regfile_writes 92 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 22125 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 21334 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 43517 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 464 # Transaction distribution +system.membus.trans_dist::ReadExReq 18836 # Transaction distribution +system.membus.trans_dist::ReadExResp 18835 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 464 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 22125 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 22125 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 22125 # Request fanout histogram +system.membus.reqLayer0.occupancy 31087500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 98420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 504 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 21206 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 51 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 77 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 18854 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 18851 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 385 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 119 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2825 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 821 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 64876 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 65697 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 2571264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2599168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 22183 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000045 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.006714 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 22182 100.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 22183 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 43015500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 9.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 29867500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 577500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 8 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 48 # number of demand (read+write) hits +system.l2.demand_hits::total 56 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 8 # number of overall hits +system.l2.overall_hits::.cpu.data 48 # number of overall hits +system.l2.overall_hits::total 56 # number of overall hits +system.l2.demand_misses::.cpu.inst 377 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 18925 # number of demand (read+write) misses +system.l2.demand_misses::total 19302 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 377 # number of overall misses +system.l2.overall_misses::.cpu.data 18925 # number of overall misses +system.l2.overall_misses::total 19302 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 30084500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1436692500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1466777000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 30084500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1436692500 # number of overall miss cycles +system.l2.overall_miss_latency::total 1466777000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 385 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 18973 # number of demand (read+write) accesses +system.l2.demand_accesses::total 19358 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 385 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 18973 # number of overall (read+write) accesses +system.l2.overall_accesses::total 19358 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.979221 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.997470 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.997107 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.979221 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.997470 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.997107 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 377 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 18925 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 19302 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 377 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 18925 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 19302 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 26314500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1247472500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1273787000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 26314500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1247472500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1273787000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.997107 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.997107 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 51 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 51 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 51 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 51 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 16 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 16 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 18838 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 18838 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19206.725664 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19206.725664 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 11222.269262 # Cycle average of tags in use +system.l2.tags.total_refs 40688 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 22124 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.839089 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 2583.087120 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 362.014998 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 8277.167144 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.078830 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.011048 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.252599 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.342476 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 22124 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 472 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4203 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 17449 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.675171 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 370252 # Number of tag accesses +system.l2.tags.data_accesses 370252 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 24128 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1211008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1235136 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 377 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 18922 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 19299 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 52003755 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2610119481 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2662123235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 52003755 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2610119481 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2662123235 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 377.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 18923.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000585000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 38666 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 19300 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 19300 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1250 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1163 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1166 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1206 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1234 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.19 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 115628000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 96500000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 477503000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5991.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24741.09 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 17926 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 19300 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5032 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 4929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 5539 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 3792 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming 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write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1373 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 899.589221 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 780.016617 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 290.557773 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 61 4.44% 4.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 55 4.01% 8.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44 3.20% 11.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 0.66% 12.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 33 2.40% 14.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 0.44% 15.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 25 1.82% 16.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 0.44% 17.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1134 82.59% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1235200 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1235200 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2662.26 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2662.26 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 20.80 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 20.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 463952000 # Total gap between requests +system.mem_ctrls.avgGap 24038.96 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 24128 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1211072 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 52003754.581419132650 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2610257421.602637290955 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 377 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 18923 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 10808750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 466694250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28670.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24662.80 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 92.88 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 5069400 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2690655 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 70093380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 117849210 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 78922080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 310888485 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 670.066664 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 200539250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 248087250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 4740960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 2519880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 67701480 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 110516730 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 85096800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 306839610 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 661.340011 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 216684000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 231942500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 14752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 14752 # number of overall hits +system.cpu.icache.overall_hits::total 14752 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 503 # number of overall misses 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+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 51 # number of writebacks +system.cpu.icache.writebacks::total 51 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 118 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 385 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 385 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 385 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 385 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 30755499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30755499 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 322.204782 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15137 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 385 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39.316883 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 322.204782 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.629306 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.629306 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30895 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 326918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 326918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 326923 # number of overall hits +system.cpu.dcache.overall_hits::total 326923 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 152895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 152895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 152897 # number of overall misses +system.cpu.dcache.overall_misses::total 152897 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 9649773141 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9649773141 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 9649773141 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9649773141 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 479813 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 479813 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 479820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 479820 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.318655 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.318655 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.318655 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.318655 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 63113.726028 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63113.726028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 63112.900456 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63112.900456 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 622929 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8721 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.428621 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 21206 # number of writebacks +system.cpu.dcache.writebacks::total 21206 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 131099 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 131099 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 131099 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 131099 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 21796 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 21796 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 21798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 21798 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 1557818510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1557818510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 1558017510 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1558017510 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.045426 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.045426 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.045430 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.045430 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71472.678932 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71472.678932 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 71475.250482 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71475.250482 # average overall mshr miss latency +system.cpu.dcache.replacements 21283 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 149730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 149730 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 9539526625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9539526625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 156163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.958806 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.958806 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 492.463211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 21795 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.001468 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 492.463211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 981503 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 981503 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 463966500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/h264ref/config.ini b/TAGE_SC_L_benchmarks/h264ref/config.ini new file mode 100644 index 000000000..2f1093b10 --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + 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+clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run/h264ref_base.amd64-armcross -d /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg +cwd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run/h264ref_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=foreman_ref_encoder_baseline.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 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"profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/h264ref/foreman_ref_encoder_baseline.out b/TAGE_SC_L_benchmarks/h264ref/foreman_ref_encoder_baseline.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/h264ref/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/h264ref/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/h264ref/fs/proc/stat b/TAGE_SC_L_benchmarks/h264ref/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/h264ref/stats.txt b/TAGE_SC_L_benchmarks/h264ref/stats.txt new file mode 100644 index 000000000..ac00f9bc0 --- /dev/null +++ b/TAGE_SC_L_benchmarks/h264ref/stats.txt @@ -0,0 +1,1366 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 427446500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 162479 # Simulator instruction rate (inst/s) +host_mem_usage 854744 # Number of bytes of host memory used +host_op_rate 185570 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.15 # Real time elapsed on the host +host_tick_rate 69449032 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1142145 # Number of ops (including micro ops) simulated +sim_seconds 0.000427 # Number of seconds simulated +sim_ticks 427446500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.575075 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 121359 # Number of BTB hits +system.cpu.branchPred.BTBLookups 124375 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4313 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 198147 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 655 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1283 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 628 # Number of indirect misses. +system.cpu.branchPred.lookups 250887 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 125414 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 53109 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 101135 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 77388 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 271 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 59 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 13501 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2840 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3207 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1792 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2768 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 748 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 2375 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 3991 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 7442 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1519 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 2239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 914 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 2020 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1730 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1065 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1307 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1097 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1285 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1233 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1910 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1197 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 167 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 370 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 120104 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 828 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 553 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3993 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8056 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 4579 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 824 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3601 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3076 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1884 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2406 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7039 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 2146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1665 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 2144 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 951 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1108 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1599 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1503 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1304 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1331 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 2041 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 54083 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 181 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1074 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 13605 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 379872 # number of cc regfile reads +system.cpu.cc_regfile_writes 372672 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3271 # The number of times a branch was mispredicted +system.cpu.commit.branches 224913 # Number of branches committed +system.cpu.commit.bw_lim_events 50758 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 252 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 56194 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1003095 # Number of instructions committed +system.cpu.commit.committedOps 1145240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 770738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.485901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.369664 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 426603 55.35% 55.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116834 15.16% 70.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 67596 8.77% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 39515 5.13% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22580 2.93% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13536 1.76% 89.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22607 2.93% 92.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10709 1.39% 93.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50758 6.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770738 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 12624 # Number of function calls committed. +system.cpu.commit.int_insts 1024481 # Number of committed integer instructions. +system.cpu.commit.loads 150860 # Number of loads committed +system.cpu.commit.membars 232 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 6 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 863752 75.42% 75.42% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5029 0.44% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 5 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 9 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 9 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 376 0.03% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 22 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 22 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 24 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 245 0.02% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 150860 13.17% 89.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 124880 10.90% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1145240 # Class of committed instruction +system.cpu.commit.refs 275740 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 8879 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1142145 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.854894 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.854894 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 368509 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1137 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 119986 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1224547 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 178045 # Number of cycles decode is idle +system.cpu.decode.RunCycles 216792 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3386 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3609 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 12829 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 250887 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 171510 # Number of cache lines fetched +system.cpu.fetch.Cycles 561356 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1099130 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 489 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 9018 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.293471 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 212929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 135619 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.285692 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 779561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.607915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.731971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 528636 67.81% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27113 3.48% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36295 4.66% 75.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 12254 1.57% 77.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30279 3.88% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 37573 4.82% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11082 1.42% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29102 3.73% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 67227 8.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 779561 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 75333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3610 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 232462 # Number of branches executed +system.cpu.iew.exec_nop 3256 # number of nop insts executed +system.cpu.iew.exec_rate 1.385596 # Inst execution rate +system.cpu.iew.exec_refs 290276 # number of memory reference insts executed +system.cpu.iew.exec_stores 128324 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 16400 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 159345 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 373 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 825 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 130179 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1202599 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 161952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5071 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1184538 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 11293 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3386 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11568 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 6347 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1197 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 8480 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5299 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1314 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1108752 # num instructions consuming a value +system.cpu.iew.wb_count 1175456 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.594385 # average fanout of values written-back +system.cpu.iew.wb_producers 659026 # num instructions producing a value +system.cpu.iew.wb_rate 1.374973 # insts written-back per cycle +system.cpu.iew.wb_sent 1177494 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1320787 # number of integer regfile reads +system.cpu.int_regfile_writes 841620 # number of integer regfile writes +system.cpu.ipc 1.169736 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169736 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 87 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 891253 74.92% 74.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5132 0.43% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 15 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 9 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 505 0.04% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 280 0.02% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163357 13.73% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 128886 10.83% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1189612 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14157 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5654 39.94% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1451 10.25% 50.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7049 49.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1192014 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3151220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1165962 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1244261 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1198970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1189612 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 373 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 57189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 671 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 43243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 779561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.526002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.034822 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 391506 50.22% 50.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101942 13.08% 63.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 84279 10.81% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59290 7.61% 81.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54793 7.03% 88.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35615 4.57% 93.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31539 4.05% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10015 1.28% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10582 1.36% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 779561 # Number of insts issued each cycle +system.cpu.iq.rate 1.391532 # Inst issue rate +system.cpu.iq.vec_alu_accesses 11668 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 22390 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 9494 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 12293 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 3440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3163 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 159345 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 130179 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 800526 # number of misc regfile reads +system.cpu.misc_regfile_writes 1323 # number of misc regfile writes +system.cpu.numCycles 854894 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 28940 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1176670 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1971 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 184460 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2889 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1821783 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1215369 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1258811 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 222802 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 53928 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3386 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 65271 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 82118 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1347675 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 274702 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5780 # count of serializing insts renamed +system.cpu.rename.skidInsts 55715 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 370 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 9913 # Number of vector rename lookups +system.cpu.rob.rob_reads 1920192 # The number of ROB reads +system.cpu.rob.rob_writes 2411737 # The number of ROB writes +system.cpu.timesIdled 1270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 8786 # number of vector regfile reads +system.cpu.vec_regfile_writes 924 # number of vector regfile writes +system.cpu.workload.numSyscalls 19 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6119 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 7306 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 15623 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1472 # Transaction distribution +system.membus.trans_dist::ReadExReq 2056 # Transaction distribution +system.membus.trans_dist::ReadExResp 2056 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1472 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2591 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 9647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9647 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 225792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 225792 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 6119 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6119 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6119 # Request fanout histogram +system.membus.reqLayer0.occupancy 7296500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 18591250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3350 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4967 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1538 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 801 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2132 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2131 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2036 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1314 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2835 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2835 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 5610 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 18329 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 23939 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 228736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 538368 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 767104 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 8317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000120 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.010965 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 8316 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 8317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 14316500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 6585499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3054499 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1095 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 858 # number of demand (read+write) hits +system.l2.demand_hits::total 1953 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1095 # number of overall hits +system.l2.overall_hits::.cpu.data 858 # number of overall hits +system.l2.overall_hits::total 1953 # number of overall hits +system.l2.demand_misses::.cpu.inst 941 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2588 # number of demand (read+write) misses +system.l2.demand_misses::total 3529 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 941 # number of overall misses +system.l2.overall_misses::.cpu.data 2588 # number of overall misses +system.l2.overall_misses::total 3529 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 73969000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 198318000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 272287000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 73969000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 198318000 # number of overall miss cycles +system.l2.overall_miss_latency::total 272287000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2036 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 3446 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5482 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2036 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 3446 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5482 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.462181 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.751016 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.643743 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.462181 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.751016 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.643743 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78606.801275 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 76629.829985 # average overall miss latency +system.l2.demand_avg_miss_latency::total 77156.984982 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78606.801275 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 76629.829985 # average overall miss latency +system.l2.overall_avg_miss_latency::total 77156.984982 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 941 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2588 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3529 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 941 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2588 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3529 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 64559000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 172447501 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 237006501 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 64559000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 172447501 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 237006501 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.751016 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.643743 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.751016 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.643743 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 66633.501159 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 67159.677246 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 66633.501159 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 67159.677246 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 4967 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 4967 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 4967 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 4967 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1538 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1538 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1538 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1538 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 75 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 75 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 2057 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2057 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 155434500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 155434500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2132 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2132 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.964822 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.964822 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75563.684978 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75563.684978 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2057 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2057 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 134874001 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 134874001 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.964822 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.964822 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65568.303841 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65568.303841 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1095 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1095 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 941 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 941 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 73969000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 73969000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2036 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2036 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.462181 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.462181 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78606.801275 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78606.801275 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 941 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 941 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 64559000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 64559000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.462181 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68606.801275 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 783 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 783 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 42883500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 42883500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1314 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1314 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.404110 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.404110 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80759.887006 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80759.887006 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37573500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37573500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.404110 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.404110 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70759.887006 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70759.887006 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 244 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 244 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 2591 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2591 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2835 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2835 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.913933 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.913933 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2591 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2591 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 49882500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 49882500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.913933 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.913933 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19252.219220 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19252.219220 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3445.376602 # Cycle average of tags in use +system.l2.tags.total_refs 13030 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 6363 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.047776 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1510.581900 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 802.458021 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1132.336680 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.046099 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.024489 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.034556 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.105145 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 6119 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 612 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 5439 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.186737 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 131339 # Number of tag accesses +system.l2.tags.data_accesses 131339 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 60224 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 165568 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 225792 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 60224 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 60224 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 941 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2587 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 3528 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 140892486 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 387342042 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 528234528 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 140892486 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 140892486 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 140892486 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 387342042 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 528234528 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 941.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2587.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000580000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 7098 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3528 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 3528 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 235 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 318 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 169 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 236 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 284 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 142 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 146 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 259 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 208 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 252 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 25715500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 17640000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 91865500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 7288.97 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26038.97 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 3062 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.79 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3528 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2460 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 714 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 245 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 91 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 465 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 483.509677 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 291.844159 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 400.792061 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 117 25.16% 25.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 72 15.48% 40.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 57 12.26% 52.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 25 5.38% 58.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 3.87% 62.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 18 3.87% 66.02% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 14 3.01% 69.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 1.51% 70.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 137 29.46% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 465 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 225792 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 225792 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 528.23 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 528.23 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.13 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 427332000 # Total gap between requests +system.mem_ctrls.avgGap 121125.85 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 60224 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 165568 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 140892485.960231274366 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 387342041.635619878769 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 941 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2587 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 25845750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 66019750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27466.26 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 25519.81 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.79 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1449420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 770385 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 12109440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 126533160 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 57585600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 231638565 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 541.912415 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 148059250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 265347250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1877820 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 994290 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 13080480 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 81271740 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 95700480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 226115370 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 528.991043 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 247772000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 165634500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 169215 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 169215 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 169215 # number of overall hits +system.cpu.icache.overall_hits::total 169215 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2293 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2293 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2293 # number of overall misses +system.cpu.icache.overall_misses::total 2293 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 104755998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 104755998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 104755998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 104755998 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 171508 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 171508 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 171508 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 171508 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.013370 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013370 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.013370 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013370 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 45685.127780 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45685.127780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 45685.127780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45685.127780 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1607 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.958333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1538 # number of writebacks +system.cpu.icache.writebacks::total 1538 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 257 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 257 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 257 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 257 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2036 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2036 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2036 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2036 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88649498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88649498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88649498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88649498 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.011871 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.011871 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.011871 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.011871 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 43541.010806 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43541.010806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 43541.010806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43541.010806 # average overall mshr miss latency +system.cpu.icache.replacements 1538 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 169215 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 169215 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2293 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2293 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 104755998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 104755998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 171508 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 171508 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.013370 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013370 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 45685.127780 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45685.127780 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 257 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 2036 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2036 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 88649498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 88649498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.011871 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.011871 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 43541.010806 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43541.010806 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 465.809207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 171251 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2036 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 84.111493 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 465.809207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.909784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 498 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.972656 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 345052 # Number of tag accesses +system.cpu.icache.tags.data_accesses 345052 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 257906 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 257906 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 257925 # number of overall hits +system.cpu.dcache.overall_hits::total 257925 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 17545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 17547 # number of overall misses +system.cpu.dcache.overall_misses::total 17547 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 954383136 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 954383136 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 954383136 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 954383136 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 275451 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 275451 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 275472 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 275472 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.063696 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.063696 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.063698 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.063698 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 54396.302992 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54396.302992 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 54390.102924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54390.102924 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 55929 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2942 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.010537 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 4967 # number of writebacks +system.cpu.dcache.writebacks::total 4967 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 11268 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 11268 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 11268 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 11268 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6277 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6277 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 6279 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 6279 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 297627965 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297627965 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 297812965 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297812965 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.022788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.022788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.022794 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.022794 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 47415.638840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47415.638840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 47429.999204 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47429.999204 # average overall mshr miss latency +system.cpu.dcache.replacements 5768 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 147681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147681 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3117 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 129376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 129376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 150798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 150798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.020670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 41506.737247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.737247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1311 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1311 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 52921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.008694 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008694 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 40367.276888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40367.276888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 110145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 110145 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 11747 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11747 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 741676646 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 741676646 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 121892 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 121892 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.096372 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.096372 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63137.536903 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63137.536903 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 9462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 2285 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2285 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 164057475 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 164057475 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 71797.582057 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71797.582057 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 19 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 19 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 21 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 21 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.095238 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.095238 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.095238 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.095238 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 80 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 80 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2681 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2681 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 83329990 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 83329990 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2761 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2761 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.971025 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.971025 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31081.682208 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31081.682208 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2681 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2681 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 80648990 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 80648990 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.971025 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.971025 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30081.682208 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30081.682208 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 200000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 200000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 244 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 244 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 50000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 50000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.008197 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008197 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 478.577533 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 264677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6280 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 42.146019 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 478.577533 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.934722 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.934722 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 558176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 558176 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 427446500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/hmmer/bombesin.out b/TAGE_SC_L_benchmarks/hmmer/bombesin.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/hmmer/config.ini b/TAGE_SC_L_benchmarks/hmmer/config.ini new file mode 100644 index 000000000..c3c5b1874 --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 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"ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/hmmer/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/hmmer/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/hmmer/fs/proc/stat b/TAGE_SC_L_benchmarks/hmmer/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/hmmer/stats.txt b/TAGE_SC_L_benchmarks/hmmer/stats.txt new file mode 100644 index 000000000..1cbccac05 --- /dev/null +++ b/TAGE_SC_L_benchmarks/hmmer/stats.txt @@ -0,0 +1,1345 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 371151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 131229 # Simulator instruction rate (inst/s) +host_mem_usage 855668 # Number of bytes of host memory used +host_op_rate 167322 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.62 # Real time elapsed on the host +host_tick_rate 48704426 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1275067 # Number of ops (including micro ops) simulated +sim_seconds 0.000371 # Number of seconds simulated +sim_ticks 371151000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.606810 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 134690 # Number of BTB hits +system.cpu.branchPred.BTBLookups 136593 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7055 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 204306 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 469 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1143 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 674 # Number of indirect misses. +system.cpu.branchPred.lookups 261150 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95555 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 56119 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89830 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61844 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 277 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 66 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 11001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2901 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 666 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 346 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 6942 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1667 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1558 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 892 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1613 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 838 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1380 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2365 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1862 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1343 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2169 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 355 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1232 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 102898 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1036 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1952 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 472 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 6800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 7412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1147 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1856 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1332 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1037 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1444 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1142 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1280 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1072 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1398 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1571 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1970 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1994 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2018 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 3065 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39731 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 649 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 2829 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 19178 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 172 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 299295 # number of cc regfile reads +system.cpu.cc_regfile_writes 276253 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6404 # The number of times a branch was mispredicted +system.cpu.commit.branches 199789 # Number of branches committed +system.cpu.commit.bw_lim_events 86134 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 405 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 214441 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002214 # Number of instructions committed +system.cpu.commit.committedOps 1277279 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 626626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038343 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.814350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301756 48.16% 48.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 90275 14.41% 62.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51837 8.27% 70.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 43017 6.86% 77.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25180 4.02% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 11065 1.77% 83.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 12372 1.97% 85.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4990 0.80% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 86134 13.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 626626 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 15547 # Number of function calls committed. +system.cpu.commit.int_insts 1131445 # Number of committed integer instructions. +system.cpu.commit.loads 187072 # Number of loads committed +system.cpu.commit.membars 384 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 861 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756222 59.21% 59.27% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7535 0.59% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 23 0.00% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2196 0.17% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 10982 0.86% 60.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 10950 0.86% 61.75% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 15330 1.20% 62.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 2212 0.17% 63.13% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 16014 1.25% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1597 0.13% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 2100 0.16% 64.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 2000 0.16% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 3853 0.30% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 187072 14.65% 79.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 258328 20.22% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1277279 # Class of committed instruction +system.cpu.commit.refs 445400 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 96081 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1275067 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.742302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.742302 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 239022 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 662 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131096 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1597574 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 141803 # Number of cycles decode is idle +system.cpu.decode.RunCycles 249035 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6496 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2505 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 20755 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 261150 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157977 # Number of cache lines fetched +system.cpu.fetch.Cycles 467292 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2017 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1344580 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14294 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.351811 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 182557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 154337 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.811363 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 657111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.521428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.140176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 348325 53.01% 53.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23632 3.60% 56.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27656 4.21% 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30837 4.69% 65.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 31384 4.78% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30870 4.70% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 47784 7.27% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14171 2.16% 84.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102452 15.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 657111 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 85192 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 11895 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 212923 # Number of branches executed +system.cpu.iew.exec_nop 2687 # number of nop insts executed +system.cpu.iew.exec_rate 1.861834 # Inst execution rate +system.cpu.iew.exec_refs 480552 # number of memory reference insts executed +system.cpu.iew.exec_stores 266534 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 30022 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 229901 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 453 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 644 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 292791 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1492153 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 214018 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1382045 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 127 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 240 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6496 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 396 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 297 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 83 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 42824 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 34431 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2505 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 9390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1186513 # num instructions consuming a value +system.cpu.iew.wb_count 1367463 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.568161 # average fanout of values written-back +system.cpu.iew.wb_producers 674131 # num instructions producing a value +system.cpu.iew.wb_rate 1.842190 # insts written-back per cycle +system.cpu.iew.wb_sent 1374742 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1621778 # number of integer regfile reads +system.cpu.int_regfile_writes 838864 # number of integer regfile writes +system.cpu.ipc 1.347161 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.347161 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 998 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829308 59.28% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7609 0.54% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 28 0.00% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2197 0.16% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 4 0.00% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 10983 0.79% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 10950 0.78% 61.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 15330 1.10% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 2212 0.16% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 16097 1.15% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1811 0.13% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 2359 0.17% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2282 0.16% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 4283 0.31% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 219731 15.71% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 272755 19.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1398937 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 43962 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031425 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7219 16.42% 16.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 13 0.03% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 2190 4.98% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 52 0.12% 21.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 62 0.14% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7316 16.64% 38.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 27110 61.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1342253 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3302227 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1269728 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1600011 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1489013 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1398937 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 453 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 214328 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 193555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 657111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.128920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.441391 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278120 42.32% 42.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 72738 11.07% 53.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 50307 7.66% 61.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 80997 12.33% 73.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 55228 8.40% 81.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 38544 5.87% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28076 4.27% 91.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 24302 3.70% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28799 4.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 657111 # Number of insts issued each cycle +system.cpu.iq.rate 1.884590 # Inst issue rate +system.cpu.iq.vec_alu_accesses 99648 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 198960 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 97735 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 103851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1873 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21229 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 229901 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 292791 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1127954 # number of misc regfile reads +system.cpu.misc_regfile_writes 45403 # number of misc regfile writes +system.cpu.numCycles 742303 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 31082 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1164220 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 541 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 153081 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2573258 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1560444 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1380122 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 256102 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 146174 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6496 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 153264 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 215859 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1883723 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 57086 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3503 # count of serializing insts renamed +system.cpu.rename.skidInsts 60035 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 123940 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031718 # The number of ROB reads +system.cpu.rob.rob_writes 3014020 # The number of ROB writes +system.cpu.timesIdled 847 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 120536 # number of vector regfile reads +system.cpu.vec_regfile_writes 92784 # number of vector regfile writes +system.cpu.workload.numSyscalls 20 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1880 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1721 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4415 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1411 # Transaction distribution +system.membus.trans_dist::ReadExReq 456 # Transaction distribution +system.membus.trans_dist::ReadExResp 456 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1411 # Transaction distribution +system.membus.trans_dist::InvalidateReq 13 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1880 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1880 # Request fanout histogram +system.membus.reqLayer0.occupancy 2346500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 9886750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2054 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 580 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 821 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 320 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 467 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 467 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1313 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 741 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 173 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 173 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3447 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 3662 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 136576 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 114432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 251008 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2694 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000371 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.019266 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2693 99.96% 99.96% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.04% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2694 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 3608500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1898999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1969999 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 245 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 409 # number of demand (read+write) hits +system.l2.demand_hits::total 654 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 245 # number of overall hits +system.l2.overall_hits::.cpu.data 409 # number of overall hits +system.l2.overall_hits::total 654 # number of overall hits +system.l2.demand_misses::.cpu.inst 1068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 799 # number of demand (read+write) misses +system.l2.demand_misses::total 1867 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1068 # number of overall misses +system.l2.overall_misses::.cpu.data 799 # number of overall misses +system.l2.overall_misses::total 1867 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 83627500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 64742000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 148369500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 83627500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 64742000 # number of overall miss cycles +system.l2.overall_miss_latency::total 148369500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1313 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1208 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2521 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1313 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1208 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2521 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.813404 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.661424 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.740579 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.813404 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.661424 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.740579 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 799 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1867 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 799 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1867 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 72947500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 56752000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 129699500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 72947500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 56752000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 129699500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.740579 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.740579 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 580 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 580 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 820 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 820 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 820 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 820 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 11 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 11 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 456 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 456 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1313 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1313 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.813404 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.813404 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 160 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 160 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 13 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 13 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18961.538462 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18961.538462 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1571.392330 # Cycle average of tags in use +system.l2.tags.total_refs 4401 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2036 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.161591 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.498537 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 965.191752 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 599.702041 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000198 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.029455 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.018301 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047955 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1876 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.057251 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 37348 # Number of tag accesses +system.l2.tags.data_accesses 37348 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 68352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 119488 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 799 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1867 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 184162241 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 137776808 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 321939049 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 184162241 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 137776808 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 321939049 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 799.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000577500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3767 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1867 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1867 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 37 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 28 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 177 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 180 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 17820750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 9335000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 52827000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9545.13 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28295.13 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1446 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 77.45 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1867 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1121 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 532 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length 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write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 420 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 284.190476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 185.885137 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 276.585457 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 132 31.43% 31.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 114 27.14% 58.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 62 14.76% 73.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 33 7.86% 81.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 26 6.19% 87.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 3.33% 90.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 0.95% 91.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 1.90% 93.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 27 6.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 420 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 119488 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 119488 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 321.94 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 321.94 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.52 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 369996500 # Total gap between requests +system.mem_ctrls.avgGap 198177.02 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 68352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51136 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 184162241.244129747152 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 137776807.822153240442 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 799 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 28999750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 23827250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27153.32 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 29821.34 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1692180 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 895620 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6525960 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 151671300 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14798880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 204472020 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 550.913294 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 37200500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 321730500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1313760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 698280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6804420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 90643680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 66190560 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 194538780 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 524.149955 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 171329000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 187602000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 156317 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 156317 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 156317 # number of overall hits +system.cpu.icache.overall_hits::total 156317 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1660 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1660 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1660 # number of overall misses +system.cpu.icache.overall_misses::total 1660 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 108308496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108308496 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 157977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 157977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 157977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 157977 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.010508 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.010508 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.010508 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.010508 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65246.081928 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65246.081928 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65246.081928 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65246.081928 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 922 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.086957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 821 # number of writebacks +system.cpu.icache.writebacks::total 821 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 347 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 347 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 347 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88219497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88219497 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.replacements 821 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 156317 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 156317 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1660 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1660 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 108308496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108308496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 157977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 157977 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.010508 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.010508 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 65246.081928 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65246.081928 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 347 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 88219497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 88219497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008311 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67189.258949 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 461.614751 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 157630 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1313 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 120.053313 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 461.614751 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 492 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.960938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 317267 # Number of tag accesses +system.cpu.icache.tags.data_accesses 317267 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 468504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 468504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 468777 # number of overall hits +system.cpu.dcache.overall_hits::total 468777 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 4699 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4699 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 4709 # number of overall misses +system.cpu.dcache.overall_misses::total 4709 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 212942364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212942364 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 473203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 473203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 473486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 473486 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.009930 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009930 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.009945 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009945 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 45316.527772 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45316.527772 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 45220.293905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45220.293905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7524 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.258824 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 580 # number of writebacks +system.cpu.dcache.writebacks::total 580 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3323 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 1376 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 1381 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1381 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 72791495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 72791495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 73193495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 73193495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.002908 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002908 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.002917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002917 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 52900.795785 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52900.795785 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 53000.358436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000.358436 # average overall mshr miss latency +system.cpu.dcache.replacements 900 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 397.840327 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470952 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1381 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 341.022448 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 397.840327 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 481 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.939453 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 949941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 949941 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 371151000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/lbm/config.ini b/TAGE_SC_L_benchmarks/lbm/config.ini new file mode 100644 index 000000000..a1d3029c6 --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector 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+eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross 20 reference.dat 0 1 /home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//data/ref/input/100_100_130_ldc.of +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lbm.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/lbm/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/lbm/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/lbm/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/lbm/config.json b/TAGE_SC_L_benchmarks/lbm/config.json new file mode 100644 index 000000000..c8d147201 --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/config.json @@ -0,0 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"snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/lbm/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/lbm/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/lbm/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": 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"addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/lbm/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/lbm/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/lbm/fs/proc/stat b/TAGE_SC_L_benchmarks/lbm/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/lbm/lbm.out b/TAGE_SC_L_benchmarks/lbm/lbm.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/lbm/stats.txt b/TAGE_SC_L_benchmarks/lbm/stats.txt new file mode 100644 index 000000000..6efd69344 --- /dev/null +++ b/TAGE_SC_L_benchmarks/lbm/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 4902307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 36955 # Simulator instruction rate (inst/s) +host_mem_usage 855112 # Number of bytes of host memory used +host_op_rate 84038 # Simulator op (including micro ops) rate (op/s) +host_seconds 27.06 # Real time elapsed on the host +host_tick_rate 181161749 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 2274104 # Number of ops (including micro ops) simulated +sim_seconds 0.004902 # Number of seconds simulated +sim_ticks 4902307500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.321334 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 80345 # Number of BTB hits +system.cpu.branchPred.BTBLookups 80894 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 681 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 82458 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 184 # Number of indirect misses. +system.cpu.branchPred.lookups 83857 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 1019 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 71229 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 885 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71363 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 7 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 16 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 13 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 71818 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 11 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 6 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 6 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 3 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 382 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 224787 # number of cc regfile reads +system.cpu.cc_regfile_writes 224753 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 458 # The number of times a branch was mispredicted +system.cpu.commit.branches 72859 # Number of branches committed +system.cpu.commit.bw_lim_events 3268 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 25 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 117033 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000020 # Number of instructions committed +system.cpu.commit.committedOps 2274123 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 9747057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.233314 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.924085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8920827 91.52% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 211342 2.17% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 263671 2.71% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 192727 1.98% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 887 0.01% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26860 0.28% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99059 1.02% 99.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28416 0.29% 99.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3268 0.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9747057 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 212 # Number of function calls committed. +system.cpu.commit.int_insts 2202108 # Number of committed integer instructions. +system.cpu.commit.loads 1635 # Number of loads committed +system.cpu.commit.membars 14 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 18 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 856639 37.67% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 35 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 2 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 5 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 50 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 75 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 72 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 50 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1635 0.07% 37.75% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1415539 62.25% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2274123 # Class of committed instruction +system.cpu.commit.refs 1417174 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1343403 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 2274104 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 9.804606 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.804606 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 9350428 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 226 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 77569 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2473522 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 94627 # Number of cycles decode is idle +system.cpu.decode.RunCycles 91391 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3247 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 222392 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 83857 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 165626 # Number of cache lines fetched +system.cpu.fetch.Cycles 9580362 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 474 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1144257 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6940 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.008553 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 178206 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 80767 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.116706 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.265638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.361026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9355453 95.83% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 462 0.00% 95.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 81714 0.84% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 306 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 404 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 356 0.00% 96.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 80930 0.83% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 288 0.00% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 242172 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 536 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 76341 # Number of branches executed +system.cpu.iew.exec_nop 39 # number of nop insts executed +system.cpu.iew.exec_rate 0.247066 # Inst execution rate +system.cpu.iew.exec_refs 1509552 # number of memory reference insts executed +system.cpu.iew.exec_stores 1507002 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 12538 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2762 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1507465 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2424933 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2550 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 596 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2422384 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3565955 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3563309 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 138537 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 25 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1127 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 91926 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 431 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1315617 # num instructions consuming a value +system.cpu.iew.wb_count 2385368 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.470059 # average fanout of values written-back +system.cpu.iew.wb_producers 618418 # num instructions producing a value +system.cpu.iew.wb_rate 0.243290 # insts written-back per cycle +system.cpu.iew.wb_sent 2422037 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2500193 # number of integer regfile reads +system.cpu.int_regfile_writes 838779 # number of integer regfile writes +system.cpu.ipc 0.101993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.101993 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 912819 37.67% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 2 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 61 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 92 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 84 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2674 0.11% 37.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1507117 62.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2422980 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014892 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98 0.27% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.01% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 50 0.14% 0.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35929 99.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 994108 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 11750159 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 987126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1060881 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2424861 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2422980 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 138838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 9762085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.248203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.908083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8884365 91.01% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186986 1.92% 92.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 293038 3.00% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119100 1.22% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 160453 1.64% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73781 0.76% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 32145 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8705 0.09% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3512 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 9762085 # Number of insts issued each cycle +system.cpu.iq.rate 0.247126 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1464935 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2894045 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1398242 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1514819 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2762 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1507465 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 4684140 # number of misc regfile reads +system.cpu.misc_regfile_writes 60 # number of misc regfile writes +system.cpu.numCycles 9804616 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3576234 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1001630 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 196981 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 7051196 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2436342 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1070903 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 210854 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5679127 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3247 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5771799 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 69269 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2514763 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 102 # count of serializing insts renamed +system.cpu.rename.skidInsts 1791068 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1436706 # Number of vector rename lookups +system.cpu.rob.rob_reads 12098844 # The number of ROB reads +system.cpu.rob.rob_writes 4797353 # The number of ROB writes +system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1429226 # number of vector regfile reads +system.cpu.vec_regfile_writes 352 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 144291 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 321752 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 176581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 354068 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 391 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144072 # Transaction distribution +system.membus.trans_dist::CleanEvict 219 # Transaction distribution +system.membus.trans_dist::ReadExReq 173888 # Transaction distribution +system.membus.trans_dist::ReadExResp 173887 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 177461 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 177461 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 177461 # Request fanout histogram +system.membus.reqLayer0.occupancy 936460000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 19.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 907473250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 656 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 320411 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 151 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 701 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 173890 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 173887 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 542 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2941 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 530317 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 531552 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 44352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 22421760 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 22466112 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 144682 # Total snoops (count) +system.tol2bus.snoopTraffic 9220608 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 322169 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001217 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.034861 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 321777 99.88% 99.88% # Request fanout histogram +system.tol2bus.snoop_fanout::1 392 0.12% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 322169 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 353524000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.2 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 262472000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 813000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 23 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 24 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 23 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 24 # number of overall hits +system.l2.demand_misses::.cpu.inst 519 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 174003 # number of demand (read+write) misses +system.l2.demand_misses::total 174522 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 519 # number of overall misses +system.l2.overall_misses::.cpu.data 174003 # number of overall misses +system.l2.overall_misses::total 174522 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40762500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 17963265500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 18004028000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40762500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 17963265500 # number of overall miss cycles +system.l2.overall_miss_latency::total 18004028000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 542 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 174004 # number of demand (read+write) accesses +system.l2.demand_accesses::total 174546 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 542 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 174004 # number of overall (read+write) accesses +system.l2.overall_accesses::total 174546 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.957565 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999994 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.999863 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.957565 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999994 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.999863 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.demand_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.overall_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 144072 # number of writebacks +system.l2.writebacks::total 144072 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 174003 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 174522 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 174003 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 174522 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35572500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 16223265500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 16258838000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35572500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 16223265500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 16258838000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.999863 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.999863 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.replacements 144682 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 151 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 151 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 151 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 151 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 173890 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 173890 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18824.209453 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18824.209453 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 30365.095360 # Cycle average of tags in use +system.l2.tags.total_refs 351123 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 177450 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.978715 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 496.663908 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 68.643613 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 29799.787838 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.015157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.002095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.909417 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.926669 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 3120 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 29304 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 3009986 # Number of tag accesses +system.l2.tags.data_accesses 3009986 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 11136064 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11169280 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 9220608 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9220608 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 174001 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 174520 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 144072 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 144072 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 6775585 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2271596386 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2278371971 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1880870998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 6775585 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2271596386 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4159242969 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 144072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 174001.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000010576500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 9000 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 9000 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 438695 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 135333 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 174520 # Number of read requests accepted +system.mem_ctrls.writeReqs 144072 # Number of write requests accepted +system.mem_ctrls.readBursts 174520 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 144072 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 10869 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10878 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10850 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 10895 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 10938 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10907 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10846 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10863 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10898 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 11015 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10962 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10944 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 8964 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9014 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9013 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8966 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8980 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9024 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9067 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8960 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 23.69 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 5679206250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 872600000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 8951456250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 32541.86 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 51291.86 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 161227 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 132655 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.08 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 174520 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 144072 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 47549 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 46137 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 50896 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29930 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 365 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2640 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 8814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9125 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9139 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9752 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9591 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 10159 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 9576 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 10617 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13932 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14020 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 10969 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 10027 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 9450 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 171 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 24680 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 826.069368 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 676.795020 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 328.058619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1587 6.43% 6.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1443 5.85% 12.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 890 3.61% 15.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 501 2.03% 17.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 902 3.65% 21.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 405 1.64% 23.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1154 4.68% 27.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3458 14.01% 41.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 14340 58.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 24680 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 9000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.390222 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.723502 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 342.009805 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8999 99.99% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 9000 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 9000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.005111 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.004843 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.096479 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 8971 99.68% 99.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.16% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 13 0.14% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 0.02% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 9000 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 11169280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9218944 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11169280 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9220608 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2278.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1880.53 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2278.37 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1880.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 32.49 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 17.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.69 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 4902290500 # Total gap between requests +system.mem_ctrls.avgGap 15387.36 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 11136064 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 9218944 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 6775584.762889721431 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2271596385.987619400024 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1880531566.002336740494 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 174001 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 144072 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14227250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8937229000 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 108442678250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27412.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 51363.09 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 752697.81 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.24 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 88129020 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 46826505 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 624564360 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 377035380 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 1662343440 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 482617920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 3668125185 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 748.244614 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 1206855250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 3531912250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 88114740 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 46834095 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 621508440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 374884740 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 1648007370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 494690400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 3660648345 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 746.719447 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1234393250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 3504374250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 164918 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 164918 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 164918 # number of overall hits +system.cpu.icache.overall_hits::total 164918 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 708 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 708 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 708 # number of overall misses +system.cpu.icache.overall_misses::total 708 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 52243997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52243997 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 165626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 165626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 165626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 165626 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.004275 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004275 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.004275 # 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cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 509.260955 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 393134 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 176942 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 2.221824 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 509.260955 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3012882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3012882 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 4902307500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/leslie3d/config.ini b/TAGE_SC_L_benchmarks/leslie3d/config.ini new file mode 100644 index 000000000..adcec07c0 --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 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+opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//data/ref/input/leslie3d.in +kvmInSE=false +maxStackSize=67108864 +output=leslie3d.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/leslie3d/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/leslie3d/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/leslie3d/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/leslie3d/config.json b/TAGE_SC_L_benchmarks/leslie3d/config.json new file mode 100644 index 000000000..c7b060e78 --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/leslie3d/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/leslie3d/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/leslie3d/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": 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0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/leslie3d/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/leslie3d/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/leslie3d/fs/proc/stat b/TAGE_SC_L_benchmarks/leslie3d/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/leslie3d/leslie3d.stdout b/TAGE_SC_L_benchmarks/leslie3d/leslie3d.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/leslie3d/stats.txt b/TAGE_SC_L_benchmarks/leslie3d/stats.txt new file mode 100644 index 000000000..841a69336 --- /dev/null +++ b/TAGE_SC_L_benchmarks/leslie3d/stats.txt @@ -0,0 +1,1375 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 633191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 139236 # Simulator instruction rate (inst/s) +host_mem_usage 858128 # Number of bytes of host memory used +host_op_rate 143016 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.18 # Real time elapsed on the host +host_tick_rate 88161056 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1027168 # Number of ops (including micro ops) simulated +sim_seconds 0.000633 # Number of seconds simulated +sim_ticks 633191500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.331508 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 271326 # Number of BTB hits +system.cpu.branchPred.BTBLookups 273152 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4136 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 288777 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1729 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2702 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 973 # Number of indirect misses. +system.cpu.branchPred.lookups 303846 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 220585 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 15411 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14913 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 221083 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 71 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6676 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4222 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 97 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 176 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 7184 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 8627 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 175 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 149 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 14793 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 24269 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 123 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1754 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 31282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 50224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 45 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2133 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 12495 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 863 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 2717 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 4338 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 548 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 435 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 273 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 33753 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 811 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 5603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4512 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5240 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 7180 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 681 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2024 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 6802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 14803 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 126 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 24296 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 31283 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 31 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 50204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 14495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 315 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 830 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 7160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 176080 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 124 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1242 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 5816 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 229 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 741872 # number of cc regfile reads +system.cpu.cc_regfile_writes 745941 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3517 # The number of times a branch was mispredicted +system.cpu.commit.branches 247012 # Number of branches committed +system.cpu.commit.bw_lim_events 10828 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 105898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002022 # Number of instructions committed +system.cpu.commit.committedOps 1029189 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1184416 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.868942 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.633643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 852717 71.99% 71.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 86958 7.34% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26662 2.25% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38740 3.27% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 162261 13.70% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2540 0.21% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1651 0.14% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2059 0.17% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10828 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1184416 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 4620 # Number of function calls committed. +system.cpu.commit.int_insts 800492 # Number of committed integer instructions. +system.cpu.commit.loads 35378 # Number of loads committed +system.cpu.commit.membars 138 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 3 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756594 73.51% 73.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 384 0.04% 73.55% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 94 0.01% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 15 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 10 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 12 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 72 0.01% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 35378 3.44% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 236587 22.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1029189 # Class of committed instruction +system.cpu.commit.refs 271965 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2101 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1027168 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.266383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.266383 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 939021 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 633 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 256856 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1193254 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 81548 # Number of cycles decode is idle +system.cpu.decode.RunCycles 122138 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4010 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2198 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 52729 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 303846 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 33096 # Number of cache lines fetched +system.cpu.fetch.Cycles 1134130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1231249 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9258 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239932 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 60555 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 278871 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.972256 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.054599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.921750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 900384 75.07% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5040 0.42% 75.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4823 0.40% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6304 0.53% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 251564 20.97% 97.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5198 0.43% 97.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2375 0.20% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5224 0.44% 98.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18534 1.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 66938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4018 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 266820 # Number of branches executed +system.cpu.iew.exec_nop 3248 # number of nop insts executed +system.cpu.iew.exec_rate 0.883459 # Inst execution rate +system.cpu.iew.exec_refs 295165 # number of memory reference insts executed +system.cpu.iew.exec_stores 254519 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 11776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 41845 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 258911 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1147285 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40646 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1118798 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 5041 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4010 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5055 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 16436 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2895 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 6467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 22322 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1721 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1445197 # num instructions consuming a value +system.cpu.iew.wb_count 1105084 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.389950 # average fanout of values written-back +system.cpu.iew.wb_producers 563554 # num instructions producing a value +system.cpu.iew.wb_rate 0.872629 # insts written-back per cycle +system.cpu.iew.wb_sent 1116457 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1374875 # number of integer regfile reads +system.cpu.int_regfile_writes 605717 # number of integer regfile writes +system.cpu.ipc 0.789651 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.789651 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 827002 73.50% 73.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385 0.03% 73.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 96 0.01% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 43 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 21 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 14 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 79 0.01% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41481 3.69% 77.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 256057 22.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1125209 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3779 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003358 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1189 31.46% 31.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.03% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.03% 31.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.05% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1706 45.14% 76.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 880 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1126587 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3449247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1102914 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1258414 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1143825 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1125209 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 212 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 116860 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 269 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 67635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1199446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.938107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.588111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 834403 69.57% 69.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 57645 4.81% 74.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59296 4.94% 79.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 79441 6.62% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 149085 12.43% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9168 0.76% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6069 0.51% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2657 0.22% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1682 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1199446 # Number of insts issued each cycle +system.cpu.iq.rate 0.888521 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2397 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 4664 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2170 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2523 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1322 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 41845 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258911 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 837113 # number of misc regfile reads +system.cpu.misc_regfile_writes 561 # number of misc regfile writes +system.cpu.numCycles 1266384 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 17199 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1240714 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 76 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 110111 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1532 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2211765 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1167418 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1407025 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 145021 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 898782 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4010 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 902303 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 166281 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1427211 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20802 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 866 # count of serializing insts renamed +system.cpu.rename.skidInsts 403798 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 212 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 2276 # Number of vector rename lookups +system.cpu.rob.rob_reads 2302630 # The number of ROB reads +system.cpu.rob.rob_writes 2285280 # The number of ROB writes +system.cpu.timesIdled 955 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2115 # number of vector regfile reads +system.cpu.vec_regfile_writes 186 # number of vector regfile writes +system.cpu.workload.numSyscalls 35 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 27415 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 27242 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 55462 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 1 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 981 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1 # Transaction distribution +system.membus.trans_dist::CleanEvict 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 26347 # Transaction distribution +system.membus.trans_dist::ReadExResp 26347 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 981 # Transaction distribution +system.membus.trans_dist::InvalidateReq 81 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 27409 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 27409 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 27409 # Request fanout histogram +system.membus.reqLayer0.occupancy 38625500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 142095500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1786 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 26011 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1033 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 205 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 26353 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 26350 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1496 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 290 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 81 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 81 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4025 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 79654 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 83679 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 161856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 3369600 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 3531456 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 7 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 28227 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000177 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013308 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 28222 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 5 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 28227 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 54774000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 8.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 40000500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2244000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 663 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 147 # number of demand (read+write) hits +system.l2.demand_hits::total 810 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 663 # number of overall hits +system.l2.overall_hits::.cpu.data 147 # number of overall hits +system.l2.overall_hits::total 810 # number of overall hits +system.l2.demand_misses::.cpu.inst 833 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 26496 # number of demand (read+write) misses +system.l2.demand_misses::total 27329 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 833 # number of overall misses +system.l2.overall_misses::.cpu.data 26496 # number of overall misses +system.l2.overall_misses::total 27329 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 65230000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1988340500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 2053570500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 65230000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1988340500 # number of overall miss cycles +system.l2.overall_miss_latency::total 2053570500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1496 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 26643 # number of demand (read+write) accesses +system.l2.demand_accesses::total 28139 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1496 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 26643 # number of overall (read+write) accesses +system.l2.overall_accesses::total 28139 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.556818 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.994483 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.971214 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.556818 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.994483 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.971214 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1 # number of writebacks +system.l2.writebacks::total 1 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 833 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 26496 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 27329 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 833 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 26496 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 27329 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 56900000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1723390500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1780290500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 56900000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1723390500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1780290500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.971214 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.971214 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.replacements 7 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1031 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1031 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1031 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1031 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 5 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 5 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 26348 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 26348 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 81 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 81 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18827.160494 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18827.160494 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 12249.229006 # Cycle average of tags in use +system.l2.tags.total_refs 55376 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 27409 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.020358 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 68.558691 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 789.028674 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 11391.641641 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.002092 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.024079 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.347645 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.373817 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 27402 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4388 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 22522 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.836243 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 471073 # Number of tag accesses +system.l2.tags.data_accesses 471073 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 53312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1695680 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1748992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 64 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 64 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 833 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 26495 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 27328 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 84195698 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2677989202 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2762184900 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 101075 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 84195698 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2677989202 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2762285975 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 833.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 26495.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 54769 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 27328 # Number of read requests accepted +system.mem_ctrls.writeReqs 1 # Number of write requests accepted +system.mem_ctrls.readBursts 27328 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1772 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1704 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1666 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1604 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1597 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1622 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1620 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1697 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1766 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1832 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1740 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1725 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1755 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1692 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.76 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.09 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 140438500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 136640000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 652838500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5139.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 23889.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 25352 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.77 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 27328 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7425 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7778 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 9212 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 2906 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 885.495441 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 752.763476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.372978 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 104 5.27% 5.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 85 4.31% 9.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 66 3.34% 12.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23 1.17% 14.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 46 2.33% 16.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.46% 16.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 33 1.67% 18.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 11 0.56% 19.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1597 80.90% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1748992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1748992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 64 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2762.18 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2762.18 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 21.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 633124500 # Total gap between requests +system.mem_ctrls.avgGap 23166.76 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 53312 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1695680 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 84195697.510152921081 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2677989202.318729877472 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 833 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 26495 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 22622500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 630216000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27157.86 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 23786.22 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 0.00 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.77 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 7339920 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 3901260 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 99817200 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 177114390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 93996960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 431955570 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 682.187885 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 236432000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 21060000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 375699500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6768720 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3590070 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 95304720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 172093830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 98224800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 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WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 26376 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 8 # number of SoftPFReq misses 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rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.477586 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 89018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 26721 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.331387 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.477586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 573017 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 573017 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 633191500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/libquantum/config.ini b/TAGE_SC_L_benchmarks/libquantum/config.ini new file mode 100644 index 000000000..8c0098a32 --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + 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system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 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+ +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/libquantum/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/libquantum/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/libquantum/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/libquantum/config.json b/TAGE_SC_L_benchmarks/libquantum/config.json new file mode 100644 index 000000000..a1fdbd563 --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/libquantum/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + 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100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/libquantum/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/libquantum/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/libquantum/fs/proc/stat b/TAGE_SC_L_benchmarks/libquantum/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/libquantum/ref.out b/TAGE_SC_L_benchmarks/libquantum/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/libquantum/stats.txt b/TAGE_SC_L_benchmarks/libquantum/stats.txt new file mode 100644 index 000000000..dd609ba80 --- /dev/null +++ b/TAGE_SC_L_benchmarks/libquantum/stats.txt @@ -0,0 +1,1358 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 156283000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 194201 # Simulator instruction rate (inst/s) +host_mem_usage 850920 # Number of bytes of host memory used +host_op_rate 198028 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.15 # Real time elapsed on the host +host_tick_rate 30349266 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1019736 # Number of ops (including micro ops) simulated +sim_seconds 0.000156 # Number of seconds simulated +sim_ticks 156283000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.556468 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118292 # Number of BTB hits +system.cpu.branchPred.BTBLookups 118819 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 917 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 143507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 16 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 223 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 207 # Number of indirect misses. +system.cpu.branchPred.lookups 158035 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 35991 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 103468 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 35878 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 103581 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 86 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 9243 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 52 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 212 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 113 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8355 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 456 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 907 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 78 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 16839 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1144 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 605 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 26857 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 23350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 909 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 356 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 51 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 45800 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 413 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 76 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 373 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 74 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 29 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 8684 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 127 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 968 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 16840 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1250 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 688 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1102 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 27054 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 873 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1098 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 24756 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 92619 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 85 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 629 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 55 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 369735 # number of cc regfile reads +system.cpu.cc_regfile_writes 385833 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 671 # The number of times a branch was mispredicted +system.cpu.commit.branches 152825 # Number of branches committed +system.cpu.commit.bw_lim_events 48481 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 56 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14700 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000086 # Number of instructions committed +system.cpu.commit.committedOps 1019822 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 267479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.812718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.461220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92809 34.70% 34.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 26484 9.90% 44.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9629 3.60% 48.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 5117 1.91% 50.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2873 1.07% 51.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4221 1.58% 52.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6771 2.53% 55.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71094 26.58% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 48481 18.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267479 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 374 # Number of function calls committed. +system.cpu.commit.int_insts 810700 # Number of committed integer instructions. +system.cpu.commit.loads 256050 # Number of loads committed +system.cpu.commit.membars 48 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 10 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 571430 56.03% 56.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6238 0.61% 56.64% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.00% 56.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 4094 0.40% 57.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 15846 1.55% 58.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 6163 0.60% 59.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 21987 2.16% 61.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21987 2.16% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 22 0.00% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 2070 0.20% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 32 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 37 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 40 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2082 0.20% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 256050 25.11% 89.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 111727 10.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1019822 # Class of committed instruction +system.cpu.commit.refs 367777 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 110708 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1019736 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.312568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.312568 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 69648 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 118068 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1040742 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 47684 # Number of cycles decode is idle +system.cpu.decode.RunCycles 140140 # Number of cycles decode is running +system.cpu.decode.SquashCycles 713 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 839 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 11559 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 158035 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 42789 # Number of cache lines fetched +system.cpu.fetch.Cycles 215002 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 516 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1025109 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1918 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.505602 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 53749 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 118937 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.279635 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 269744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.883860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.387563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102170 37.88% 37.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9565 3.55% 41.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6294 2.33% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5938 2.20% 45.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5209 1.93% 47.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6036 2.24% 50.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12883 4.78% 54.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 93825 34.78% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27824 10.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269744 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 154172 # Number of branches executed +system.cpu.iew.exec_nop 130 # number of nop insts executed +system.cpu.iew.exec_rate 3.294656 # Inst execution rate +system.cpu.iew.exec_refs 371135 # number of memory reference insts executed +system.cpu.iew.exec_stores 112764 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2318 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 258513 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 113591 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1034781 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 258371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1104 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1029804 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2877 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 713 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2932 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 569 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 140 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 78 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2438 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 557 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1277106 # num instructions consuming a value +system.cpu.iew.wb_count 1027868 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.577195 # average fanout of values written-back +system.cpu.iew.wb_producers 737139 # num instructions producing a value +system.cpu.iew.wb_rate 3.288462 # insts written-back per cycle +system.cpu.iew.wb_sent 1028662 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1294575 # number of integer regfile reads +system.cpu.int_regfile_writes 665220 # number of integer regfile writes +system.cpu.ipc 3.199304 # IPC: Instructions Per Cycle +system.cpu.ipc_total 3.199304 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 578607 56.13% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6240 0.61% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 9 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4094 0.40% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15852 1.54% 58.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 6163 0.60% 59.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 21995 2.13% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 21995 2.13% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 22 0.00% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 2072 0.20% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 38 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2087 0.20% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 258670 25.09% 89.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 112972 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1030912 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5321 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005161 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 519 9.75% 9.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.02% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2475 46.51% 56.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 195 3.66% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 5 0.09% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.02% 60.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.04% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1818 34.17% 94.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 305 5.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 922482 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2112204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 917053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 937630 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1034581 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1030912 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11951 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 269744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.821816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.843448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 61206 22.69% 22.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17814 6.60% 29.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21088 7.82% 37.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22536 8.35% 45.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26893 9.97% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24003 8.90% 64.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18524 6.87% 71.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 56857 21.08% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 20823 7.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269744 # Number of insts issued each cycle +system.cpu.iq.rate 3.298201 # Inst issue rate +system.cpu.iq.vec_alu_accesses 113740 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 224805 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 110815 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 111851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2064 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2465 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 258513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 113591 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 948337 # number of misc regfile reads +system.cpu.misc_regfile_writes 70292 # number of misc regfile writes +system.cpu.numCycles 312568 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 5775 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1206644 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4616 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 53304 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 6698 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2146469 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1038011 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1225360 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 146000 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 40512 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 713 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 55711 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 18540 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1304214 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 8241 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 282 # count of serializing insts renamed +system.cpu.rename.skidInsts 60610 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 171953 # Number of vector rename lookups +system.cpu.rob.rob_reads 1253156 # The number of ROB reads +system.cpu.rob.rob_writes 2071426 # The number of ROB writes +system.cpu.timesIdled 418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 171247 # number of vector regfile reads +system.cpu.vec_regfile_writes 94563 # number of vector regfile writes +system.cpu.workload.numSyscalls 7 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1859 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 5706 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 12316 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 615 # Transaction distribution +system.membus.trans_dist::ReadExReq 698 # Transaction distribution +system.membus.trans_dist::ReadExResp 698 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 615 # Transaction distribution +system.membus.trans_dist::InvalidateReq 546 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1859 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1859 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1859 # Request fanout histogram +system.membus.reqLayer0.occupancy 2153000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 6928250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2880 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 5434 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 135 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 137 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2357 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 568 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 568 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1185 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 17739 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 18924 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 700736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 742976 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6610 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000151 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012300 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6609 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6610 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 11727000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.5 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8556500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 12 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4717 # number of demand (read+write) hits +system.l2.demand_hits::total 4729 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 12 # number of overall hits +system.l2.overall_hits::.cpu.data 4717 # number of overall hits +system.l2.overall_hits::total 4729 # number of overall hits +system.l2.demand_misses::.cpu.inst 513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 800 # number of demand (read+write) misses +system.l2.demand_misses::total 1313 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 513 # number of overall misses +system.l2.overall_misses::.cpu.data 800 # number of overall misses +system.l2.overall_misses::total 1313 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40757500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 61617000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 102374500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40757500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 61617000 # number of overall miss cycles +system.l2.overall_miss_latency::total 102374500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 525 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5517 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6042 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 525 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5517 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6042 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.977143 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.145006 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.217312 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.977143 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.145006 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.217312 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.demand_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.overall_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 800 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 800 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35627500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 53617000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 89244500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35627500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 53617000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 89244500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.217312 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.217312 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 135 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 135 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 135 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 135 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 2462 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 2462 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 698 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 698 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 22 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 22 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 546 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 546 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19130.036630 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19130.036630 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1068.548216 # Cycle average of tags in use +system.l2.tags.total_refs 11769 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1879 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 6.263438 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 265.121704 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 444.344216 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 359.082296 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.008091 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013560 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.010958 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.032610 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1857 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 954 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.056671 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 100399 # Number of tag accesses +system.l2.tags.data_accesses 100399 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51200 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 84032 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 800 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1313 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 210080431 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 327610809 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 537691240 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 210080431 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 327610809 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 537691240 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 800.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000574000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2616 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1313 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1313 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 157 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 117 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 104 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 142 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 41 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 103 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10714750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6565000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 35333500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8160.51 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26910.51 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1092 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 83.17 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1313 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 688 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 427 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 156 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 221 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 380.235294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 226.255947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 366.440593 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 64 28.96% 28.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 47 21.27% 50.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 38 17.19% 67.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 6 2.71% 70.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 2.71% 72.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 3.62% 76.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.71% 79.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.26% 81.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 18.55% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 221 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 84032 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 84032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 537.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 537.69 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 153415000 # Total gap between requests +system.mem_ctrls.avgGap 116843.11 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51200 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 210080431.012970060110 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 327610808.597224235535 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 800 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14512750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 20820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28289.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26025.94 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 642600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 341550 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 5776260 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 12292800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 37806390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 28176000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 85035600 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 544.112923 # Core power per rank (mW) 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commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 30736680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 34129440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 82189965 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 525.904705 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 88357250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 5200000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79398.093333 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79398.093333 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 344.224798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 42641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 81.220952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 344.224798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.672314 # Average percentage of cache occupancy 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misses +system.cpu.dcache.overall_misses::total 50298 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 928146470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 928146470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 928146470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 928146470 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 369275 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 369275 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 369300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 369300 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.136202 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.136202 # miss rate for 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access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 5434 # number of writebacks +system.cpu.dcache.writebacks::total 5434 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 44213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44213 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6083 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6083 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 6085 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 6085 # number of overall MSHR misses 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overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 22557.938209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22557.938209 # average overall mshr miss latency +system.cpu.dcache.replacements 5571 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 250218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 250218 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 7375 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7375 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 89676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 257593 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 257593 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 111118 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 111118 # number of WriteReq accesses(hits+misses) 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rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.028483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 436.655859 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 325186 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6083 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 53.458162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 436.655859 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 450 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 744889 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 744889 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 156283000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/mcf/config.ini b/TAGE_SC_L_benchmarks/mcf/config.ini new file mode 100644 index 000000000..25fdefc9a --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//data/ref/input/inp.in +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=inp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 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+tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/mcf/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/mcf/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/mcf/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/mcf/config.json b/TAGE_SC_L_benchmarks/mcf/config.json new file mode 100644 index 000000000..988e5ebb9 --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/mcf/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/mcf/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/mcf/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + 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a/TAGE_SC_L_benchmarks/mcf/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/mcf/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/mcf/fs/proc/stat b/TAGE_SC_L_benchmarks/mcf/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/mcf/inp.out b/TAGE_SC_L_benchmarks/mcf/inp.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/mcf/stats.txt b/TAGE_SC_L_benchmarks/mcf/stats.txt new file mode 100644 index 000000000..cf8e43d5f --- /dev/null +++ b/TAGE_SC_L_benchmarks/mcf/stats.txt @@ -0,0 +1,1361 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 500536000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 150345 # Simulator instruction rate (inst/s) +host_mem_usage 851208 # Number of bytes of host memory used +host_op_rate 170550 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.65 # Real time elapsed on the host +host_tick_rate 75251159 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1134416 # Number of ops (including micro ops) simulated +sim_seconds 0.000501 # Number of seconds simulated +sim_ticks 500536000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.358374 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 92293 # Number of BTB hits +system.cpu.branchPred.BTBLookups 92889 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 809 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 181500 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3097 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3299 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 202 # Number of indirect misses. +system.cpu.branchPred.lookups 226647 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 118031 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60367 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 116682 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61716 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6619 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4134 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 2960 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 4214 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 600 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1232 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 602 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 594 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 563 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 69 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 31 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 23 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 154608 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 346 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1189 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 5426 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 4062 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 596 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1232 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 602 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 594 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 224 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 23041 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 38 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 11371 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 469065 # number of cc regfile reads +system.cpu.cc_regfile_writes 445002 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 567 # The number of times a branch was mispredicted +system.cpu.commit.branches 222072 # Number of branches committed +system.cpu.commit.bw_lim_events 63204 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14510 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000623 # Number of instructions committed +system.cpu.commit.committedOps 1135038 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 921910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.231181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320907 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 599089 64.98% 64.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 111489 12.09% 77.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 58121 6.30% 83.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 30329 3.29% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25620 2.78% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7612 0.83% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 14974 1.62% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11472 1.24% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63204 6.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 921910 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 10970 # Number of function calls committed. +system.cpu.commit.int_insts 986971 # Number of committed integer instructions. +system.cpu.commit.loads 170934 # Number of loads committed +system.cpu.commit.membars 1232 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 830 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 769661 67.81% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6011 0.53% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1895 0.17% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 1893 0.17% 68.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 1668 0.15% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2267 0.20% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 170934 15.06% 84.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 179876 15.85% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1135038 # Class of committed instruction +system.cpu.commit.refs 350810 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 19901 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1134416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.001072 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.001072 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 369143 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 245 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 92282 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1154444 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 337025 # Number of cycles decode is idle +system.cpu.decode.RunCycles 207687 # Number of cycles decode is running +system.cpu.decode.SquashCycles 679 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 9570 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 226647 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 151079 # Number of cache lines fetched +system.cpu.fetch.Cycles 515682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 503 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1024163 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1842 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.226404 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 407448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 106761 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.023065 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 924104 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.529422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 694266 75.13% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24064 2.60% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21313 2.31% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29222 3.16% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 37715 4.08% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20366 2.20% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6389 0.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 10142 1.10% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 80627 8.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 924104 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 76969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 223488 # Number of branches executed +system.cpu.iew.exec_nop 654 # number of nop insts executed +system.cpu.iew.exec_rate 1.165904 # Inst execution rate +system.cpu.iew.exec_refs 376201 # number of memory reference insts executed +system.cpu.iew.exec_stores 181843 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2328 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 172837 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1266 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 182525 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1150122 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 194358 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 818 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1167155 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 11080 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11091 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 1371 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10811 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16776 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1902 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 170 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1099277 # num instructions consuming a value +system.cpu.iew.wb_count 1144060 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.512096 # average fanout of values written-back +system.cpu.iew.wb_producers 562935 # num instructions producing a value +system.cpu.iew.wb_rate 1.142834 # insts written-back per cycle +system.cpu.iew.wb_sent 1144769 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1326039 # number of integer regfile reads +system.cpu.int_regfile_writes 763044 # number of integer regfile writes +system.cpu.ipc 0.998929 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.998929 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 848 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 776608 66.49% 66.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6014 0.51% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1951 0.17% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1948 0.17% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1706 0.15% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2303 0.20% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 194587 16.66% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 182006 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1167974 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 28747 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024613 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6136 21.34% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 21.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7980 27.76% 49.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 14627 50.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1174093 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3246005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1123907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1143560 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1148202 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1167974 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15046 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 924104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.263899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.974668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 558743 60.46% 60.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 87176 9.43% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72815 7.88% 77.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64315 6.96% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49642 5.37% 90.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39656 4.29% 94.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27197 2.94% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14287 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10273 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 924104 # Number of insts issued each cycle +system.cpu.iq.rate 1.166722 # Inst issue rate +system.cpu.iq.vec_alu_accesses 21780 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 42868 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 20153 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 20989 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 16339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7820 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 172837 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 182525 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 795052 # number of misc regfile reads +system.cpu.misc_regfile_writes 4929 # number of misc regfile writes +system.cpu.numCycles 1001073 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 10901 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1211210 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 5977 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 340701 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 119 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1857450 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1152162 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1227536 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 214110 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 97675 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 679 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 108200 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 16315 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1311537 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 249513 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3792 # count of serializing insts renamed +system.cpu.rename.skidInsts 38106 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 24991 # Number of vector rename lookups +system.cpu.rob.rob_reads 2007201 # The number of ROB reads +system.cpu.rob.rob_writes 2301310 # The number of ROB writes +system.cpu.timesIdled 7434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 24540 # number of vector regfile reads +system.cpu.vec_regfile_writes 10206 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4607 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15831 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 32533 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1281 # Transaction distribution +system.membus.trans_dist::ReadExReq 3311 # Transaction distribution +system.membus.trans_dist::ReadExResp 3311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1281 # Transaction distribution +system.membus.trans_dist::InvalidateReq 15 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4607 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4607 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4607 # Request fanout histogram +system.membus.reqLayer0.occupancy 5392000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 23805750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 13349 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4041 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 10990 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 800 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 11349 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2000 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 15 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 15 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 33688 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15547 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 49235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 1429696 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 600256 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2029952 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 16702 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000060 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.007738 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 16701 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 16702 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31297500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8014500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 17023500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 10829 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1266 # number of demand (read+write) hits +system.l2.demand_hits::total 12095 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 10829 # number of overall hits +system.l2.overall_hits::.cpu.data 1266 # number of overall hits +system.l2.overall_hits::total 12095 # number of overall hits +system.l2.demand_misses::.cpu.inst 520 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4072 # number of demand (read+write) misses +system.l2.demand_misses::total 4592 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 520 # number of overall misses +system.l2.overall_misses::.cpu.data 4072 # number of overall misses +system.l2.overall_misses::total 4592 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40890000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 355596000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 396486000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40890000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 355596000 # number of overall miss cycles +system.l2.overall_miss_latency::total 396486000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 11349 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5338 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16687 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 11349 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5338 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16687 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.045819 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.762833 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.275184 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.045819 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.762833 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.275184 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 520 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4072 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 4592 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 520 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4072 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 4592 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35690000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 314876000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 350566000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35690000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 314876000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 350566000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.275184 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.275184 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 10989 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 10989 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 10989 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 10989 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 27 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 27 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3311 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3311 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 15 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 15 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18966.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18966.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2520.152590 # Cycle average of tags in use +system.l2.tags.total_refs 32517 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 4605 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 7.061238 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 11.282538 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 502.340959 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2006.529093 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000344 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.015330 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.061234 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.076909 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4605 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 742 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 3779 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.140533 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 264861 # Number of tag accesses +system.l2.tags.data_accesses 264861 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33280 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 260608 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 293888 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 520 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4072 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 4592 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 66488724 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 520657855 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 587146579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 66488724 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 520657855 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 587146579 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 520.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000696500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 9183 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 4592 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 4592 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 322 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 275 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 310 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 422 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 261 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 286 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 312 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 257 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 301 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 208 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 273 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.53 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 74344250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 22960000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 160444250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16189.95 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34939.95 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4061 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.44 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 4592 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2205 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1063 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 694 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 619 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 529 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 553.981096 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 351.714124 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 410.059059 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 90 17.01% 17.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 113 21.36% 38.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 5.67% 44.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 28 5.29% 49.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 4.35% 53.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 17 3.21% 56.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 3.21% 60.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 32 6.05% 66.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 179 33.84% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 529 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 293888 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 293888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 587.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 587.15 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.59 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 500327000 # Total gap between requests +system.mem_ctrls.avgGap 108956.23 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33280 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 260608 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 66488724.087777905166 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 520657854.779676198959 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 520 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4072 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14303500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 146140750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27506.73 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 35889.18 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 88.44 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1899240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1001880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 14915460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 201196320 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 22777440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 281127300 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 561.652509 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 57508250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 16640000 # Time in different power states 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17541.246349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 10990 # number of writebacks +system.cpu.icache.writebacks::total 10990 # number of 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number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 139575 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 139575 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 11504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11504 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 201794498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201794498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 151079 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 151079 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.076146 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.076146 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 17541.246349 # average ReadReq miss latency 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15967.353776 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 349.312772 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 150924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11349 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.298440 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 349.312772 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.682252 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.682252 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 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replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 53073.277036 # average ReadReq miss latency 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# average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 80085.484480 # average WriteReq miss latency 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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86593.974813 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.788749 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 338206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5353 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.180646 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.788749 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 692269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 692269 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 500536000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/milc/config.ini b/TAGE_SC_L_benchmarks/milc/config.ini new file mode 100644 index 000000000..7d4d3cccf --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//data/ref/input/su3imp.in +kvmInSE=false +maxStackSize=67108864 +output=su3imp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/milc/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/milc/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/milc/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/milc/config.json b/TAGE_SC_L_benchmarks/milc/config.json new file mode 100644 index 000000000..eecb6b034 --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + 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0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/milc/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/milc/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/milc/fs/proc/stat b/TAGE_SC_L_benchmarks/milc/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/milc/stats.txt b/TAGE_SC_L_benchmarks/milc/stats.txt new file mode 100644 index 000000000..4e74bbcff --- /dev/null +++ b/TAGE_SC_L_benchmarks/milc/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 771934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 105815 # Simulator instruction rate (inst/s) +host_mem_usage 852608 # Number of bytes of host memory used +host_op_rate 109546 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.45 # Real time elapsed on the host +host_tick_rate 81680042 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000005 # Number of instructions simulated +sim_ops 1035288 # Number of ops (including micro ops) simulated +sim_seconds 0.000772 # Number of seconds simulated +sim_ticks 771934000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.792148 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 67887 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68717 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1100 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 42422 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 82 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 306 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 224 # Number of indirect misses. +system.cpu.branchPred.lookups 143579 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 21294 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 6454 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14513 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 13235 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 18 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 234 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 319 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 469 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 42 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 328 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 410 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 138 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 529 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 231 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 760 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 930 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 414 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1635 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 37 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 281 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 93 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 101 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 11 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 36 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 16937 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 387 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 174 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1951 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 71 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 8 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 323 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 409 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 59 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 350 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 231 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 530 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1869 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1647 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 687 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 196 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 10082 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 14 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 80 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 49901 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 68964 # number of cc regfile reads +system.cpu.cc_regfile_writes 68721 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 797 # The number of times a branch was mispredicted +system.cpu.commit.branches 89552 # Number of branches committed +system.cpu.commit.bw_lim_events 63878 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 169 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 505862 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000413 # Number of instructions committed +system.cpu.commit.committedOps 1035696 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1429782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.724373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.819359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1058409 74.03% 74.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 200068 13.99% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61768 4.32% 92.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9481 0.66% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20769 1.45% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6490 0.45% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5334 0.37% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3585 0.25% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63878 4.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1429782 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 30618 # Number of function calls committed. +system.cpu.commit.int_insts 1016144 # Number of committed integer instructions. +system.cpu.commit.loads 160773 # Number of loads committed +system.cpu.commit.membars 142 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 35 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 521896 50.39% 50.39% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 158304 15.28% 65.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 60283 5.82% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 83 0.01% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 138 0.01% 71.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 140 0.01% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 103 0.01% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160773 15.52% 87.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 133941 12.93% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1035696 # Class of committed instruction +system.cpu.commit.refs 294714 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1073 # Number of committed Vector instructions. +system.cpu.committedInsts 1000005 # Number of Instructions Simulated +system.cpu.committedOps 1035288 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.543861 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.543861 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1103566 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 305 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 67843 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1736058 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 125816 # Number of cycles decode is idle +system.cpu.decode.RunCycles 212734 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4634 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1033 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 49279 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 143579 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 215175 # Number of cache lines fetched +system.cpu.fetch.Cycles 1257140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1758524 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9874 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.092999 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 233891 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 117870 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.139037 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.215674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.571580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1160787 77.59% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24293 1.62% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 54513 3.64% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17903 1.20% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26423 1.77% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35114 2.35% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 27991 1.87% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 9593 0.64% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 139412 9.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 47840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2747 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 132264 # Number of branches executed +system.cpu.iew.exec_nop 464 # number of nop insts executed +system.cpu.iew.exec_rate 0.984822 # Inst execution rate +system.cpu.iew.exec_refs 473801 # number of memory reference insts executed +system.cpu.iew.exec_stores 198453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 332881 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 276092 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 214 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 228886 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1701929 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 275348 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1520436 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17214 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 49608 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4634 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75400 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 3665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 149 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 115309 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 94929 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2518 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1610580 # num instructions consuming a value +system.cpu.iew.wb_count 1454780 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.646638 # average fanout of values written-back +system.cpu.iew.wb_producers 1041462 # num instructions producing a value +system.cpu.iew.wb_rate 0.942295 # insts written-back per cycle +system.cpu.iew.wb_sent 1519421 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2248203 # number of integer regfile reads +system.cpu.int_regfile_writes 1261314 # number of integer regfile writes +system.cpu.ipc 0.647727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.647727 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 779760 51.22% 51.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 199683 13.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 67953 4.46% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 85 0.01% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 140 0.01% 68.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 140 0.01% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 107 0.01% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 275910 18.12% 86.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 198634 13.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1522447 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1173303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.770669 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7553 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 612118 52.17% 52.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 533999 45.51% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11437 0.97% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8193 0.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 2694513 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5738105 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1453690 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2366292 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1701251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1522447 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 666110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 26240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 514802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1496029 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.017659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.601098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 888614 59.40% 59.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200614 13.41% 72.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 178533 11.93% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95716 6.40% 91.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45502 3.04% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45883 3.07% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22769 1.52% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17602 1.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 796 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1496029 # Number of insts issued each cycle +system.cpu.iq.rate 0.986124 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1202 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2360 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1090 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1315 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 4086 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 166 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 276092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 228886 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 923178 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.numCycles 1543869 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 463634 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 914731 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 93277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 136560 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 125 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2724794 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1715294 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1498240 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239996 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 537737 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4634 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 638173 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 583452 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2637927 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 13032 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 390 # count of serializing insts renamed +system.cpu.rename.skidInsts 224398 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 223 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1492 # Number of vector rename lookups +system.cpu.rob.rob_reads 2857867 # The number of ROB reads +system.cpu.rob.rob_writes 3149444 # The number of ROB writes +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1321 # number of vector regfile reads +system.cpu.vec_regfile_writes 571 # number of vector regfile writes +system.cpu.workload.numSyscalls 26 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 13062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 29025 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 25 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 31663 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 25 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 753 # Transaction distribution +system.membus.trans_dist::WritebackDirty 13041 # Transaction distribution +system.membus.trans_dist::CleanEvict 21 # Transaction distribution +system.membus.trans_dist::ReadExReq 15203 # Transaction distribution +system.membus.trans_dist::ReadExResp 15202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 753 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 15963 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15963 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15963 # Request fanout histogram +system.membus.reqLayer0.occupancy 85449500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 11.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 83558250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 959 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 28109 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 412 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 59 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 15204 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 15202 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 816 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 143 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 7 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 7 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2044 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 45787 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 47831 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 78592 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 1946432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2025024 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 13087 # Total snoops (count) +system.tol2bus.snoopTraffic 834624 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 29257 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000889 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.029798 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 29231 99.91% 99.91% # Request fanout histogram +system.tol2bus.snoop_fanout::1 26 0.09% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 29257 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31311500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 23021000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 3.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1224000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 203 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4 # number of demand (read+write) hits +system.l2.demand_hits::total 207 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 203 # number of overall hits +system.l2.overall_hits::.cpu.data 4 # number of overall hits +system.l2.overall_hits::total 207 # number of overall hits +system.l2.demand_misses::.cpu.inst 613 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 15343 # number of demand (read+write) misses +system.l2.demand_misses::total 15956 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 613 # number of overall misses +system.l2.overall_misses::.cpu.data 15343 # number of overall misses +system.l2.overall_misses::total 15956 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 47921500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1333591000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1381512500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 47921500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1333591000 # number of overall miss cycles +system.l2.overall_miss_latency::total 1381512500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 816 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 15347 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16163 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 816 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 15347 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16163 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.751225 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999739 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.987193 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.751225 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999739 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.987193 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 13041 # number of writebacks +system.l2.writebacks::total 13041 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 613 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 15343 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 15956 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 613 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 15343 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 15956 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 41791500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1180181000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1221972500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 41791500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1180181000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1221972500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.987193 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.987193 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.replacements 13087 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 411 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 411 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 411 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 411 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 15203 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 15203 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2615.918231 # Cycle average of tags in use +system.l2.tags.total_refs 31653 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 15957 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.983644 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.225835 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 565.825416 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2048.866980 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000037 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.017268 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.062526 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.079831 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2870 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1846 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 822 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.087585 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 269253 # Number of tag accesses +system.l2.tags.data_accesses 269253 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 39232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 981952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1021184 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 834624 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 834624 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 613 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 15343 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 15956 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 13041 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 13041 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 50822998 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1272067301 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1322890299 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1081211606 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 50822998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1272067301 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2404101905 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 13041.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 613.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 15343.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000013500250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 813 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 813 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 43428 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 12201 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 15956 # Number of read requests accepted +system.mem_ctrls.writeReqs 13041 # Number of write requests accepted +system.mem_ctrls.readBursts 15956 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 13041 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 992 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1054 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 982 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 972 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1073 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 985 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1026 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 956 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 979 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1036 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1008 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 976 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 814 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 811 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 818 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 815 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 810 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.02 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 249603250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 79780000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 548778250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 15643.22 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34393.22 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 13782 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 11296 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.62 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 15956 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 13041 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7854 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7660 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 818 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 3886 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 476.557900 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 444.203406 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 118.434932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 147 3.78% 3.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 4.04% 7.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 28 0.72% 8.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 185 4.76% 13.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3341 85.98% 99.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 0.21% 99.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 0.08% 99.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 0.10% 99.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 0.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 3886 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 813 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.611316 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.109728 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 102.759447 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 812 99.88% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2944-3071 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 813 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 813 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.007380 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.006268 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.210429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 812 99.88% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.12% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 813 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 1021184 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 832896 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1021184 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 834624 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1322.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1078.97 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1322.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1081.21 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 18.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.34 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 8.43 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 771884000 # Total gap between requests +system.mem_ctrls.avgGap 26619.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 39232 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 981952 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 832896 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 50822997.821057237685 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1272067301.090507745743 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1078973072.827469587326 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 613 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 15343 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 13041 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 16555500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 532222750 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 15715577750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27007.34 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 34688.31 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 1205089.93 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 86.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 14080080 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 7460970 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 57398460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 33971760 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 334312410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14896800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 522969840 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 677.479992 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 36020250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 710173750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 13708800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 7286400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 33961320 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 335170830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 14173920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 521678010 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 675.806494 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 34169250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 712024750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 214182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 214182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 214182 # number of overall hits +system.cpu.icache.overall_hits::total 214182 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 993 # number of overall misses +system.cpu.icache.overall_misses::total 993 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 62276498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62276498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 62276498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62276498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 215175 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 215175 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 215175 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 215175 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.004615 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004615 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.004615 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004615 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 62715.506546 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62715.506546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 62715.506546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62715.506546 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 943 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.583333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 412 # number of writebacks +system.cpu.icache.writebacks::total 412 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 177 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 816 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 816 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 816 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 816 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 51375498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51375498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 51375498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51375498 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.003792 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003792 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.003792 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003792 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62960.169118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62960.169118 # average overall mshr miss latency +system.cpu.icache.replacements 412 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 214182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 214182 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 62276498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62276498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 215175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 215175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.004615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 62715.506546 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62715.506546 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 51375498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51375498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.003792 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003792 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62960.169118 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 395.647856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 214998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 816 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 263.477941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 395.647856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.772750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.772750 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 404 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 431166 # Number of tag accesses +system.cpu.icache.tags.data_accesses 431166 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 279583 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 279583 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 279634 # number of overall hits +system.cpu.dcache.overall_hits::total 279634 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 128971 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 128971 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 128976 # number of overall misses +system.cpu.dcache.overall_misses::total 128976 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 10006739847 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10006739847 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 10006739847 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10006739847 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 408554 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408554 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 408610 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408610 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.315677 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.315677 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.315646 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.315646 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 77589.069225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77589.069225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 77586.061337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77586.061337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 95515 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.948112 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 15068 # number of writebacks +system.cpu.dcache.writebacks::total 15068 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 113621 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113621 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 113621 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113621 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 15350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 15350 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 15353 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 15353 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 1356375996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1356375996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 1356610496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1356610496 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.037572 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037572 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.037574 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037574 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 88363.257068 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88363.257068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 88361.264639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.264639 # average overall mshr miss latency +system.cpu.dcache.replacements 15081 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 274439 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 274439 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 295 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 295 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 23351500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23351500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 274734 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 274734 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001074 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001074 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 79157.627119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79157.627119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 84978.417266 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84978.417266 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5144 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5144 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 128669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 128669 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 9983165849 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9983165849 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 133813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 133813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.961558 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.961558 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 77587.964848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77587.964848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 113465 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 113465 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 15204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 15204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 1344348498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1344348498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.113621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.113621 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 88420.711523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88420.711523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 264.979661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 295294 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 15352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.234888 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 264.979661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.529297 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 833190 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 833190 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 771934000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/milc/su3imp.out b/TAGE_SC_L_benchmarks/milc/su3imp.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/namd/config.ini b/TAGE_SC_L_benchmarks/namd/config.ini new file mode 100644 index 000000000..cd6cd5e1d --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross --input /home/min/a/ece565/benchspec-2020/CPU2006/444.namd//data/all/input/namd.input --iterations 1 --output namd.out +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=namd.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 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+clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/namd/config.json b/TAGE_SC_L_benchmarks/namd/config.json new file mode 100644 index 000000000..2abc5e7a4 --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/config.json @@ -0,0 +1,1816 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + 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1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/namd/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/namd/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/namd/fs/proc/stat b/TAGE_SC_L_benchmarks/namd/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/namd/namd.stdout b/TAGE_SC_L_benchmarks/namd/namd.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/namd/stats.txt b/TAGE_SC_L_benchmarks/namd/stats.txt new file mode 100644 index 000000000..339525bf1 --- /dev/null +++ b/TAGE_SC_L_benchmarks/namd/stats.txt @@ -0,0 +1,1346 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 342062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 157818 # Simulator instruction rate (inst/s) +host_mem_usage 853680 # Number of bytes of host memory used +host_op_rate 175433 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.34 # Real time elapsed on the host +host_tick_rate 53981928 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1111649 # Number of ops (including micro ops) simulated +sim_seconds 0.000342 # Number of seconds simulated +sim_ticks 342062500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.672835 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118809 # Number of BTB hits +system.cpu.branchPred.BTBLookups 120407 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4928 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2833 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3243 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 410 # Number of indirect misses. +system.cpu.branchPred.lookups 252244 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 101918 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 65407 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 97895 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 69430 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 234 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3091 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1934 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 549 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 986 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1869 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1433 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 568 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 590 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1553 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 981 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1682 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1384 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 768 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 526 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 379 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 818 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 872 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1097 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 812 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1409 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 264 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 124175 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 959 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3431 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1422 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4096 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3051 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 5683 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2247 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1586 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1202 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 973 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1537 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 634 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1807 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 738 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 513 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 962 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1080 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1488 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 37083 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 680 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1093 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 12668 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 107 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 406413 # number of cc regfile reads +system.cpu.cc_regfile_writes 399910 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4465 # The number of times a branch was mispredicted +system.cpu.commit.branches 216048 # Number of branches committed +system.cpu.commit.bw_lim_events 53496 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 486 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 118898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001856 # Number of instructions committed +system.cpu.commit.committedOps 1113505 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 605513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.838945 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.532655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 255756 42.24% 42.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 143185 23.65% 65.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57737 9.54% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36800 6.08% 81.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21553 3.56% 85.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8832 1.46% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10972 1.81% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17182 2.84% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53496 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 605513 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 11108 # Number of function calls committed. +system.cpu.commit.int_insts 980744 # Number of committed integer instructions. +system.cpu.commit.loads 176934 # Number of loads committed +system.cpu.commit.membars 475 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 185 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 796966 71.57% 71.59% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3693 0.33% 71.92% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 912 0.08% 72.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 438 0.04% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 15 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 9 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1629 0.15% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 433 0.04% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 647 0.06% 72.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 598 0.05% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 526 0.05% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 176934 15.89% 88.28% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 130493 11.72% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1113505 # Class of committed instruction +system.cpu.commit.refs 307427 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 10353 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1111649 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.684126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.684126 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 123704 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 477 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117668 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1269158 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 241422 # Number of cycles decode is idle +system.cpu.decode.RunCycles 244786 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4577 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1653 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 8066 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 252244 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 191602 # Number of cache lines fetched +system.cpu.fetch.Cycles 351490 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1163577 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10080 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.368710 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 265962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 134310 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.700823 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 622555 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.077656 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.946208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 354909 57.01% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36395 5.85% 62.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35829 5.76% 68.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29315 4.71% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25782 4.14% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22071 3.55% 81.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22996 3.69% 84.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16066 2.58% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 79192 12.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 622555 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 61571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 226272 # Number of branches executed +system.cpu.iew.exec_nop 1973 # number of nop insts executed +system.cpu.iew.exec_rate 1.731738 # Inst execution rate +system.cpu.iew.exec_refs 336529 # number of memory reference insts executed +system.cpu.iew.exec_stores 137581 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 18776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199413 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 143076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1232740 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 198948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1184727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 75 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4577 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 13404 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 51 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11145 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 22474 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 12581 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 51 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3178 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1611 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1051584 # num instructions consuming a value +system.cpu.iew.wb_count 1169811 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.565495 # average fanout of values written-back +system.cpu.iew.wb_producers 594666 # num instructions producing a value +system.cpu.iew.wb_rate 1.709935 # insts written-back per cycle +system.cpu.iew.wb_sent 1171681 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1338795 # number of integer regfile reads +system.cpu.int_regfile_writes 842064 # number of integer regfile writes +system.cpu.ipc 1.461719 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.461719 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 205 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 843381 70.75% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3830 0.32% 71.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 913 0.08% 71.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 443 0.04% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 22 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 9 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1911 0.16% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 1 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 490 0.04% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 729 0.06% 71.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 662 0.06% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 561 0.05% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 200822 16.85% 88.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138126 11.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1192128 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19491 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016350 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7584 38.91% 38.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 286 1.47% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 16 0.08% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 1 0.01% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 37 0.19% 40.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 40.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 32 0.16% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3651 18.73% 59.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7880 40.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1198409 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3001822 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1158219 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1335839 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1230257 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1192128 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 119104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 604 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 91660 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 622555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.914896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.081400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 224872 36.12% 36.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 111647 17.93% 54.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 80394 12.91% 66.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 65833 10.57% 77.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57137 9.18% 86.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35638 5.72% 92.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25524 4.10% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9768 1.57% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11742 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 622555 # Number of insts issued each cycle +system.cpu.iq.rate 1.742556 # Inst issue rate +system.cpu.iq.vec_alu_accesses 13005 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 25084 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 11592 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 14079 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 11813 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10481 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 143076 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 814624 # number of misc regfile reads +system.cpu.misc_regfile_writes 2390 # number of misc regfile writes +system.cpu.numCycles 684126 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 20510 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1188200 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4829 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 245465 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1607 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 197 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1901749 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1255514 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1346306 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 248576 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 43450 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4577 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 52052 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 158085 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1414708 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 51375 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2390 # count of serializing insts renamed +system.cpu.rename.skidInsts 24882 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 512 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 11865 # Number of vector rename lookups +system.cpu.rob.rob_reads 1783497 # The number of ROB reads +system.cpu.rob.rob_writes 2481923 # The number of ROB writes +system.cpu.timesIdled 2175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 11159 # number of vector regfile reads +system.cpu.vec_regfile_writes 5976 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 3 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 3085 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 7097 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1021 # Transaction distribution +system.membus.trans_dist::ReadExReq 385 # Transaction distribution +system.membus.trans_dist::ReadExResp 385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1021 # Transaction distribution +system.membus.trans_dist::InvalidateReq 12 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1418 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1418 # Request fanout histogram +system.membus.reqLayer0.occupancy 1743000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 7466000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3603 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 123 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 98 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 397 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 397 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3346 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 257 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 12 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 12 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 9556 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1553 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 11109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 397440 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 49728 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 447168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 4012 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000748 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.027338 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 4009 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 4012 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 6535500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 987499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 5019000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2570 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 2594 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2570 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 2594 # number of overall hits +system.l2.demand_misses::.cpu.inst 776 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 630 # number of demand (read+write) misses +system.l2.demand_misses::total 1406 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 776 # number of overall misses +system.l2.overall_misses::.cpu.data 630 # number of overall misses +system.l2.overall_misses::total 1406 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61228500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 53298500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 114527000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61228500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 53298500 # number of overall miss cycles +system.l2.overall_miss_latency::total 114527000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3346 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 654 # number of demand (read+write) accesses +system.l2.demand_accesses::total 4000 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3346 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 654 # number of overall (read+write) accesses +system.l2.overall_accesses::total 4000 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.231919 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.963303 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.351500 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.231919 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.963303 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.351500 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.demand_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.overall_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 776 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 630 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1406 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 776 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 630 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1406 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53468500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 46998500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 100467000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53468500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 46998500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 100467000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.351500 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.351500 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 123 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 123 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2862 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2862 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2862 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2862 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 12 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 12 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 385 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 385 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 12 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 12 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19166.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19166.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1147.163949 # Cycle average of tags in use +system.l2.tags.total_refs 7082 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1414 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 5.008487 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 3.100039 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 718.567739 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 425.496172 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.021929 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.012985 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.035009 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1307 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.043152 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 58166 # Number of tag accesses +system.l2.tags.data_accesses 58166 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 49664 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 40320 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 89984 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 776 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 630 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1406 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 145189841 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 117873196 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 263063037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 145189841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 117873196 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 263063037 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 776.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 630.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000595500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2857 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1406 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1406 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 188 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.12 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 16247000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 7030000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 42609500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 11555.48 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 30305.48 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1036 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1406 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 925 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 309 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 119 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 366 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 244.459016 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 165.753947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 253.358390 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 108 29.51% 29.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 154 42.08% 71.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 34 9.29% 80.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21 5.74% 86.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 2.19% 88.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.28% 92.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 1.64% 93.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.09% 94.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 19 5.19% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 366 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 89984 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 89984 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 263.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 263.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.06 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.06 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 341590500 # Total gap between requests +system.mem_ctrls.avgGap 242951.99 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 49664 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 40320 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 145189841.037822037935 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 117873195.687922537327 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 776 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 630 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21553250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 21056250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27774.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33422.62 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 73.68 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1342320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 705870 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4219740 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 142332420 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 11493120 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 186522990 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 545.289209 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 28704750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 302177750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1299480 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5819100 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 102551550 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 44992800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 181775550 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 531.410342 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 116125500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 214757000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 188002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 188002 # number of overall hits +system.cpu.icache.overall_hits::total 188002 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3599 # number of overall misses +system.cpu.icache.overall_misses::total 3599 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 110804999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 110804999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 110804999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 110804999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 191601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 191601 # number of demand (read+write) accesses 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.052632 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2864 # number of writebacks +system.cpu.icache.writebacks::total 2864 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 253 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 253 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 253 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 3346 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3346 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 3346 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3346 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 93334999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 93334999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 93334999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 93334999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.017463 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.017463 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.017463 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.017463 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 27894.500598 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27894.500598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 27894.500598 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27894.500598 # average overall mshr miss latency +system.cpu.icache.replacements 2864 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 188002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188002 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 3599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3599 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 110804999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 110804999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 191601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 191601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.018784 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018784 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 30787.718533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30787.718533 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 253 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 3346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 93334999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 93334999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.017463 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017463 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 27894.500598 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27894.500598 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 455.896294 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 191348 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.187089 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 455.896294 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.890422 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.890422 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 482 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 479 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386548 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386548 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 300898 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 300898 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 302152 # number of overall hits +system.cpu.dcache.overall_hits::total 302152 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 2484 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2484 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 2487 # number of overall misses +system.cpu.dcache.overall_misses::total 2487 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 191127451 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 191127451 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 191127451 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 191127451 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 303382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 303382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 304639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 304639 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.008188 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008188 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.008164 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008164 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 76943.418277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76943.418277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 76850.603538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76850.603538 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4244 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.136986 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 123 # number of writebacks +system.cpu.dcache.writebacks::total 123 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1821 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1821 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 666 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 666 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 54682992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54682992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 54913492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54913492 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.002185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.002186 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002186 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 82478.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82478.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 82452.690691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82452.690691 # average overall mshr miss latency +system.cpu.dcache.replacements 221 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 172595 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 172595 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 770 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 56980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 173365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 173365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.004441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 74000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 254 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 20680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.001465 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001465 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 81419.291339 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81419.291339 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 128296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128296 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1706 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 133892953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133892953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 344.568452 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 303779 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 666 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 456.124625 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 344.568452 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.869141 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 611866 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 611866 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 342062500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/omnetpp/config.ini b/TAGE_SC_L_benchmarks/omnetpp/config.ini new file mode 100644 index 000000000..54bfe7e69 --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + 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+clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//data/ref/input/omnetpp.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=omnetpp.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false 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+app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/omnetpp/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/omnetpp/config.json b/TAGE_SC_L_benchmarks/omnetpp/config.json new file mode 100644 index 000000000..a0e9b2a65 --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + 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+ "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/omnetpp/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/omnetpp/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/omnetpp/fs/proc/stat b/TAGE_SC_L_benchmarks/omnetpp/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/omnetpp/omnetpp.log b/TAGE_SC_L_benchmarks/omnetpp/omnetpp.log new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/omnetpp/stats.txt b/TAGE_SC_L_benchmarks/omnetpp/stats.txt new file mode 100644 index 000000000..5bca03da4 --- /dev/null +++ b/TAGE_SC_L_benchmarks/omnetpp/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 600830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 143137 # Simulator instruction rate (inst/s) +host_mem_usage 872532 # Number of bytes of host memory used +host_op_rate 153888 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.99 # Real time elapsed on the host +host_tick_rate 85998751 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1075135 # Number of ops (including micro ops) simulated +sim_seconds 0.000601 # Number of seconds simulated +sim_ticks 600830500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.016583 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 148545 # Number of BTB hits +system.cpu.branchPred.BTBLookups 153113 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6561 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 256294 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1996 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3048 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 1052 # Number of indirect misses. +system.cpu.branchPred.lookups 344799 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 124051 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60754 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113162 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71643 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 344 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 45 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5324 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2167 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 57 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 329 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3284 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1458 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 3422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 757 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1066 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1083 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 405 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 765 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 867 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 766 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1241 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 905 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 993 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 494 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1436 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 209 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 568 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 152787 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 781 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1385 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 307 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 552 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 955 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1870 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2792 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1115 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 782 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 948 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 502 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 815 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 890 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1314 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1593 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1083 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 24677 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 269 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1362 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 31611 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 517 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 559188 # number of cc regfile reads +system.cpu.cc_regfile_writes 492774 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4887 # The number of times a branch was mispredicted +system.cpu.commit.branches 250422 # Number of branches committed +system.cpu.commit.bw_lim_events 61679 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 540 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 250346 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1003357 # Number of instructions committed +system.cpu.commit.committedOps 1078492 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1060509 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.016957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.129603 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 743853 70.14% 70.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104575 9.86% 80.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 71710 6.76% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25390 2.39% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28256 2.66% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8269 0.78% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10913 1.03% 93.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5864 0.55% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61679 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1060509 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 24973 # Number of function calls committed. +system.cpu.commit.int_insts 934829 # Number of committed integer instructions. +system.cpu.commit.loads 104843 # Number of loads committed +system.cpu.commit.membars 532 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 12 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 870934 80.75% 80.76% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 40054 3.71% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 38 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 47 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 49 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 47 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 104843 9.72% 94.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 62445 5.79% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1078492 # Class of committed instruction +system.cpu.commit.refs 167288 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 699 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1075135 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.201662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.201662 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 617643 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1684 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 144015 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1375078 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 199308 # Number of cycles decode is idle +system.cpu.decode.RunCycles 230164 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4951 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 7329 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 42522 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 344799 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 251042 # Number of cache lines fetched +system.cpu.fetch.Cycles 796828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3081 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1341720 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 13250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.286935 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 290887 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182152 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.116554 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.312222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 757448 69.20% 69.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52806 4.82% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72422 6.62% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 31200 2.85% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 29155 2.66% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36050 3.29% 89.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 20265 1.85% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35303 3.23% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59939 5.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 107074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 5288 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 292397 # Number of branches executed +system.cpu.iew.exec_nop 3630 # number of nop insts executed +system.cpu.iew.exec_rate 1.036673 # Inst execution rate +system.cpu.iew.exec_refs 190511 # number of memory reference insts executed +system.cpu.iew.exec_stores 68247 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 236197 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131642 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 697 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 72865 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1329304 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8709 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1245730 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1309 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1325 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4951 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5211 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 7688 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2529 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 10420 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2944 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1319747 # num instructions consuming a value +system.cpu.iew.wb_count 1234451 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.515417 # average fanout of values written-back +system.cpu.iew.wb_producers 680220 # num instructions producing a value +system.cpu.iew.wb_rate 1.027286 # insts written-back per cycle +system.cpu.iew.wb_sent 1237611 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1401236 # number of integer regfile reads +system.cpu.int_regfile_writes 922560 # number of integer regfile writes +system.cpu.ipc 0.832181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.832181 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1018643 81.20% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 40062 3.19% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 26 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 54 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 70 0.01% 84.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 69 0.01% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126059 10.05% 94.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 69382 5.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1254440 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 10878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008672 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8498 78.12% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.02% 78.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 6 0.06% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 685 6.30% 84.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1687 15.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1264404 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3613205 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1233634 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1575017 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1325083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1254440 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 591 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 250524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 671 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 145632 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1094588 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.146039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.729328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 605474 55.32% 55.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 173599 15.86% 71.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 126763 11.58% 82.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70125 6.41% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49712 4.54% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23222 2.12% 95.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 26221 2.40% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11120 1.02% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8352 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1094588 # Number of insts issued each cycle +system.cpu.iq.rate 1.043921 # Inst issue rate +system.cpu.iq.vec_alu_accesses 897 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1811 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 817 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1221 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 8896 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6565 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 131642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 72865 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 776684 # number of misc regfile reads +system.cpu.misc_regfile_writes 2121 # number of misc regfile writes +system.cpu.numCycles 1201662 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 386132 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1228037 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 116818 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 213486 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2867 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5124 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2147241 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1354877 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1542516 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 250910 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7919 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4951 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 144869 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 314451 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1523758 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 94240 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2166 # count of serializing insts renamed +system.cpu.rename.skidInsts 218820 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 593 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1144 # Number of vector rename lookups +system.cpu.rob.rob_reads 2327278 # The number of ROB reads +system.cpu.rob.rob_writes 2691796 # The number of ROB writes +system.cpu.timesIdled 1246 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 944 # number of vector regfile reads +system.cpu.vec_regfile_writes 295 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6851 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 6920 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 14864 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 5670 # Transaction distribution +system.membus.trans_dist::ReadExReq 1032 # Transaction distribution +system.membus.trans_dist::ReadExResp 1031 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5670 # Transaction distribution +system.membus.trans_dist::InvalidateReq 149 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 6851 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6851 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6851 # Request fanout histogram +system.membus.reqLayer0.occupancy 8063000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 35377250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 6743 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1272 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1208 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 4440 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1049 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1048 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1718 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 5026 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 151 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 151 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4644 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 18162 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 22806 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 187264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 470080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 657344 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 7944 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.011220 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 7943 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 7944 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9912000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 9185499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2577998 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 205 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 886 # number of demand (read+write) hits +system.l2.demand_hits::total 1091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 205 # number of overall hits +system.l2.overall_hits::.cpu.data 886 # number of overall hits +system.l2.overall_hits::total 1091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5189 # number of demand (read+write) misses +system.l2.demand_misses::total 6702 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1513 # number of overall misses +system.l2.overall_misses::.cpu.data 5189 # number of overall misses +system.l2.overall_misses::total 6702 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 118284000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 389913000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 508197000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 118284000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 389913000 # number of overall miss cycles +system.l2.overall_miss_latency::total 508197000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1718 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 6075 # number of demand (read+write) accesses +system.l2.demand_accesses::total 7793 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1718 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 6075 # number of overall (read+write) accesses +system.l2.overall_accesses::total 7793 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.880675 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.854156 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.860003 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.880675 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.854156 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.860003 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5189 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 6702 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5189 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 6702 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 103154000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 338033000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 441187000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 103154000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 338033000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 441187000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.860003 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.860003 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1208 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1208 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1208 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1208 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 17 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 17 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 1032 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 1032 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 149 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 149 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19114.093960 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19114.093960 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3524.172320 # Cycle average of tags in use +system.l2.tags.total_refs 14713 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 6852 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.147256 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 103.457419 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1250.327723 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2170.387178 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.038157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.066235 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.107549 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 6850 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1057 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 5723 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.209045 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 125756 # Number of tag accesses +system.l2.tags.data_accesses 125756 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 96832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 332032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 428864 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5188 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 6701 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 161163589 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 552621746 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 713785335 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 161163589 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 552621746 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 713785335 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5189.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000592250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 13490 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 6702 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 6702 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 366 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 531 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 375 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 552 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 486 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 454 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 472 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 373 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 387 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.18 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 40720500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 33510000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 166383000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6075.87 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24825.87 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 5865 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.51 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 6702 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5584 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 809 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an 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+system.mem_ctrls.bytesPerActivate::gmean 327.950498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 396.797343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 152 18.18% 18.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 165 19.74% 37.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 89 10.65% 48.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 53 6.34% 54.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 52 6.22% 61.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 22 2.63% 63.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 21 2.51% 66.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 22 2.63% 68.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 260 31.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 836 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 428928 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 428928 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 713.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 713.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 600814000 # Total gap between requests +system.mem_ctrls.avgGap 89646.97 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 96832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 332096 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 161163589.398341149092 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 552728265.292790651321 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5189 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 40921500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 125461500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27046.60 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24178.36 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2977380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1578720 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24468780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 167296710 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 89837760 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 333486630 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 555.042778 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 231136500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 20020000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 349674000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 2998800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 23383500 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 169256370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 88187520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 332747370 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 553.812381 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 227066750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 20020000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 353743750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 248600 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 248600 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 248600 # number of overall hits +system.cpu.icache.overall_hits::total 248600 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2440 # number of overall misses +system.cpu.icache.overall_misses::total 2440 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 160765498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 160765498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 160765498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 160765498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 251040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 251040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 251040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 251040 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.009720 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009720 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.009720 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009720 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65887.499180 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65887.499180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65887.499180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65887.499180 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1208 # number of writebacks +system.cpu.icache.writebacks::total 1208 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 722 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 722 # number of demand (read+write) MSHR hits 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0.006844 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006844 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.006844 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006844 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 71653.665891 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.665891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 71653.665891 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71653.665891 # average overall mshr miss latency +system.cpu.icache.replacements 1208 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 248600 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 248600 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2440 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 160765498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 160765498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 251040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 251040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.009720 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009720 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 65887.499180 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65887.499180 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 722 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 722 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1718 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1718 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 123100998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123100998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.006844 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006844 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 71653.665891 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.665891 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 483.277910 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 250318 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1718 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.703143 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 483.277910 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.943902 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943902 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 503798 # Number of tag accesses +system.cpu.icache.tags.data_accesses 503798 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 149406 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149406 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 149416 # number of overall hits +system.cpu.dcache.overall_hits::total 149416 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 23408 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23408 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 23410 # number of overall misses +system.cpu.dcache.overall_misses::total 23410 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 1454601825 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1454601825 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 1454601825 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1454601825 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 172814 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172814 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 172826 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172826 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.135452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.135452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.135454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.135454 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 62141.226290 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62141.226290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62135.917343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62135.917343 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8845 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.522088 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1272 # number of writebacks +system.cpu.dcache.writebacks::total 1272 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 17188 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17188 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 17188 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17188 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6220 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6220 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 6222 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 6222 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 412672891 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 412672891 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 412857391 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 412857391 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.035992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.035992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.036002 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.036002 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 66346.123955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66346.123955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 66354.450498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66354.450498 # average overall mshr miss latency +system.cpu.dcache.replacements 5712 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 91292 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 91292 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 19596 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 19596 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 1208935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1208935000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 110888 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110888 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.176719 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.176719 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 61692.947540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61692.947540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 14576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 14576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 5020 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5020 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 324697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 324697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.045271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045271 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 64680.776892 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64680.776892 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 58103 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 58103 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3672 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3672 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 241178421 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241178421 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 61775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 61775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.059442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 65680.397876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65680.397876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2612 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2612 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1060 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1060 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 83626987 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83626987 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78893.383962 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78893.383962 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 472.929101 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156727 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6224 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.181073 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 472.929101 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 354060 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 354060 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 600830500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/povray/SPEC-benchmark-ref.stdout b/TAGE_SC_L_benchmarks/povray/SPEC-benchmark-ref.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/povray/config.ini b/TAGE_SC_L_benchmarks/povray/config.ini new file mode 100644 index 000000000..d6f4f6281 --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 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+children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/453.povray//data/ref/input/SPEC-benchmark-ref.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 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+size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 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system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/povray/config.json b/TAGE_SC_L_benchmarks/povray/config.json new file mode 100644 index 000000000..799434181 --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/povray/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/povray/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/povray/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + 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"PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/povray/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/povray/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/povray/fs/proc/stat b/TAGE_SC_L_benchmarks/povray/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/povray/stats.txt b/TAGE_SC_L_benchmarks/povray/stats.txt new file mode 100644 index 000000000..4fbbab637 --- /dev/null +++ b/TAGE_SC_L_benchmarks/povray/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 440535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 134562 # Simulator instruction rate (inst/s) +host_mem_usage 860024 # Number of bytes of host memory used +host_op_rate 158451 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.43 # Real time elapsed on the host +host_tick_rate 59277888 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1177555 # Number of ops (including micro ops) simulated +sim_seconds 0.000441 # Number of seconds simulated +sim_ticks 440535000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.198572 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115989 # Number of BTB hits +system.cpu.branchPred.BTBLookups 119332 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7435 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 213239 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1230 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2181 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 951 # Number of indirect misses. +system.cpu.branchPred.lookups 290314 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 125053 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 46817 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113188 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 58682 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 918 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 207 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12467 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2851 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1409 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3608 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 980 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2217 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1418 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2515 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1455 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1565 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3315 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2539 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 724 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1115 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1141 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 664 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 235 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2236 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 375 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 687 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 118623 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2119 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2831 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 3677 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3364 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3420 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3217 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2153 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1816 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 2903 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 2587 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1068 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1492 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 2976 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1833 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 514 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 729 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 43932 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 362 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1603 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 29908 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 306 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 385761 # number of cc regfile reads +system.cpu.cc_regfile_writes 379620 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6003 # The number of times a branch was mispredicted +system.cpu.commit.branches 236171 # Number of branches committed +system.cpu.commit.bw_lim_events 73367 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 75 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 136896 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000964 # Number of instructions committed +system.cpu.commit.committedOps 1178517 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 736122 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.600981 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.554495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 393460 53.45% 53.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 135494 18.41% 71.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47723 6.48% 78.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 40908 5.56% 83.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13088 1.78% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12972 1.76% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 13065 1.77% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6045 0.82% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73367 9.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 736122 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 25599 # Number of function calls committed. +system.cpu.commit.int_insts 1058462 # Number of committed integer instructions. +system.cpu.commit.loads 219653 # Number of loads committed +system.cpu.commit.membars 58 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 85 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 803955 68.22% 68.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 43 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 8 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 3 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 24 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 211 0.02% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 346 0.03% 68.28% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 340 0.03% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 4 0.00% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 252 0.02% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 219653 18.64% 86.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 153553 13.03% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1178517 # Class of committed instruction +system.cpu.commit.refs 373206 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2565 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1177555 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.881069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881069 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 352277 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1467 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 112500 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1366665 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 166919 # Number of cycles decode is idle +system.cpu.decode.RunCycles 199841 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6169 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 5195 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 31333 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 290314 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 188047 # Number of cache lines fetched +system.cpu.fetch.Cycles 500939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3491 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1223026 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 15202 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.329501 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 247929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 147127 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.388113 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 756539 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.886749 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.851187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458670 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35950 4.75% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45265 5.98% 71.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36757 4.86% 76.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21735 2.87% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35827 4.74% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 17076 2.26% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19955 2.64% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85304 11.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 756539 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 124532 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 6907 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 248720 # Number of branches executed +system.cpu.iew.exec_nop 1123 # number of nop insts executed +system.cpu.iew.exec_rate 1.425137 # Inst execution rate +system.cpu.iew.exec_refs 396422 # number of memory reference insts executed +system.cpu.iew.exec_stores 160107 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 22254 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 246607 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1641 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 168064 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1316053 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 236315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1255647 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6169 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2685 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 324 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5311 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 52 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2782 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26945 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 14506 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 149 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 4240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2667 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1198971 # num instructions consuming a value +system.cpu.iew.wb_count 1244234 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.560166 # average fanout of values written-back +system.cpu.iew.wb_producers 671623 # num instructions producing a value +system.cpu.iew.wb_rate 1.412184 # insts written-back per cycle +system.cpu.iew.wb_sent 1248252 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1406014 # number of integer regfile reads +system.cpu.int_regfile_writes 902367 # number of integer regfile writes +system.cpu.ipc 1.134985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134985 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 98 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 864482 68.23% 68.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 28 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 42 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 235 0.02% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 384 0.03% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 387 0.03% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 4 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 266 0.02% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 239173 18.88% 87.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 161918 12.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1267085 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015362 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4588 23.57% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 5 0.03% 23.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 18 0.09% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525 33.52% 57.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8328 42.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1283510 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3305038 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1241483 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1448868 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1314816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1267085 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 114 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 137324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 746 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 104243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 756539 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.674844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.170087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360054 47.59% 47.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 105577 13.96% 61.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 70744 9.35% 70.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70123 9.27% 80.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57524 7.60% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29199 3.86% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28653 3.79% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15678 2.07% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18987 2.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 756539 # Number of insts issued each cycle +system.cpu.iq.rate 1.438119 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2942 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 5874 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2751 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 3525 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 3911 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5794 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 246607 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 168064 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 951083 # number of misc regfile reads +system.cpu.misc_regfile_writes 272 # number of misc regfile writes +system.cpu.numCycles 881071 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 35111 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1212533 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 12363 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 181263 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 453 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2001540 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1344395 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1383743 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 215925 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 24594 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6169 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 58674 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171123 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1509943 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 259397 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 14972 # count of serializing insts renamed +system.cpu.rename.skidInsts 139589 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 132 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 3983 # Number of vector rename lookups +system.cpu.rob.rob_reads 1977635 # The number of ROB reads +system.cpu.rob.rob_writes 2651412 # The number of ROB writes +system.cpu.timesIdled 1992 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 3332 # number of vector regfile reads +system.cpu.vec_regfile_writes 1671 # number of vector regfile writes +system.cpu.workload.numSyscalls 16 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2830 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10828 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2059 # Transaction distribution +system.membus.trans_dist::ReadExReq 761 # Transaction distribution +system.membus.trans_dist::ReadExResp 761 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2059 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2830 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2830 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2830 # Request fanout histogram +system.membus.reqLayer0.occupancy 3507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 14927500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4828 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1995 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2596 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 312 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3108 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1720 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 14 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 14 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 8812 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 7941 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16753 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 365056 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 307072 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 672128 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5925 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000169 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012991 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5924 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5925 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 10005000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 4211999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 4662000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1580 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1511 # number of demand (read+write) hits +system.l2.demand_hits::total 3091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1580 # number of overall hits +system.l2.overall_hits::.cpu.data 1511 # number of overall hits +system.l2.overall_hits::total 3091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1528 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1292 # number of demand (read+write) misses +system.l2.demand_misses::total 2820 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1528 # number of overall misses +system.l2.overall_misses::.cpu.data 1292 # number of overall misses +system.l2.overall_misses::total 2820 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 120129500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 101875000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 222004500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 120129500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 101875000 # number of overall miss cycles +system.l2.overall_miss_latency::total 222004500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3108 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2803 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5911 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3108 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2803 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5911 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.491634 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.460935 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.477077 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.491634 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.460935 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.477077 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78725 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78725 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1528 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1292 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2820 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1528 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1292 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2820 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 104849500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 88955000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 193804500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 104849500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 88955000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 193804500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.477077 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.477077 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2596 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2596 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2596 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2596 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 322 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 322 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 761 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 761 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 4 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 4 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18800 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18800 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1655.197760 # Cycle average of tags in use +system.l2.tags.total_refs 10817 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2833 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.818214 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.404433 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1024.255259 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 624.538068 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000195 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.031258 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.019059 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.050513 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2829 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 670 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2156 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.086334 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 89449 # Number of tag accesses +system.l2.tags.data_accesses 89449 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 97792 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 82688 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 180480 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1528 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1292 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2820 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 221984632 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 187699048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 409683680 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 221984632 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 187699048 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 409683680 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1528.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1292.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000578500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5675 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2820 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2820 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 134 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 298 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 133 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 216 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 289 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 221 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 141 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 130 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 137 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 179 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 183 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 24911000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 14100000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 77786000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8833.69 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27583.69 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2231 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.11 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2820 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1806 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 666 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 261 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 73 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an 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does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 588 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 306.829932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 191.362404 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 311.414367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 186 31.63% 31.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 26.70% 58.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 86 14.63% 72.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 6.46% 79.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 3.91% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 1.36% 84.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 2.89% 87.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 18 3.06% 90.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 55 9.35% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 588 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 180480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 180480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 409.68 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 409.68 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 437498000 # Total gap between requests +system.mem_ctrls.avgGap 155141.13 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 97792 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 82688 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 221984632.322062969208 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 187699047.748760044575 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1528 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1292 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 41993750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 35792250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27482.82 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 27702.98 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 79.11 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2241960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1187835 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10695720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 144782850 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 47243040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 240571245 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 546.088835 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 121360750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 304614250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1963500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1043625 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 9439080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 141036240 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 50398080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 238300365 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 540.934012 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 129731500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 296243500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 184461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 184461 # number of overall hits +system.cpu.icache.overall_hits::total 184461 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3585 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3585 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3585 # number of overall misses +system.cpu.icache.overall_misses::total 3585 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 168059999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 168059999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 188046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 188046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 188046 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.019064 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.019064 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.019064 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.019064 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 46878.660809 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46878.660809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 46878.660809 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46878.660809 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1751 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 79.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2596 # number of writebacks +system.cpu.icache.writebacks::total 2596 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 477 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 477 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 477 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 477 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 3108 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3108 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 3108 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3108 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 141521999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 141521999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 141521999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 141521999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 184461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184461 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 3585 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3585 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 168059999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 168059999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 188046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 188046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.019064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.019064 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 46878.660809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46878.660809 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 477 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 477 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 3108 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3108 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 141521999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 141521999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016528 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45534.748713 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 474.750503 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 187569 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3108 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.350386 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 474.750503 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.927247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.927247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379200 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379200 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 371800 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371800 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 372567 # number of overall hits +system.cpu.dcache.overall_hits::total 372567 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 9926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 9954 # number of overall misses +system.cpu.dcache.overall_misses::total 9954 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 439411405 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 439411405 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 439411405 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 439411405 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 381726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 381726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 382521 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 382521 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.026003 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026003 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.026022 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026022 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 44268.729095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44268.729095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 44144.203838 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44144.203838 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13976 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1075 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 333 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 20 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.969970 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.750000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1995 # number of writebacks +system.cpu.dcache.writebacks::total 1995 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 7137 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7137 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 7137 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7137 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 2789 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2789 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 2816 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2816 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 121822488 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 121822488 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 122603988 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 122603988 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.007306 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007306 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 43679.629975 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43679.629975 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 43538.348011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43538.348011 # average overall mshr miss latency +system.cpu.dcache.replacements 2307 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 411.700494 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 375512 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 133.302094 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 411.700494 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 768119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 768119 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 440535000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/sjeng/config.ini b/TAGE_SC_L_benchmarks/sjeng/config.ini new file mode 100644 index 000000000..21fff9625 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 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+opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 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+eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//data/ref/input/ref.txt +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 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+use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/sjeng/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/sjeng/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/sjeng/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/sjeng/config.json b/TAGE_SC_L_benchmarks/sjeng/config.json new file mode 100644 index 000000000..68de32d84 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "TAGE_SC_L_benchmarks/sjeng/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "TAGE_SC_L_benchmarks/sjeng/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "TAGE_SC_L_benchmarks/sjeng/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": 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"smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "Process", + "executable": "/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", + "cwd": "/home/min/a/bnwachuk/Final/gem5", + "pgid": 100, + "simpoint": 0, + "euid": 100, + "input": "cin", + "path": "system.cpu.workload", + "name": "workload", + "cmd": [ + "/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross", + "/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//data/ref/input/ref.txt" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "release": "5.1.0", + "output": "ref.out" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + 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"clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + 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"cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sjeng/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/sjeng/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/sjeng/fs/proc/stat b/TAGE_SC_L_benchmarks/sjeng/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sjeng/ref.out b/TAGE_SC_L_benchmarks/sjeng/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/sjeng/stats.txt b/TAGE_SC_L_benchmarks/sjeng/stats.txt new file mode 100644 index 000000000..664778112 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sjeng/stats.txt @@ -0,0 +1,1415 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 980748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 104020 # Simulator instruction rate (inst/s) +host_mem_usage 855440 # Number of bytes of host memory used +host_op_rate 104740 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.61 # Real time elapsed on the host +host_tick_rate 102014951 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1006944 # Number of ops (including micro ops) simulated +sim_seconds 0.000981 # Number of seconds simulated +sim_ticks 980748500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.766989 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 200381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 200849 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 660 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 202147 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 162 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 162 # Number of indirect misses. +system.cpu.branchPred.lookups 207743 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 3582 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 126240 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 3154 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 126668 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 824 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 236 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 591 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1040 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 362 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 238 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2732 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 10706 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 413 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 561 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 267 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 33 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 100795 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 291 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 581 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 242 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2000 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 18 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 916 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1438 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2770 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 201 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3784 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 171 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 10709 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 162 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 561 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 32 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 28293 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 9 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 41 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2330 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 763581 # number of cc regfile reads +system.cpu.cc_regfile_writes 763725 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 463 # The number of times a branch was mispredicted +system.cpu.commit.branches 134686 # Number of branches committed +system.cpu.commit.bw_lim_events 49449 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 31 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 198975 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000027 # Number of instructions committed +system.cpu.commit.committedOps 1006970 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1903352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.581430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1624847 85.37% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 85631 4.50% 89.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12379 0.65% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 49231 2.59% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 58284 3.06% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21793 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 971 0.05% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 767 0.04% 97.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 49449 2.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1903352 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2158 # Number of function calls committed. +system.cpu.commit.int_insts 879162 # Number of committed integer instructions. +system.cpu.commit.loads 161698 # Number of loads committed +system.cpu.commit.membars 20 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 625681 62.14% 62.14% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 633 0.06% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 19 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 23 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161698 16.06% 78.26% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 218868 21.74% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1006970 # Class of committed instruction +system.cpu.commit.refs 380566 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 339 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1006944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.961496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.961496 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1647816 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 185395 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1239183 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 79217 # Number of cycles decode is idle +system.cpu.decode.RunCycles 142072 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1988 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 753 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 57398 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 207743 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 64422 # Number of cache lines fetched +system.cpu.fetch.Cycles 1852627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 408 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1295277 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.105910 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 73603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 202711 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.660351 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.676031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.761491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1643977 85.25% 85.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3025 0.16% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25385 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1234 0.06% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 190628 9.88% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4849 0.25% 96.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6124 0.32% 97.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3430 0.18% 97.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 49839 2.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 33007 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 539 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 184716 # Number of branches executed +system.cpu.iew.exec_nop 50 # number of nop insts executed +system.cpu.iew.exec_rate 0.617105 # Inst execution rate +system.cpu.iew.exec_refs 432521 # number of memory reference insts executed +system.cpu.iew.exec_stores 268651 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 24614 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 162739 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 269164 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1211943 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 163870 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 682 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1210451 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 80974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1988 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 81014 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 79369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3749 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1041 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 50295 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 396 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 143 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1569905 # num instructions consuming a value +system.cpu.iew.wb_count 1161920 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.418041 # average fanout of values written-back +system.cpu.iew.wb_producers 656285 # num instructions producing a value +system.cpu.iew.wb_rate 0.592364 # insts written-back per cycle +system.cpu.iew.wb_sent 1208711 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1602908 # number of integer regfile reads +system.cpu.int_regfile_writes 757605 # number of integer regfile writes +system.cpu.ipc 0.509815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.509815 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 777546 64.20% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 635 0.05% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 164047 13.54% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 268787 22.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1211134 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 23303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019241 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 569 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21971 94.28% 96.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 758 3.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1233956 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4373200 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1161517 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1416130 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1211854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1211134 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 204944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 237898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1928491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.628022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.395842 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1513888 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 121000 6.27% 84.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31671 1.64% 86.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 101187 5.25% 91.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 108415 5.62% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28444 1.47% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 20642 1.07% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2453 0.13% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 791 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1928491 # Number of insts issued each cycle +system.cpu.iq.rate 0.617454 # Inst issue rate +system.cpu.iq.vec_alu_accesses 474 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 946 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 403 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 719 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2216 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 162739 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 269164 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1877143 # number of misc regfile reads +system.cpu.misc_regfile_writes 81 # number of misc regfile writes +system.cpu.numCycles 1961498 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 106316 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1270067 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 7588 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 100412 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 180 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2955535 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1213947 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1526987 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 176735 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1527719 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1988 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1538180 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 256905 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1606307 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4860 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 99 # count of serializing insts renamed +system.cpu.rename.skidInsts 379312 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 640 # Number of vector rename lookups +system.cpu.rob.rob_reads 3040140 # The number of ROB reads +system.cpu.rob.rob_writes 2437041 # The number of ROB writes +system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 458 # number of vector regfile reads +system.cpu.vec_regfile_writes 126 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 65557 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 164732 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 98357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 350 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 197581 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 350 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 537 # Transaction distribution +system.membus.trans_dist::WritebackDirty 65372 # Transaction distribution +system.membus.trans_dist::CleanEvict 168 # Transaction distribution +system.membus.trans_dist::ReadExReq 2717 # Transaction distribution +system.membus.trans_dist::ReadExResp 2717 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 537 # Transaction distribution +system.membus.trans_dist::InvalidateReq 95921 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 99175 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 99175 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 99175 # Request fanout histogram +system.membus.reqLayer0.occupancy 436705000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 44.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17318250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 563 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 163555 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 71 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 624 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 421 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 142 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 95925 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 95922 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 913 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 295889 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 296802 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 6467712 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 6499200 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 65893 # Total snoops (count) +system.tol2bus.snoopTraffic 4184000 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 165117 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.046057 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 164766 99.79% 99.79% # Request fanout histogram +system.tol2bus.snoop_fanout::1 351 0.21% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 165117 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 197041500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 20.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 52278000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 631500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 6 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 45 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 6 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 45 # number of overall hits +system.l2.demand_misses::.cpu.inst 415 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2839 # number of demand (read+write) misses +system.l2.demand_misses::total 3254 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 415 # number of overall misses +system.l2.overall_misses::.cpu.data 2839 # number of overall misses +system.l2.overall_misses::total 3254 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 32613000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 227186000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 259799000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 32613000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 227186000 # number of overall miss cycles +system.l2.overall_miss_latency::total 259799000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 421 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2878 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3299 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 421 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2878 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3299 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.985748 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.986449 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.986360 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.985748 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.986449 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.986360 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 65375 # number of writebacks +system.l2.writebacks::total 65375 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 415 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2839 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3254 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 415 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2839 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3254 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 28463000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 198796000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 227259000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 28463000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 198796000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 227259000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.986360 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.986360 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.replacements 65893 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 71 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 71 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 71 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 71 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 19 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 19 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 2717 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2717 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19466.567282 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19466.567282 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 23292.165447 # Cycle average of tags in use +system.l2.tags.total_refs 101656 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 98662 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.030346 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 22101.183594 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 161.770983 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1029.210870 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.674475 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.004937 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.031409 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.710820 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 1194 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 10740 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 20834 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1679302 # Number of tag accesses +system.l2.tags.data_accesses 1679302 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 26560 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 181696 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 208256 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 4183808 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4183808 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 415 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2839 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 3254 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 65372 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 65372 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 27081357 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 185262583 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 212343939 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 4265933621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 27081357 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 185262583 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4478277560 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 65372.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 415.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2839.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000056666500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 592 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 592 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 16022 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 67132 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3254 # Number of read requests accepted +system.mem_ctrls.writeReqs 65372 # Number of write requests accepted +system.mem_ctrls.readBursts 3254 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 65372 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 274 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 191 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 189 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 176 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 217 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 178 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 308 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 302 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 4057 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 4030 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 3888 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3947 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 4046 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 4088 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 4091 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 4144 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 4157 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 4156 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 4121 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 4102 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 4228 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 4107 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 16.38 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 31713500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 16270000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 92726000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9746.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28496.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 17 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2870 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 61148 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.20 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 93.54 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3254 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 65372 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1468 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1234 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 491 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 593 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1170 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2364 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1702 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 4354 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3585 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 5869 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 4237 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 6370 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 5698 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 5444 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 5067 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3054 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2674 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 1493 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 929 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 275 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 260 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 266 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 202 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 299 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 277 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 304 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 289 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 328 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 278 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 282 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 325 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 283 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 270 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 292 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 232 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 298 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 298 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 209 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 225 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 174 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 113 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 63 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 54 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 4587 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 956.986266 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 889.505183 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 215.926431 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 106 2.31% 2.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 81 1.77% 4.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 52 1.13% 5.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 90 1.96% 7.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 37 0.81% 7.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 38 0.83% 8.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 32 0.70% 9.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 64 1.40% 10.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4087 89.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4587 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 592 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 5.496622 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 133.738576 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 591 99.83% 99.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::3200-3327 1 0.17% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 592 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 592 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 110.395270 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 97.326672 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 53.606284 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16-23 9 1.52% 1.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24-31 17 2.87% 4.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32-39 10 1.69% 6.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40-47 3 0.51% 6.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48-55 73 12.33% 18.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::56-63 2 0.34% 19.26% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::64-71 7 1.18% 20.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::72-79 2 0.34% 20.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::80-87 108 18.24% 39.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::88-95 3 0.51% 39.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::96-103 6 1.01% 40.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::104-111 8 1.35% 41.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::112-119 104 17.57% 59.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::120-127 2 0.34% 59.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::128-135 172 29.05% 88.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::168-175 13 2.20% 91.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::176-183 9 1.52% 92.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::184-191 6 1.01% 93.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::192-199 9 1.52% 95.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::200-207 3 0.51% 95.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::216-223 1 0.17% 95.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::248-255 2 0.34% 96.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::256-263 2 0.34% 96.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::264-271 3 0.51% 96.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::272-279 8 1.35% 98.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::288-295 1 0.17% 98.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::296-303 4 0.68% 99.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::304-311 2 0.34% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::312-319 3 0.51% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 592 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 208256 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 4182656 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 208256 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4183808 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 212.34 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 4264.76 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 212.34 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 4265.93 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 34.98 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.66 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 33.32 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 980732500 # Total gap between requests +system.mem_ctrls.avgGap 14290.98 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 26560 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 181696 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 4182656 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 27081356.739265978336 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 185262582.609099060297 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 4264759008.043346405029 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 415 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2839 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 65372 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 11386750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 81339250 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 18580665500 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27437.95 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28650.67 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 284229.72 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 93.29 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 16529100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 8774040 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 12580680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 172578420 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 76830000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 274550760 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 145406880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 707249880 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 721.132767 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 366755250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 32500000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 581493250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 16243500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 8629830 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 10652880 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 168559020 # Energy for write commands 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33434.805137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33434.805137 # average overall mshr miss latency +system.cpu.dcache.replacements 98288 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 158208 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 158208 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 390 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 390 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26189500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 158598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.002459 # miss rate for ReadReq accesses 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accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 74663.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74663.043478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 100892 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 100892 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 22008 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22008 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 1372654102 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1372654102 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 122900 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 122900 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.179072 # miss rate for WriteReq accesses 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mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 80829.801532 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80829.801532 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 500.623213 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 357948 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 98800 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.622955 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 500.623213 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 512 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 853742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 853742 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 980748500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/sphinx3/an4.out b/TAGE_SC_L_benchmarks/sphinx3/an4.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/sphinx3/config.ini b/TAGE_SC_L_benchmarks/sphinx3/config.ini new file mode 100644 index 000000000..467257777 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + 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+possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 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+app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/sphinx3/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/TAGE_SC_L_benchmarks/sphinx3/config.json b/TAGE_SC_L_benchmarks/sphinx3/config.json new file mode 100644 index 000000000..f0e1ad2d6 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + 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32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sphinx3/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/sphinx3/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/sphinx3/fs/proc/stat b/TAGE_SC_L_benchmarks/sphinx3/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/sphinx3/stats.txt b/TAGE_SC_L_benchmarks/sphinx3/stats.txt new file mode 100644 index 000000000..c84d8c658 --- /dev/null +++ b/TAGE_SC_L_benchmarks/sphinx3/stats.txt @@ -0,0 +1,1362 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 262124000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 200098 # Simulator instruction rate (inst/s) +host_mem_usage 855720 # Number of bytes of host memory used +host_op_rate 214608 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.00 # Real time elapsed on the host +host_tick_rate 52448371 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1072552 # Number of ops (including micro ops) simulated +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 262124000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 96.464447 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 63381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 65704 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 3839 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 95325 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 994 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1699 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 705 # Number of indirect misses. +system.cpu.branchPred.lookups 140686 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 46115 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 33541 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 45341 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 34315 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 321 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 103 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1573 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1223 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 208 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 125 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 99 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 269 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 265 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 114 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 113 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 69 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 103 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 55 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 71 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 111 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 103 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 667 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 99 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 401 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 70432 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 390 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 164 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1364 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 381 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 692 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 167 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1655 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 216 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 152 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 354 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 127 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 101 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 79 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 46 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 55 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 109 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 77 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 77 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 140 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 144 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 5369 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 174 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 463 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 18625 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 220 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 179476 # number of cc regfile reads +system.cpu.cc_regfile_writes 176795 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3085 # The number of times a branch was mispredicted +system.cpu.commit.branches 119983 # Number of branches committed +system.cpu.commit.bw_lim_events 96974 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 228 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 61655 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000505 # Number of instructions committed +system.cpu.commit.committedOps 1073057 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 418375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.564821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.292903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194354 46.45% 46.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 59808 14.30% 60.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29677 7.09% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8925 2.13% 69.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5687 1.36% 71.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12453 2.98% 74.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7164 1.71% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3333 0.80% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 96974 23.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 418375 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 17242 # Number of function calls committed. +system.cpu.commit.int_insts 734201 # Number of committed integer instructions. +system.cpu.commit.loads 142765 # Number of loads committed +system.cpu.commit.membars 204 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 116 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 548333 51.10% 51.11% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3271 0.30% 51.42% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 457 0.04% 51.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 71130 6.63% 58.09% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 58.09% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 22496 2.10% 60.18% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 48537 4.52% 64.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 149838 13.96% 78.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3 0.00% 78.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 40433 3.77% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 276 0.03% 82.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 82.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 332 0.03% 82.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 300 0.03% 82.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 82.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 333 0.03% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 142765 13.30% 95.86% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 44433 4.14% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1073057 # Class of committed instruction +system.cpu.commit.refs 187198 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 433458 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1072552 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.524249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.524249 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 54009 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 772 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 62851 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1160527 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 156875 # Number of cycles decode is idle +system.cpu.decode.RunCycles 209741 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3188 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2606 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 4140 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 140686 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 126273 # Number of cache lines fetched +system.cpu.fetch.Cycles 256214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2031 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1099785 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 7884 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.268357 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 167713 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 83000 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.097829 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 427953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.767416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 205833 48.10% 48.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13163 3.08% 51.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34349 8.03% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25506 5.96% 65.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21816 5.10% 70.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 10056 2.35% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22547 5.27% 77.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4345 1.02% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 90338 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 427953 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 96296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3849 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 126141 # Number of branches executed +system.cpu.iew.exec_nop 623 # number of nop insts executed +system.cpu.iew.exec_rate 2.123289 # Inst execution rate +system.cpu.iew.exec_refs 199745 # number of memory reference insts executed +system.cpu.iew.exec_stores 46919 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 19278 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 153387 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 274 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1244 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 50232 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1134863 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 152826 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1113132 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 160 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 731 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3188 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1021 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 277 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2573 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 92 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1848 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 10609 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5799 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 92 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1474 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1358128 # num instructions consuming a value +system.cpu.iew.wb_count 1106645 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.631922 # average fanout of values written-back +system.cpu.iew.wb_producers 858231 # num instructions producing a value +system.cpu.iew.wb_rate 2.110915 # insts written-back per cycle +system.cpu.iew.wb_sent 1108482 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 843864 # number of integer regfile reads +system.cpu.int_regfile_writes 556092 # number of integer regfile writes +system.cpu.ipc 1.907491 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.907491 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 134 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 578928 51.75% 51.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3335 0.30% 52.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 483 0.04% 52.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 71137 6.36% 58.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 58.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 22501 2.01% 60.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 48544 4.34% 64.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 149850 13.40% 78.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3 0.00% 78.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 40472 3.62% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 320 0.03% 81.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 381 0.03% 81.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 342 0.03% 81.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 385 0.03% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153991 13.77% 95.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 47790 4.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1118601 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 39140 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034990 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2336 5.97% 5.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 523 1.34% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 9434 24.10% 31.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 8931 22.82% 54.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 54.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 13417 34.28% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 1 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1557 3.98% 92.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2940 7.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 691665 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1804991 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 672835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 760861 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1133966 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1118601 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 274 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 61589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 796 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 41055 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 427953 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.613841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.212838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102583 23.97% 23.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 51282 11.98% 35.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69011 16.13% 52.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 68408 15.98% 68.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52050 12.16% 80.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33459 7.82% 88.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21697 5.07% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17308 4.04% 97.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12155 2.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 427953 # Number of insts issued each cycle +system.cpu.iq.rate 2.133721 # Inst issue rate +system.cpu.iq.vec_alu_accesses 465942 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 900090 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 433810 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 435056 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1920 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2168 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 153387 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 50232 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1655966 # number of misc regfile reads +system.cpu.misc_regfile_writes 292823 # number of misc regfile writes +system.cpu.numCycles 524249 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23162 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1424093 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2569 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 160142 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 521 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 578 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2968369 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1150360 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1504695 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 210258 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5064 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3188 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 10163 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 80438 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 889297 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 21040 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 987 # count of serializing insts renamed +system.cpu.rename.skidInsts 17013 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 274 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 720945 # Number of vector rename lookups +system.cpu.rob.rob_reads 1455684 # The number of ROB reads +system.cpu.rob.rob_writes 2279181 # The number of ROB writes +system.cpu.timesIdled 1397 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 719978 # number of vector regfile reads +system.cpu.vec_regfile_writes 436284 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1903 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 3 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2245 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 5451 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1527 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution +system.membus.trans_dist::ReadExResp 182 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1527 # Transaction distribution +system.membus.trans_dist::InvalidateReq 194 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 109376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 109376 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1903 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1903 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1903 # Request fanout histogram +system.membus.reqLayer0.occupancy 2366500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 9057750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2741 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 308 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1763 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 174 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 217 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 217 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2272 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 469 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 248 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 248 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 6307 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 2350 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 8657 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 258240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 63616 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 321856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3206 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000936 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.030580 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3203 99.91% 99.91% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.09% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3206 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 4796500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1153000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3408000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1082 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 167 # number of demand (read+write) hits +system.l2.demand_hits::total 1249 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1082 # number of overall hits +system.l2.overall_hits::.cpu.data 167 # number of overall hits +system.l2.overall_hits::total 1249 # number of overall hits +system.l2.demand_misses::.cpu.inst 1190 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 519 # number of demand (read+write) misses +system.l2.demand_misses::total 1709 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1190 # number of overall misses +system.l2.overall_misses::.cpu.data 519 # number of overall misses +system.l2.overall_misses::total 1709 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 92408500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 42177500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 134586000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 92408500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 42177500 # number of overall miss cycles +system.l2.overall_miss_latency::total 134586000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2272 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 686 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2958 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2272 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 686 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2958 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.523768 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.756560 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.577755 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.523768 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.756560 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.577755 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77654.201681 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81266.859345 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78751.316559 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77654.201681 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81266.859345 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78751.316559 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1190 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1709 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1190 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1709 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 80508500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 36987500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 117496000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 80508500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 36987500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 117496000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.756560 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.577755 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.756560 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.577755 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71266.859345 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68751.316559 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71266.859345 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68751.316559 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 308 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 308 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 308 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 308 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1762 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1762 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1762 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1762 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 35 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 35 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 182 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 182 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 15019500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 15019500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 217 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 217 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.838710 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.838710 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82524.725275 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82524.725275 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 182 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 182 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 13199500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 13199500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.838710 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.838710 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72524.725275 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72524.725275 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1082 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1082 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1190 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1190 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 92408500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 92408500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2272 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2272 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.523768 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.523768 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77654.201681 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77654.201681 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1190 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1190 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 80508500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 80508500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.523768 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67654.201681 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 132 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 132 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 337 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 337 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 27158000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 27158000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 469 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 469 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.718550 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.718550 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80587.537092 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80587.537092 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 337 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 337 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 23788000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 23788000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.718550 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.718550 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70587.537092 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70587.537092 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 54 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 54 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 194 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 194 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 248 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 248 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.782258 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.782258 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 194 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 194 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 3710500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 3710500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.782258 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.782258 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19126.288660 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19126.288660 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1352.510825 # Cycle average of tags in use +system.l2.tags.total_refs 5254 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1851 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.838466 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 54.036738 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 907.826980 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 390.647106 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001649 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.027705 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.011922 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.041275 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1777 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.054840 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 45435 # Number of tag accesses +system.l2.tags.data_accesses 45435 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 76160 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 109376 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 76160 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 76160 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1190 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1709 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 290549511 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 126718652 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 417268163 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 290549511 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 290549511 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 290549511 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 126718652 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 417268163 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1190.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000582000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3420 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1709 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1709 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 148 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 17 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 197 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 203 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15085750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 8545000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 47129500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8827.24 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27577.24 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1344 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.64 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1709 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1019 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 477 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 159 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 365 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 299.660274 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 187.787436 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 307.137251 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 111 30.41% 30.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 111 30.41% 60.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 42 11.51% 72.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 31 8.49% 80.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 3.29% 84.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 2.19% 86.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.19% 88.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 2.19% 90.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 34 9.32% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 365 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 109376 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 109376 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 417.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 417.27 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.26 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 219764000 # Total gap between requests +system.mem_ctrls.avgGap 128592.16 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 76160 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 290549510.918496549129 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 126718652.240924134851 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1190 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 31535750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 15593750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26500.63 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 30045.76 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.64 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1156680 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 614790 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6897240 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 64134120 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46648320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 139734270 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 533.084609 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 120660250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8580000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 132883750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1449420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 770385 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5305020 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 86269500 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 28008000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 142085445 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 542.054314 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 72058250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 8580000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states 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misses +system.cpu.icache.overall_misses::total 2677 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 129130499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 129130499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 129130499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 129130499 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 126273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 126273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 126273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 126273 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.021200 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.021200 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.021200 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.021200 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 48237.018678 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48237.018678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 48237.018678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48237.018678 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1678 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1763 # number of writebacks +system.cpu.icache.writebacks::total 1763 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 405 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 405 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2272 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2272 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2272 # number of overall MSHR misses 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overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 47226.011884 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47226.011884 # average overall mshr miss latency +system.cpu.icache.replacements 1763 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 123596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 123596 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2677 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 129130499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 129130499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 126273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 126273 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017993 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 47226.011884 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47226.011884 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 456.192415 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 125868 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2272 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 55.399648 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 456.192415 # Average occupied blocks per requestor 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various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 197156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 197458 # number of overall hits +system.cpu.dcache.overall_hits::total 197458 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 3082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 3093 # number of overall misses +system.cpu.dcache.overall_misses::total 3093 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 183074284 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 183074284 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 183074284 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 183074284 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 200238 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 200238 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 200551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 200551 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.015392 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015392 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.015423 # miss rate for overall accesses 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access was blocked +system.cpu.dcache.writebacks::.writebacks 308 # number of writebacks +system.cpu.dcache.writebacks::total 308 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2155 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2155 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2155 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2155 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 932 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 932 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 51327831 # number of demand (read+write) MSHR miss cycles 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mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55364.089056 # average overall mshr miss latency +system.cpu.dcache.replacements 482 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 154147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 154147 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1849 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1849 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 114822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 155996 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 155996 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.011853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 62099.513250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62099.513250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1387 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1387 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 28829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 62401.515152 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62401.515152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 42966 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 42966 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 994 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 994 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 61448448 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61448448 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 43960 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 43960 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.022611 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022611 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 61819.364185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61819.364185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 768 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 768 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 226 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 226 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 15933495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15933495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.005141 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005141 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 70502.190265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70502.190265 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 302 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 302 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 313 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 313 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035144 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035144 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.015974 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.015974 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 54300 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54300 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 43 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 43 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 239 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 239 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 6803836 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 6803836 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 282 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 282 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.847518 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.847518 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 28467.933054 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 28467.933054 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 239 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 239 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 6564836 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 6564836 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.847518 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.847518 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 27467.933054 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 27467.933054 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 218 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 218 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 219000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 219000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.018018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 54750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 189000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 189000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.009009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.009009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 94500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 94500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 204 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 204 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 204 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 204 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 356.298250 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 198814 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 934 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 212.862955 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 195500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 356.298250 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.695895 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.695895 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 452 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 432 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.882812 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 402888 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 402888 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 262124000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/TAGE_SC_L_benchmarks/xalancbmk/config.ini b/TAGE_SC_L_benchmarks/xalancbmk/config.ini new file mode 100644 index 000000000..a93a11fc3 --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + 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+power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross -v /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/t5.xml /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/xalanc.xsl +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/xalancbmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/xalancbmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=TAGE_SC_L_benchmarks/xalancbmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state 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"qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/cpuinfo b/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/stat b/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/online b/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/possible b/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/TAGE_SC_L_benchmarks/xalancbmk/ref.out b/TAGE_SC_L_benchmarks/xalancbmk/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/TAGE_SC_L_benchmarks/xalancbmk/stats.txt b/TAGE_SC_L_benchmarks/xalancbmk/stats.txt new file mode 100644 index 000000000..b4505dd21 --- /dev/null +++ b/TAGE_SC_L_benchmarks/xalancbmk/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 579856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 127936 # Simulator instruction rate (inst/s) +host_mem_usage 890880 # Number of bytes of host memory used +host_op_rate 155554 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.82 # Real time elapsed on the host +host_tick_rate 74182822 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1215895 # Number of ops (including micro ops) simulated +sim_seconds 0.000580 # Number of seconds simulated +sim_ticks 579856000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 92.857196 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 125269 # Number of BTB hits +system.cpu.branchPred.BTBLookups 134905 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 107 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 11090 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 208840 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2001 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 5384 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 3383 # Number of indirect misses. +system.cpu.branchPred.lookups 273110 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 99747 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 76380 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 95577 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80550 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 1187 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 233 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 19143 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3731 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1461 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2431 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1071 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 834 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2172 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2216 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3513 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1300 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1037 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 983 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1106 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1086 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 406 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 255 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 39 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 17 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2272 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 369 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 806 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 125944 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2445 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2345 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 11110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1906 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3138 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 862 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4631 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1319 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1155 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 629 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 847 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 575 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 23 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39556 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 358 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1467 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 22387 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 987 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 419976 # number of cc regfile reads +system.cpu.cc_regfile_writes 419014 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 7417 # The number of times a branch was mispredicted +system.cpu.commit.branches 221019 # Number of branches committed +system.cpu.commit.bw_lim_events 61414 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 571 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 143338 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001904 # Number of instructions committed +system.cpu.commit.committedOps 1217799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 902904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.338428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 554856 61.45% 61.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 105154 11.65% 73.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72671 8.05% 81.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36450 4.04% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25173 2.79% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23567 2.61% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17219 1.91% 92.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6400 0.71% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61414 6.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902904 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 16953 # Number of function calls committed. +system.cpu.commit.int_insts 1112699 # Number of committed integer instructions. +system.cpu.commit.loads 173888 # Number of loads committed +system.cpu.commit.membars 554 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 844574 69.35% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1323 0.11% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 95 0.01% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 2 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 21 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 22 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 55 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 173888 14.28% 83.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 197792 16.24% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1217799 # Class of committed instruction +system.cpu.commit.refs 371680 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1107 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1215895 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.159715 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.159715 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 374344 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 3766 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 125047 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1416652 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 260178 # Number of cycles decode is idle +system.cpu.decode.RunCycles 263754 # Number of cycles decode is running +system.cpu.decode.SquashCycles 7605 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 14784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 19324 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 273110 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 214136 # Number of cache lines fetched +system.cpu.fetch.Cycles 589369 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5867 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1237549 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 165 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 22604 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.235498 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 324221 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 149657 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.067115 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 925205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.614934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.765819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 597384 64.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 80324 8.68% 73.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34451 3.72% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27811 3.01% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24777 2.68% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24101 2.60% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15521 1.68% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17941 1.94% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102895 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 925205 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 234510 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9099 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 236093 # Number of branches executed +system.cpu.iew.exec_nop 2122 # number of nop insts executed +system.cpu.iew.exec_rate 1.139700 # Inst execution rate +system.cpu.iew.exec_refs 411841 # number of memory reference insts executed +system.cpu.iew.exec_stores 208001 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 23049 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199610 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 629 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4062 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 215816 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1362258 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 203840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11775 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1321727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 48124 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 7605 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 48219 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 4300 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 26 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11458 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25721 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 18022 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 108 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 5522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3577 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1201356 # num instructions consuming a value +system.cpu.iew.wb_count 1299572 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.538563 # average fanout of values written-back +system.cpu.iew.wb_producers 647006 # num instructions producing a value +system.cpu.iew.wb_rate 1.120596 # insts written-back per cycle +system.cpu.iew.wb_sent 1304297 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1618351 # number of integer regfile reads +system.cpu.int_regfile_writes 892161 # number of integer regfile writes +system.cpu.ipc 0.862281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.862281 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 32 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 915262 68.64% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1337 0.10% 68.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 103 0.01% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 2 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 23 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 24 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 65 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 206702 15.50% 84.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 209919 15.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1333503 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 11914 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008934 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3953 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4390 36.85% 70.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3571 29.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1343852 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3602156 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1298270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1502413 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1359507 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1333503 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 629 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 144232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 58 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 86393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 925205 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.441305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.054051 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 498135 53.84% 53.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 118576 12.82% 66.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 83984 9.08% 75.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64521 6.97% 82.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52354 5.66% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39145 4.23% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42831 4.63% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14003 1.51% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11656 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 925205 # Number of insts issued each cycle +system.cpu.iq.rate 1.149854 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1533 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3047 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1302 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2061 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 9744 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13227 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 215816 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 935747 # number of misc regfile reads +system.cpu.misc_regfile_writes 2172 # number of misc regfile writes +system.cpu.numCycles 1159715 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 76994 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1229281 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 8458 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 273167 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 4162 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2182900 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1394927 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1400311 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 268873 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 102227 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 7605 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 124732 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171018 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1710175 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 173834 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.skidInsts 98664 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 639 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1643 # Number of vector rename lookups +system.cpu.rob.rob_reads 2201236 # The number of ROB reads +system.cpu.rob.rob_writes 2744762 # The number of ROB writes +system.cpu.timesIdled 3555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1296 # number of vector regfile reads +system.cpu.vec_regfile_writes 152 # number of vector regfile writes +system.cpu.workload.numSyscalls 28 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 7702 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 8 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 10142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 21309 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 4080 # Transaction distribution +system.membus.trans_dist::ReadExReq 3453 # Transaction distribution +system.membus.trans_dist::ReadExResp 3453 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4080 # Transaction distribution +system.membus.trans_dist::InvalidateReq 169 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7702 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7702 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7702 # Request fanout histogram +system.membus.reqLayer0.occupancy 9544500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 39849750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 7371 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 3884 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 5199 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1059 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 5712 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1659 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 172 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 172 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 16622 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15853 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 32475 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 698240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 586688 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1284928 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 11167 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000716 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.026757 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 11159 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 8 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 11167 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 19737500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8012496 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 8568499 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2643 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 818 # number of demand (read+write) hits +system.l2.demand_hits::total 3461 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2643 # number of overall hits +system.l2.overall_hits::.cpu.data 818 # number of overall hits +system.l2.overall_hits::total 3461 # number of overall hits +system.l2.demand_misses::.cpu.inst 3068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4465 # number of demand (read+write) misses +system.l2.demand_misses::total 7533 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 3068 # number of overall misses +system.l2.overall_misses::.cpu.data 4465 # number of overall misses +system.l2.overall_misses::total 7533 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 244130500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 348269000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 592399500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 244130500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 348269000 # number of overall miss cycles +system.l2.overall_miss_latency::total 592399500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 5711 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5283 # number of demand (read+write) accesses +system.l2.demand_accesses::total 10994 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 5711 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5283 # number of overall (read+write) accesses +system.l2.overall_accesses::total 10994 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.537209 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.845164 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.685192 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.537209 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.845164 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.685192 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 3068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4465 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 7533 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 3068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4465 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 7533 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 213450500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 303619000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 517069500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 213450500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 303619000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 517069500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.685192 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.685192 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 5196 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 5196 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 5196 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 5196 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 171 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 171 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3453 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3453 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1659 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1659 # number of ReadSharedReq accesses(hits+misses) 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+system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 3 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 3 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 169 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 169 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19147.928994 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19147.928994 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3795.325559 # Cycle average of tags in use +system.l2.tags.total_refs 21134 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 7705 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.742894 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 104.826620 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1882.074184 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1808.424755 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003199 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.057436 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.055189 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.115824 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 7702 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 6364 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.235046 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 178129 # Number of tag accesses +system.l2.tags.data_accesses 178129 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 196352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 285760 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 482112 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 3068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4465 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 7533 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 338622003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 492812008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 831434011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 338622003 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 492812008 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 831434011 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 3068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4465.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000681500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 15052 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 7533 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 7533 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 615 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 664 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 376 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 668 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 653 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 381 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 361 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 344 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 303 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 438 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 468 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 542 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 626 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.48 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 65889750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 37665000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 207133500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8746.81 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27496.81 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 6067 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.54 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 7533 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 4675 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 2113 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 553 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What 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195 13.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1463 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 482112 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 482112 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 831.43 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 831.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 6.50 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 579750500 # Total gap between requests +system.mem_ctrls.avgGap 76961.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 196352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 285760 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 338622002.704119622707 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 492812008.498661696911 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 3068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4465 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 87227000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 119906500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28431.23 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26854.76 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.54 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3991260 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2117610 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24782940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 209475570 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46264320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 332115060 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 572.754373 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 118055750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 19240000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 442560250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6475980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3434475 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 29002680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 254494740 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 8353440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 347244675 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 598.846395 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 18199250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 19240000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 542416750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 207011 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 207011 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 207011 # number of overall hits +system.cpu.icache.overall_hits::total 207011 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 7122 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7122 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 7122 # number of overall misses +system.cpu.icache.overall_misses::total 7122 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 351779497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351779497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 351779497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351779497 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 214133 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 214133 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 214133 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 214133 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.033260 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.033260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.033260 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033260 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1632 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.275862 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 5199 # number of writebacks +system.cpu.icache.writebacks::total 5199 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 1410 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1410 # number of demand (read+write) MSHR hits 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+system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.026675 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.026675 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.026675 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.026675 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 49196.515756 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49196.515756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 49196.515756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49196.515756 # average overall mshr miss latency +system.cpu.icache.replacements 5199 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 207011 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 207011 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 7122 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7122 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 351779497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351779497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 214133 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 214133 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.033260 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.033260 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 49393.358186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49393.358186 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 1410 # number of ReadReq MSHR hits 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+system.cpu.icache.tags.tagsinuse 486.265530 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 212723 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5712 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37.241422 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 486.265530 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.949737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.949737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 433978 # Number of tag accesses +system.cpu.icache.tags.data_accesses 433978 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 340975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 340975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 341602 # number of overall hits +system.cpu.dcache.overall_hits::total 341602 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 41857 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 41857 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 41863 # number of overall misses +system.cpu.dcache.overall_misses::total 41863 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 2567950314 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2567950314 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 2567950314 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2567950314 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 382832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 382832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 383465 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 383465 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.109335 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109335 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.109170 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109170 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 61350.558186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61350.558186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 61341.765139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61341.765139 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32596 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3937 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 845 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 38 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.575148 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.605263 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 3884 # number of writebacks +system.cpu.dcache.writebacks::total 3884 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 36410 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 36410 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 36410 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 36410 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 5447 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5447 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 5453 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5453 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 370241896 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 370241896 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 370586896 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 370586896 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.014228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.014220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014220 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 67971.708463 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.708463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 67960.186319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67960.186319 # average overall mshr miss latency +system.cpu.dcache.replacements 4943 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 185501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 185501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.057768 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.057768 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 54554.124673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54554.124673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 9065 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 9065 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 91811500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 91811500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.008900 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008900 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 55609.630527 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55609.630527 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 166188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166188 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 30997 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 30997 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 1978714400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1978714400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 197185 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 197185 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 57500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 57500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 2 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 2 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 144 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 144 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4633914 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4633914 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 146 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 146 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.986301 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.986301 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32179.958333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32179.958333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 476.083078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348169 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5455 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.825665 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 476.083078 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 774617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 774617 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 579856000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/a.out b/a.out new file mode 100755 index 000000000..c78282446 Binary files /dev/null and b/a.out differ diff --git a/arm.patch b/arm.patch new file mode 100644 index 000000000..c31ad5661 --- /dev/null +++ b/arm.patch @@ -0,0 +1,273 @@ +diff --git a/configs/spec2k6/spec2k6.py b/configs/spec2k6/spec2k6.py +index 3ce2cf8..3abfecf 100644 +--- a/configs/spec2k6/spec2k6.py ++++ b/configs/spec2k6/spec2k6.py +@@ -53,7 +53,7 @@ output_dir= '/home/min/a/$USER/outputs/spec2k6/' + perlbench = Process() + perlbench_dir = '400.perlbench/' + perlbench.executable = bench_dir+perlbench_dir+\ +- '/exe/perlbench_base.amd64-m64-gcc43-nn' ++ '/exe/perlbench_base.amd64-armcross' + perlbench.cmd = [perlbench.executable] + ['-I./lib', 'attrs.pl'] + perlbench.output = 'attrs.out' + +@@ -61,7 +61,7 @@ perlbench.output = 'attrs.out' + bzip2 = Process() + bzip2_dir = '401.bzip2/' + bzip2.executable = bench_dir+bzip2_dir+\ +- '/exe/bzip2_base.amd64-m64-gcc43-nn' ++ '/exe/bzip2_base.amd64-armcross' + data=bench_dir+bzip2_dir+'data/ref/input/input.source' + bzip2.cmd = [bzip2.executable] + [data, '1'] + bzip2.output = 'input.source.out' +@@ -70,7 +70,7 @@ bzip2.output = 'input.source.out' + gcc = Process() + gcc_dir = '403.gcc/' + gcc.executable = bench_dir+gcc_dir+\ +- '/exe/gcc_base.amd64-m64-gcc43-nn' ++ '/exe/gcc_base.amd64-armcross' + data=bench_dir+'/data/ref/input/166.i' + output=output_dir+'/gcc/166.s' + gcc.cmd = [gcc.executable] + [data]+['-o',output] + ['-quiet'] \ +@@ -81,7 +81,7 @@ gcc.cmd = [gcc.executable] + [data]+['-o',output] + ['-quiet'] \ + + #410.bwaves + bwaves = Process() +-bwaves.executable = bench_dir+'/exe/bwaves_base.amd64-m64-gcc43-nn' ++bwaves.executable = bench_dir+'/exe/bwaves_base.amd64-armcross' + #bwaves.data = bwaves.data + bwaves.cmd = [bwaves.executable] + +@@ -89,7 +89,7 @@ bwaves.cmd = [bwaves.executable] + gamess=Process() + gamess_dir='416.gamess/' + gamess.executable = bench_dir+gamess_dir+\ +- '/exe/gamess_base.amd64-m64-gcc43-nn' ++ '/exe/gamess_base.amd64-armcross' + gamess.cmd = [gamess.executable] + gamess.input='exam29.config' + gamess.output='exam29.output' +@@ -98,7 +98,7 @@ gamess.output='exam29.output' + mcf = Process() + mcf_dir = '429.mcf/' + mcf.executable = bench_dir+mcf_dir+\ +- '/exe/mcf_base.amd64-m64-gcc43-nn' ++ '/exe/mcf_base.amd64-armcross' + data=bench_dir+mcf_dir+'/data/ref/input/inp.in' + mcf.cmd = [mcf.executable] + [data] + mcf.output = 'inp.out' +@@ -107,7 +107,7 @@ mcf.output = 'inp.out' + milc=Process() + milc_dir='433.milc/' + milc.executable = bench_dir+milc_dir+\ +- '/exe/milc_base.amd64-m64-gcc43-nn' ++ '/exe/milc_base.amd64-armcross' + stdin=bench_dir+milc_dir+'/data/ref/input/su3imp.in' + milc.cmd = [milc.executable] + milc.input=stdin +@@ -117,7 +117,7 @@ milc.output='su3imp.out' + zeusmp=Process() + zeusmp_dir='434.zeusmp/' + zeusmp.executable = bench_dir+zeusmp_dir+\ +- '/exe/zeusmp_base.amd64-m64-gcc43-nn' ++ '/exe/zeusmp_base.amd64-armcross' + zeusmp.cmd = [zeusmp.executable] + zeusmp.output = 'zeusmp.stdout' + +@@ -125,7 +125,7 @@ zeusmp.output = 'zeusmp.stdout' + gromacs = Process() + gromacs_dir='435.gromacs/' + gromacs.executable = bench_dir+gromacs_dir+gromacs_dir+\ +- '/exe/gromacs_base.amd64-m64-gcc43-nn' ++ '/exe/gromacs_base.amd64-armcross' + data=bench_dir+gromacs_dir+'/data/ref/input/gromacs.tpr' + gromacs.cmd = [gromacs.executable] + ['-silent','-deffnm',data,'-nice','0'] + +@@ -133,7 +133,7 @@ gromacs.cmd = [gromacs.executable] + ['-silent','-deffnm',data,'-nice','0'] + cactusADM = Process() + cactusADM_dir = '436.cactusADM/' + cactusADM.executable = bench_dir+cactusADM_dir+\ +- '/exe/cactusADM_base.amd64-m64-gcc43-nn' ++ '/exe/cactusADM_base.amd64-armcross' + data=bench_dir+cactusADM_dir+'/data/ref/input/benchADM.par' + cactusADM.cmd = [cactusADM.executable] + [data] + cactusADM.output = 'benchADM.out' +@@ -142,7 +142,7 @@ cactusADM.output = 'benchADM.out' + leslie3d=Process() + leslie3d_dir= '437.leslie3d/' + leslie3d.executable = bench_dir+leslie3d_dir+\ +- '/exe/leslie3d_base.amd64-m64-gcc43-nn' ++ '/exe/leslie3d_base.amd64-armcross' + stdin=bench_dir+leslie3d_dir+'/data/ref/input/leslie3d.in' + leslie3d.cmd = [leslie3d.executable] + leslie3d.input=stdin +@@ -152,7 +152,7 @@ leslie3d.output='leslie3d.stdout' + namd = Process() + namd_dir='444.namd/' + namd.executable = bench_dir+namd_dir+\ +- '/exe/namd_base.amd64-m64-gcc43-nn' ++ '/exe/namd_base.amd64-armcross' + input=bench_dir+namd_dir+'/data/all/input/namd.input' + namd.cmd = [namd.executable] + ['--input',input,'--iterations','1',\ + '--output','namd.out'] +@@ -162,7 +162,7 @@ namd.output='namd.stdout' + gobmk=Process() + gobmk_dir = '445.gobmk/' + gobmk.executable = bench_dir+gobmk_dir+\ +- '/exe/gobmk_base.amd64-m64-gcc43-nn' ++ '/exe/gobmk_base.amd64-armcross' + stdin=bench_dir+gobmk_dir+'/data/ref/input/13x13.tst' + gobmk.cmd = [gobmk.executable]+['--quiet','--mode','gtp'] + gobmk.input=stdin +@@ -172,7 +172,7 @@ gobmk.output='capture.out' + dealII=Process() + dealII_dir = '447.dealII/' + dealII.executable = bench_dir+dealII_dir+\ +- '/exe/dealII_base.amd64-m64-gcc43-nn' ++ '/exe/dealII_base.amd64-armcross' + dealII.cmd = [gobmk.executable]+['8'] + dealII.output='log' + +@@ -180,7 +180,7 @@ dealII.output='log' + soplex=Process() + soplex_dir = '450.soplex/' + soplex.executable = bench_dir+soplex_dir+\ +- '/exe/soplex_base.amd64-m64-gcc43-nn' ++ '/exe/soplex_base.amd64-armcross' + data=bench_dir+soplex_dir+'/data/ref/input/ref.mps' + soplex.cmd = [soplex.executable]+['-m10000',data] + soplex.output = 'test.out' +@@ -189,7 +189,7 @@ soplex.output = 'test.out' + povray=Process() + povray_dir = '453.povray/' + povray.executable = bench_dir+povray_dir+\ +- '/exe/povray_base.amd64-m64-gcc43-nn' ++ '/exe/povray_base.amd64-armcross' + data=bench_dir+povray_dir+'/data/ref/input/SPEC-benchmark-ref.ini' + povray.cmd = [povray.executable]+[data] + povray.output = 'SPEC-benchmark-ref.stdout' +@@ -198,7 +198,7 @@ povray.output = 'SPEC-benchmark-ref.stdout' + calculix=Process() + calculix_dir='454.calculix/' + calculix.executable = bench_dir+calculix_dir+\ +- '/exe/calculix_base.amd64-m64-gcc43-nn' ++ '/exe/calculix_base.amd64-armcross' + data='/data/ref/input/hyperviscoplastic.inp' + calculix.cmd = [calculix.executable]+['-i',data] + calculix.output = 'beampic.log' +@@ -207,7 +207,7 @@ calculix.output = 'beampic.log' + hmmer=Process() + hmmr_dir = '456.hmmr/' + hmmer.executable = bench_dir+hmmr_dir+\ +- '/exe/hmmer_base.amd64-m64-gcc43-nn' ++ '/exe/hmmer_base.amd64-armcross' + data=bench_dir+hmmr_dir+'/data/ref/input/nph3.hmm' + hmmer.cmd = [hmmer.executable]+['--fixed', '0', '--mean', '325',\ + '--num', '5000', '--sd', '200', '--seed', '0', data] +@@ -217,7 +217,7 @@ hmmer.output = 'bombesin.out' + sjeng=Process() + sjeng_dir = '458.sjeng/' + sjeng.executable = bench_dir+sjeng_dir+\ +- '/exe/sjeng_base.amd64-m64-gcc43-nn' ++ '/exe/sjeng_base.amd64-armcross' + data=bench_dir+sjeng_dir+'/data/ref/input/ref.txt' + sjeng.cmd = [sjeng.executable]+[data] + sjeng.output = 'ref.out' +@@ -226,7 +226,7 @@ sjeng.output = 'ref.out' + GemsFDTD=Process() + GemsFDTD_dir = '459.GemsFDTD/' + GemsFDTD.executable = bench_dir+GemsFDTD_dir+\ +- '/exe/GemsFDTD_base.amd64-m64-gcc43-nn' ++ '/exe/GemsFDTD_base.amd64-armcross' + GemsFDTD.cmd = [GemsFDTD.executable] + GemsFDTD.output = 'ref.log' + +@@ -234,7 +234,7 @@ GemsFDTD.output = 'ref.log' + libquantum=Process() + libquantum_dir ='462.libquantum/' + libquantum.executable = bench_dir+libquantum_dir+\ +- '/exe/libquantum_base.amd64-m64-gcc43-nn' ++ '/exe/libquantum_base.amd64-armcross' + libquantum.cmd = [libquantum.executable],'33','5' + libquantum.output = 'ref.out' + +@@ -242,7 +242,7 @@ libquantum.output = 'ref.out' + h264ref=Process() + h264_dir = '464.h264ref/' + h264ref.executable = bench_dir+h264_dir+\ +- '/exe/h264_base.amd64-m64-gcc43-nn' ++ '/exe/h264_base.amd64-armcross' + data=bench_dir+h264_dir+'/data/ref/input/foreman_ref_encoder_baseline.cfg' + h264ref.cmd = [h264ref.executable]+['-d',data] + h264ref.output = 'foreman_ref_encoder_baseline.out' +@@ -250,7 +250,7 @@ h264ref.output = 'foreman_ref_encoder_baseline.out' + #470.lbm + lbm=Process() + lbm_dir='470.lbm/' +-lbm.executable = bench_dir+lbm_dir+'/exe/lbm_base.amd64-m64-gcc43-nn' ++lbm.executable = bench_dir+lbm_dir+'/exe/lbm_base.amd64-armcross' + data=bench_dir+lbm_dir+'/data/ref/input/100_100_130_ldc.of' + lbm.cmd = [lbm.executable]+['20', 'reference.dat', '0', '1' ,data] + lbm.output = 'lbm.out' +@@ -259,7 +259,7 @@ lbm.output = 'lbm.out' + omnetpp=Process() + omnetpp_dir = '471.omnetpp/' + omnetpp.executable = bench_dir+omnetpp_dir+\ +- '/exe/omnetpp_base.amd64-m64-gcc43-nn' ++ '/exe/omnetpp_base.amd64-armcross' + data=bench_dir+omnetpp_dir+'/data/ref/input/omnetpp.ini' + omnetpp.cmd = [omnetpp.executable]+[data] + omnetpp.output = 'omnetpp.log' +@@ -268,7 +268,7 @@ omnetpp.output = 'omnetpp.log' + astar=Process() + astar_dir='473.astar' + astar.executable = bench_dir+astar_dir+\ +- '/exe/astar_base.amd64-m64-gcc43-nn' ++ '/exe/astar_base.amd64-armcross' + data=bench_dir+astar_dir+'/data/ref/input/rivers.cfg' + astar.cmd = [astar.executable]+[data] + astar.output = 'lake.out' +@@ -276,7 +276,7 @@ astar.output = 'lake.out' + #481.wrf + wrf=Process() + wrf_dir = '481.wrf' +-wrf.executable = bench_dir+wrf_dir+'/exe/wrf_base.amd64-m64-gcc43-nn' ++wrf.executable = bench_dir+wrf_dir+'/exe/wrf_base.amd64-armcross' + data = bench_dir+wrf_dir+'/data/ref/input/namelist.input' + wrf.cmd = [wrf.executable]+[data] + wrf.output = 'rsl.out.0000' +@@ -285,7 +285,7 @@ wrf.output = 'rsl.out.0000' + sphinx3=Process() + sphinx3_dir = '482.sphinx/' + sphinx3.executable = bench_dir+sphinx3_dir+\ +- '/exe/sphinx_base.amd64-m64-gcc43-nn' ++ '/exe/sphinx_base.amd64-armcross' + sphinx3.cmd = [sphinx3.executable]+['ctlfile', '.', 'args.an4'] + sphinx3.output = 'an4.out' + +@@ -293,7 +293,7 @@ sphinx3.output = 'an4.out' + xalancbmk=Process() + xalanch_dir = '483.xalancbmk/' + xalancbmk.executable = bench_dir+xalanch_dir+\ +- '/exe/Xalan_base.amd64-m64-gcc43-nn' ++ '/exe/Xalan_base.amd64-armcross' + data = bench_dir + xalanch_dir + '/data/ref/input/' + xalancbmk.cmd = [xalancbmk.executable]+['-v',data+'t5.xml',data+'xalanc.xsl'] + xalancbmk.output = 'ref.out' +@@ -302,7 +302,7 @@ xalancbmk.output = 'ref.out' + specrand_i=Process() + specrand_i_dir = '998.specrand/' + specrand_i.executable = bench_dir+specrand_i_dir+\ +- '/exe/specrand_i_base.amd64-m64-gcc43-nn' ++ '/exe/specrand_i_base.amd64-armcross' + specrand_i.cmd = [specrand_i.executable] + ['324342','24239'] + specrand_i.output = 'rand.24239.out' + +@@ -310,6 +310,6 @@ specrand_i.output = 'rand.24239.out' + specrand_f=Process() + specrand_f_dir = '999.specrand/' + specrand_f.executable = bench_dir+specrand_f_dir+\ +- '/exe/specrand_f_base.amd64-m64-gcc43-nn' ++ '/exe/specrand_f_base.amd64-armcross' + specrand_f.cmd = [specrand_f.executable] + ['324342','24239'] + specrand_f.output = 'rand.24239.out' diff --git a/arm_gcc.sh b/arm_gcc.sh new file mode 100755 index 000000000..8397d5c61 --- /dev/null +++ b/arm_gcc.sh @@ -0,0 +1,2 @@ +#!/bin/sh +/usr/bin/arm-linux-gnueabi-gcc -O0 -static $1 diff --git a/benchmarks.sh b/benchmarks.sh new file mode 100644 index 000000000..d7917848a --- /dev/null +++ b/benchmarks.sh @@ -0,0 +1,17 @@ +./build/ARM/gem5.opt -d zeusmp configs/spec2k6/run.py -b zeusmp --maxinsts=200000000 --cpu-type=DerivO3CPU --caches --l2cache --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=8 --l1d_size=32kB --l1i_size=32kB --l2_size=2MB + +./build/ARM/gem5.opt -d tsl_tage/hmmer configs/spec2k6/run.py -b hmmer\ + --maxinsts=200000000 --cpu-type=DerivO3CPU --caches --l2cache --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=8\ + --l1d_size=64kB --l1i_size=64kB --l2_size=4MB + + + dealII + gamess + gromacs + perlbench + soplex + specrand_f + specrand_i + sphinx3 + tonto + zeusmp \ No newline at end of file diff --git a/branch.txt b/branch.txt new file mode 100644 index 000000000..3d805ed3c --- /dev/null +++ b/branch.txt @@ -0,0 +1,8 @@ +warn: CheckedInt already exists in allParams. This may be caused by the Python 2.7 compatibility layer. +warn: Enum already exists in allParams. This may be caused by the Python 2.7 compatibility layer. +warn: ScopedEnum already exists in allParams. This may be caused by the Python 2.7 compatibility layer. +warn: No dot file generated. Please install pydot to generate the dot file and pdf. +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +0: system.remote_gdb: listening for remote gdb on port 7000 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/bwaves.in b/bwaves.in new file mode 100644 index 000000000..e69de29bb diff --git a/bwaves.out b/bwaves.out new file mode 100644 index 000000000..e69de29bb diff --git a/bwaves2.out b/bwaves2.out new file mode 100644 index 000000000..e69de29bb diff --git a/bwaves3.out b/bwaves3.out new file mode 100644 index 000000000..e69de29bb diff --git a/bzip2/config.ini b/bzip2/config.ini new file mode 100644 index 000000000..92370079f --- /dev/null +++ b/bzip2/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2/data/ref/input/input.source 1 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=input.source.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=bzip2/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=bzip2/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=bzip2/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/bzip2/config.json b/bzip2/config.json new file mode 100644 index 000000000..997afafbf --- /dev/null +++ b/bzip2/config.json @@ -0,0 +1,1687 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": 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"path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/bzip2/fs/proc/cpuinfo b/bzip2/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/bzip2/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/bzip2/fs/proc/stat b/bzip2/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/bzip2/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/bzip2/fs/sys/devices/system/cpu/online b/bzip2/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/bzip2/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/bzip2/fs/sys/devices/system/cpu/possible b/bzip2/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/bzip2/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/bzip2/input.source.out b/bzip2/input.source.out new file mode 100644 index 000000000..e69de29bb diff --git a/bzip2/stats.txt b/bzip2/stats.txt new file mode 100644 index 000000000..504b34b82 --- /dev/null +++ b/bzip2/stats.txt @@ -0,0 +1,1313 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 264828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 107544 # Simulator instruction rate (inst/s) +host_mem_usage 848784 # Number of bytes of host memory used +host_op_rate 113641 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.65 # Real time elapsed on the host +host_tick_rate 56957854 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500007 # Number of instructions simulated +sim_ops 528374 # Number of ops (including micro ops) simulated +sim_seconds 0.000265 # Number of seconds simulated +sim_ticks 264828500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.844789 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 76580 # Number of BTB hits +system.cpu.branchPred.BTBLookups 77475 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1370 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 102563 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 196 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 188 # Number of indirect misses. +system.cpu.branchPred.lookups 127181 # Number of BP lookups +system.cpu.branchPred.usedRAS 790 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 54 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 203385 # number of cc regfile reads +system.cpu.cc_regfile_writes 203553 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 1143 # The number of times a branch was mispredicted +system.cpu.commit.branches 85775 # Number of branches committed +system.cpu.commit.bw_lim_events 42632 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 150246 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500277 # Number of instructions committed +system.cpu.commit.committedOps 528644 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 467712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.130277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.412345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 326918 69.90% 69.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60449 12.92% 82.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17052 3.65% 86.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7808 1.67% 88.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2728 0.58% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5227 1.12% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1722 0.37% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3176 0.68% 90.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 42632 9.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 467712 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 452 # Number of function calls committed. +system.cpu.commit.int_insts 465265 # Number of committed integer instructions. +system.cpu.commit.loads 186291 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 9 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 257589 48.73% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 21 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 29 0.01% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 34 0.01% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 36 0.01% 48.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 48.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 26 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 186291 35.24% 84.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 84606 16.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 528644 # Class of committed instruction +system.cpu.commit.refs 270897 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 224 # Number of committed Vector instructions. +system.cpu.committedInsts 500007 # Number of Instructions Simulated +system.cpu.committedOps 528374 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.059301 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.059301 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 294139 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 229 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 68725 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 697016 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 65018 # Number of cycles decode is idle +system.cpu.decode.RunCycles 102397 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1986 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 801 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 23828 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 127181 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 79708 # Number of cache lines fetched +system.cpu.fetch.Cycles 393179 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 689 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 712438 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4426 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.240119 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 91940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 77378 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.345091 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 487368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.527845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.667720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 321694 66.01% 66.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 46469 9.53% 75.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10585 2.17% 77.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2587 0.53% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13610 2.79% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 37815 7.76% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1665 0.34% 89.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7826 1.61% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 45117 9.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 487368 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42290 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1297 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 113361 # Number of branches executed +system.cpu.iew.exec_nop 351 # number of nop insts executed +system.cpu.iew.exec_rate 1.398704 # Inst execution rate +system.cpu.iew.exec_refs 398318 # number of memory reference insts executed +system.cpu.iew.exec_stores 112078 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 32637 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 219108 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 265 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 114800 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 682609 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 286240 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 740835 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 19356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1986 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 18817 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2103 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 55156 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 27236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 32807 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 30192 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 947 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 350 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 724833 # num instructions consuming a value +system.cpu.iew.wb_count 644538 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.575784 # average fanout of values written-back +system.cpu.iew.wb_producers 417347 # num instructions producing a value +system.cpu.iew.wb_rate 1.216895 # insts written-back per cycle +system.cpu.iew.wb_sent 670087 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 911523 # number of integer regfile reads +system.cpu.int_regfile_writes 467973 # number of integer regfile writes +system.cpu.ipc 0.944019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944019 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 343011 46.20% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 24 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 5 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 38 0.01% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 40 0.01% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 28 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 286935 38.64% 84.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 112390 15.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 742516 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 18679 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025156 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 750 4.02% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 4.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.02% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 4.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 16735 89.59% 93.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1189 6.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 760891 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1990687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 644284 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 835657 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 682178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 742516 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 80 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 153859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 210 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 94475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 487368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.523522 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.982630 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251394 51.58% 51.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43213 8.87% 60.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60712 12.46% 72.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 38203 7.84% 80.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47079 9.66% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 22653 4.65% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11282 2.31% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8659 1.78% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4173 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 487368 # Number of insts issued each cycle +system.cpu.iq.rate 1.401878 # Inst issue rate +system.cpu.iq.vec_alu_accesses 294 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 602 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 254 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 510 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 45471 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30354 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 219108 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 114800 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 573590 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 529658 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 74721 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 506606 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 11861 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 76374 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 37864 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1346 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1052064 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 691222 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 692034 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 113599 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 155788 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1986 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 210928 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 185385 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 840154 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 213 # count of serializing insts renamed +system.cpu.rename.skidInsts 140092 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 502 # Number of vector rename lookups +system.cpu.rob.rob_reads 1093557 # The number of ROB reads +system.cpu.rob.rob_writes 1377479 # The number of ROB writes +system.cpu.timesIdled 372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 336 # number of vector regfile reads +system.cpu.vec_regfile_writes 167 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1137 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6404 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4482 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 16 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 9852 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 16 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1869 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1129 # Transaction distribution +system.membus.trans_dist::CleanEvict 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 3391 # Transaction distribution +system.membus.trans_dist::ReadExResp 3391 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1869 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 11664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 408896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 408896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 5267 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5267 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5267 # Request fanout histogram +system.membus.reqLayer0.occupancy 11668500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 27141250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1940 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4381 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 140 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1114 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3422 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3422 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 516 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1424 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 8 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 8 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1172 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 14050 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 15222 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 41984 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 518272 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 560256 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1153 # Total snoops (count) +system.tol2bus.snoopTraffic 72256 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6523 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002606 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.050988 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6506 99.74% 99.74% # Request fanout histogram +system.tol2bus.snoop_fanout::1 17 0.26% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6523 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8318000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 7273000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 774000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 9 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 93 # number of demand (read+write) hits +system.l2.demand_hits::total 102 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 9 # number of overall hits +system.l2.overall_hits::.cpu.data 93 # number of overall hits +system.l2.overall_hits::total 102 # number of overall hits +system.l2.demand_misses::.cpu.inst 507 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4753 # number of demand (read+write) misses +system.l2.demand_misses::total 5260 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 507 # number of overall misses +system.l2.overall_misses::.cpu.data 4753 # number of overall misses +system.l2.overall_misses::total 5260 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40497000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 421018000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 461515000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40497000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 421018000 # number of overall miss cycles +system.l2.overall_miss_latency::total 461515000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 516 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 4846 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5362 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 516 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 4846 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5362 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.982558 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.980809 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.980977 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.982558 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.980809 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.980977 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79875.739645 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 88579.423522 # average overall miss latency +system.l2.demand_avg_miss_latency::total 87740.494297 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79875.739645 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 88579.423522 # average overall miss latency +system.l2.overall_avg_miss_latency::total 87740.494297 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1129 # number of writebacks +system.l2.writebacks::total 1129 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 507 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4753 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 5260 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 507 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4753 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 5260 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35427000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 373488000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 408915000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35427000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 373488000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 408915000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.982558 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.980809 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.980977 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.982558 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.980809 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.980977 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69875.739645 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 78579.423522 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 77740.494297 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69875.739645 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 78579.423522 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 77740.494297 # average overall mshr miss latency +system.l2.replacements 1153 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3252 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3252 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3252 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3252 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 140 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 140 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 140 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 140 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 31 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 31 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3391 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3391 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 312287000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 312287000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3422 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3422 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990941 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990941 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 92092.892952 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 92092.892952 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3391 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3391 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 278377000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 278377000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990941 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990941 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 82092.892952 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 82092.892952 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 507 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 507 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40497000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40497000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 516 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 516 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.982558 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.982558 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79875.739645 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79875.739645 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 507 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 507 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35427000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35427000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.982558 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.982558 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69875.739645 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69875.739645 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 62 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 62 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1362 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1362 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 108731000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 108731000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1424 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1424 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.956461 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.956461 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 79831.864905 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 79831.864905 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1362 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1362 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 95111000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 95111000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.956461 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.956461 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69831.864905 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69831.864905 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2776.204819 # Cycle average of tags in use +system.l2.tags.total_refs 9844 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 5272 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.867223 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 5.313210 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 395.023561 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2375.868048 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000162 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.012055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.072506 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.084723 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4118 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 3842 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.125671 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 84080 # Number of tag accesses +system.l2.tags.data_accesses 84080 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32448 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 304192 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 336640 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 72256 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 72256 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 507 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4753 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 5260 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1129 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1129 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 122524577 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1148637703 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1271162280 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 122524577 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 122524577 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 272840725 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 272840725 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 272840725 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 122524577 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1148637703 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1544003006 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1129.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 507.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4753.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000133882500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 69 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 69 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 10737 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 1048 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 5260 # Number of read requests accepted +system.mem_ctrls.writeReqs 1129 # Number of write requests accepted +system.mem_ctrls.readBursts 5260 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1129 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 329 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 356 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 290 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 353 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 364 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 361 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 272 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 285 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 65 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 70 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 64 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.39 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 17.81 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 92275250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 26300000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 190900250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 17542.82 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 36292.82 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4519 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 936 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 85.91 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 5260 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1129 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1699 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1405 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1171 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 969 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 124 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 135 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 72 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 911 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 447.227223 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 380.768471 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 191.376184 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 8.56% 8.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 81 8.89% 17.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45 4.94% 22.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 35 3.84% 26.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 625 68.61% 94.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 0.88% 95.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 12 1.32% 97.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.22% 97.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 2.74% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 911 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 69 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 72.666667 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 21.184138 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.876024 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 64 92.75% 92.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-255 1 1.45% 94.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::256-383 3 4.35% 98.55% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2560-2687 1 1.45% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 69 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 69 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.028986 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.027335 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.240772 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 68 98.55% 98.55% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 1.45% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 69 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 336640 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 70784 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 336640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 72256 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1271.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 267.28 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1271.16 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 272.84 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 12.02 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 9.93 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 2.09 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 264491000 # Total gap between requests +system.mem_ctrls.avgGap 41397.87 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32448 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 304192 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 70784 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 122524577.226393684745 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1148637703.268341541290 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 267282411.069805562496 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 507 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4753 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1129 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14556750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 176343500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 2527843500 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28711.54 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 37101.51 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 2239011.07 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 85.38 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2870280 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1525590 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 17885700 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 2834460 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 113197440 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 6432960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 165644190 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 625.477205 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 15823000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8662250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 240343250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3634260 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1931655 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 19670700 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 2938860 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 76906680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 36993600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 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time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 79023 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 79023 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 79023 # number of overall hits +system.cpu.icache.overall_hits::total 79023 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 685 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 685 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 685 # number of overall misses +system.cpu.icache.overall_misses::total 685 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 53422999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53422999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 53422999 # number of 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# average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 79678 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 79678 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 4881 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4881 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 405258320 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 405258320 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 84559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 84559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.057723 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.057723 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 83027.723827 # average WriteReq miss latency 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+system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 47 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 47 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.042553 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.042553 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 351.579959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 243895 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4854 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.246189 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 351.579959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.686680 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.686680 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 497438 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 497438 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 264828500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 264828500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/configs/spec2k6/spec2k6.py b/configs/spec2k6/spec2k6.py index 3abfecf52..b4de1a9f3 100644 --- a/configs/spec2k6/spec2k6.py +++ b/configs/spec2k6/spec2k6.py @@ -49,11 +49,18 @@ ### that require read/write to an output directory output_dir= '/home/min/a/$USER/outputs/spec2k6/' +if buildEnv['TARGET_ISA'] == 'arm': + benchtype = "-armcross" +elif buildEnv['TARGET_ISA'] == 'x86': + benchtype = '-m64-gcc43-nn' +else: + sys.exit("Unsupported ISA") + #400.perlbench perlbench = Process() perlbench_dir = '400.perlbench/' perlbench.executable = bench_dir+perlbench_dir+\ - '/exe/perlbench_base.amd64-armcross' + '/exe/perlbench_base.amd64' + benchtype perlbench.cmd = [perlbench.executable] + ['-I./lib', 'attrs.pl'] perlbench.output = 'attrs.out' @@ -61,7 +68,7 @@ bzip2 = Process() bzip2_dir = '401.bzip2/' bzip2.executable = bench_dir+bzip2_dir+\ - '/exe/bzip2_base.amd64-armcross' + '/exe/bzip2_base.amd64' + benchtype data=bench_dir+bzip2_dir+'data/ref/input/input.source' bzip2.cmd = [bzip2.executable] + [data, '1'] bzip2.output = 'input.source.out' @@ -70,7 +77,7 @@ gcc = Process() gcc_dir = '403.gcc/' gcc.executable = bench_dir+gcc_dir+\ - '/exe/gcc_base.amd64-armcross' + '/exe/gcc_base.amd64' + benchtype data=bench_dir+'/data/ref/input/166.i' output=output_dir+'/gcc/166.s' gcc.cmd = [gcc.executable] + [data]+['-o',output] + ['-quiet'] \ @@ -81,24 +88,25 @@ #410.bwaves bwaves = Process() -bwaves.executable = bench_dir+'/exe/bwaves_base.amd64-armcross' -#bwaves.data = bwaves.data +bwaves_dir=bench_dir+'/410.bwaves' +bwaves.executable = bwaves_dir+'/run/bwaves_base.amd64' + benchtype +bwaves.cwd = bwaves_dir+'/run/' bwaves.cmd = [bwaves.executable] #416.gamess gamess=Process() gamess_dir='416.gamess/' gamess.executable = bench_dir+gamess_dir+\ - '/exe/gamess_base.amd64-armcross' -gamess.cmd = [gamess.executable] -gamess.input='exam29.config' -gamess.output='exam29.output' + '/run/gamess_base.amd64' + benchtype +gamess.cmd = [gamess.executable] + ['cytosine.2.config'] +gamess.cwd = bench_dir+gamess_dir+'/run' +gamess.output='cytosine.2.output' #429.mcf mcf = Process() mcf_dir = '429.mcf/' mcf.executable = bench_dir+mcf_dir+\ - '/exe/mcf_base.amd64-armcross' + '/exe/mcf_base.amd64' + benchtype data=bench_dir+mcf_dir+'/data/ref/input/inp.in' mcf.cmd = [mcf.executable] + [data] mcf.output = 'inp.out' @@ -107,7 +115,7 @@ milc=Process() milc_dir='433.milc/' milc.executable = bench_dir+milc_dir+\ - '/exe/milc_base.amd64-armcross' + '/exe/milc_base.amd64' + benchtype stdin=bench_dir+milc_dir+'/data/ref/input/su3imp.in' milc.cmd = [milc.executable] milc.input=stdin @@ -117,15 +125,16 @@ zeusmp=Process() zeusmp_dir='434.zeusmp/' zeusmp.executable = bench_dir+zeusmp_dir+\ - '/exe/zeusmp_base.amd64-armcross' + '/run/zeusmp_base.amd64' + benchtype zeusmp.cmd = [zeusmp.executable] +zeusmp.cwd = zeusmp_dir+'/run' zeusmp.output = 'zeusmp.stdout' #435.gromacs gromacs = Process() gromacs_dir='435.gromacs/' gromacs.executable = bench_dir+gromacs_dir+gromacs_dir+\ - '/exe/gromacs_base.amd64-armcross' + '/exe/gromacs_base.amd64' + benchtype data=bench_dir+gromacs_dir+'/data/ref/input/gromacs.tpr' gromacs.cmd = [gromacs.executable] + ['-silent','-deffnm',data,'-nice','0'] @@ -133,7 +142,7 @@ cactusADM = Process() cactusADM_dir = '436.cactusADM/' cactusADM.executable = bench_dir+cactusADM_dir+\ - '/exe/cactusADM_base.amd64-armcross' + '/exe/cactusADM_base.amd64' + benchtype data=bench_dir+cactusADM_dir+'/data/ref/input/benchADM.par' cactusADM.cmd = [cactusADM.executable] + [data] cactusADM.output = 'benchADM.out' @@ -142,7 +151,7 @@ leslie3d=Process() leslie3d_dir= '437.leslie3d/' leslie3d.executable = bench_dir+leslie3d_dir+\ - '/exe/leslie3d_base.amd64-armcross' + '/exe/leslie3d_base.amd64' + benchtype stdin=bench_dir+leslie3d_dir+'/data/ref/input/leslie3d.in' leslie3d.cmd = [leslie3d.executable] leslie3d.input=stdin @@ -152,7 +161,7 @@ namd = Process() namd_dir='444.namd/' namd.executable = bench_dir+namd_dir+\ - '/exe/namd_base.amd64-armcross' + '/exe/namd_base.amd64' + benchtype input=bench_dir+namd_dir+'/data/all/input/namd.input' namd.cmd = [namd.executable] + ['--input',input,'--iterations','1',\ '--output','namd.out'] @@ -162,7 +171,7 @@ gobmk=Process() gobmk_dir = '445.gobmk/' gobmk.executable = bench_dir+gobmk_dir+\ - '/exe/gobmk_base.amd64-armcross' + '/exe/gobmk_base.amd64' + benchtype stdin=bench_dir+gobmk_dir+'/data/ref/input/13x13.tst' gobmk.cmd = [gobmk.executable]+['--quiet','--mode','gtp'] gobmk.input=stdin @@ -172,7 +181,7 @@ dealII=Process() dealII_dir = '447.dealII/' dealII.executable = bench_dir+dealII_dir+\ - '/exe/dealII_base.amd64-armcross' + '/exe/dealII_base.amd64' + benchtype dealII.cmd = [gobmk.executable]+['8'] dealII.output='log' @@ -180,7 +189,7 @@ soplex=Process() soplex_dir = '450.soplex/' soplex.executable = bench_dir+soplex_dir+\ - '/exe/soplex_base.amd64-armcross' + '/exe/soplex_base.amd64' + benchtype data=bench_dir+soplex_dir+'/data/ref/input/ref.mps' soplex.cmd = [soplex.executable]+['-m10000',data] soplex.output = 'test.out' @@ -189,7 +198,7 @@ povray=Process() povray_dir = '453.povray/' povray.executable = bench_dir+povray_dir+\ - '/exe/povray_base.amd64-armcross' + '/exe/povray_base.amd64' + benchtype data=bench_dir+povray_dir+'/data/ref/input/SPEC-benchmark-ref.ini' povray.cmd = [povray.executable]+[data] povray.output = 'SPEC-benchmark-ref.stdout' @@ -198,16 +207,16 @@ calculix=Process() calculix_dir='454.calculix/' calculix.executable = bench_dir+calculix_dir+\ - '/exe/calculix_base.amd64-armcross' + '/exe/calculix_base.amd64' + benchtype data='/data/ref/input/hyperviscoplastic.inp' calculix.cmd = [calculix.executable]+['-i',data] calculix.output = 'beampic.log' #456.hmmer hmmer=Process() -hmmr_dir = '456.hmmr/' +hmmr_dir = '456.hmmer/' hmmer.executable = bench_dir+hmmr_dir+\ - '/exe/hmmer_base.amd64-armcross' + '/exe/hmmer_base.amd64' + benchtype data=bench_dir+hmmr_dir+'/data/ref/input/nph3.hmm' hmmer.cmd = [hmmer.executable]+['--fixed', '0', '--mean', '325',\ '--num', '5000', '--sd', '200', '--seed', '0', data] @@ -217,7 +226,7 @@ sjeng=Process() sjeng_dir = '458.sjeng/' sjeng.executable = bench_dir+sjeng_dir+\ - '/exe/sjeng_base.amd64-armcross' + '/exe/sjeng_base.amd64' + benchtype data=bench_dir+sjeng_dir+'/data/ref/input/ref.txt' sjeng.cmd = [sjeng.executable]+[data] sjeng.output = 'ref.out' @@ -226,7 +235,7 @@ GemsFDTD=Process() GemsFDTD_dir = '459.GemsFDTD/' GemsFDTD.executable = bench_dir+GemsFDTD_dir+\ - '/exe/GemsFDTD_base.amd64-armcross' + '/exe/GemsFDTD_base.amd64' + benchtype GemsFDTD.cmd = [GemsFDTD.executable] GemsFDTD.output = 'ref.log' @@ -234,7 +243,7 @@ libquantum=Process() libquantum_dir ='462.libquantum/' libquantum.executable = bench_dir+libquantum_dir+\ - '/exe/libquantum_base.amd64-armcross' + '/exe/libquantum_base.amd64' + benchtype libquantum.cmd = [libquantum.executable],'33','5' libquantum.output = 'ref.out' @@ -242,15 +251,16 @@ h264ref=Process() h264_dir = '464.h264ref/' h264ref.executable = bench_dir+h264_dir+\ - '/exe/h264_base.amd64-armcross' + '/run/h264ref_base.amd64' + benchtype data=bench_dir+h264_dir+'/data/ref/input/foreman_ref_encoder_baseline.cfg' h264ref.cmd = [h264ref.executable]+['-d',data] +h264ref.cwd = bench_dir+h264_dir+'/run' h264ref.output = 'foreman_ref_encoder_baseline.out' #470.lbm lbm=Process() lbm_dir='470.lbm/' -lbm.executable = bench_dir+lbm_dir+'/exe/lbm_base.amd64-armcross' +lbm.executable = bench_dir+lbm_dir+'/exe/lbm_base.amd64' + benchtype data=bench_dir+lbm_dir+'/data/ref/input/100_100_130_ldc.of' lbm.cmd = [lbm.executable]+['20', 'reference.dat', '0', '1' ,data] lbm.output = 'lbm.out' @@ -259,7 +269,7 @@ omnetpp=Process() omnetpp_dir = '471.omnetpp/' omnetpp.executable = bench_dir+omnetpp_dir+\ - '/exe/omnetpp_base.amd64-armcross' + '/exe/omnetpp_base.amd64' + benchtype data=bench_dir+omnetpp_dir+'/data/ref/input/omnetpp.ini' omnetpp.cmd = [omnetpp.executable]+[data] omnetpp.output = 'omnetpp.log' @@ -268,32 +278,34 @@ astar=Process() astar_dir='473.astar' astar.executable = bench_dir+astar_dir+\ - '/exe/astar_base.amd64-armcross' + '/run/astar_base.amd64' + benchtype data=bench_dir+astar_dir+'/data/ref/input/rivers.cfg' astar.cmd = [astar.executable]+[data] +astar.cwd = bench_dir+astar_dir+'/run' astar.output = 'lake.out' #481.wrf wrf=Process() wrf_dir = '481.wrf' -wrf.executable = bench_dir+wrf_dir+'/exe/wrf_base.amd64-armcross' +wrf.executable = bench_dir+wrf_dir+'/exe/wrf_base.amd64' + benchtype data = bench_dir+wrf_dir+'/data/ref/input/namelist.input' wrf.cmd = [wrf.executable]+[data] wrf.output = 'rsl.out.0000' #482.sphinx sphinx3=Process() -sphinx3_dir = '482.sphinx/' +sphinx3_dir = '482.sphinx3' sphinx3.executable = bench_dir+sphinx3_dir+\ - '/exe/sphinx_base.amd64-armcross' + '/run/sphinx_livepretend_base.amd64' + benchtype sphinx3.cmd = [sphinx3.executable]+['ctlfile', '.', 'args.an4'] +sphinx3.cwd = bench_dir+sphinx3_dir + '/run/' sphinx3.output = 'an4.out' #483.xalancbmk xalancbmk=Process() xalanch_dir = '483.xalancbmk/' xalancbmk.executable = bench_dir+xalanch_dir+\ - '/exe/Xalan_base.amd64-armcross' + '/exe/Xalan_base.amd64' + benchtype data = bench_dir + xalanch_dir + '/data/ref/input/' xalancbmk.cmd = [xalancbmk.executable]+['-v',data+'t5.xml',data+'xalanc.xsl'] xalancbmk.output = 'ref.out' @@ -302,7 +314,7 @@ specrand_i=Process() specrand_i_dir = '998.specrand/' specrand_i.executable = bench_dir+specrand_i_dir+\ - '/exe/specrand_i_base.amd64-armcross' + '/exe/specrand_i_base.amd64' + benchtype specrand_i.cmd = [specrand_i.executable] + ['324342','24239'] specrand_i.output = 'rand.24239.out' @@ -310,6 +322,6 @@ specrand_f=Process() specrand_f_dir = '999.specrand/' specrand_f.executable = bench_dir+specrand_f_dir+\ - '/exe/specrand_f_base.amd64-armcross' + '/exe/specrand_f_base.amd64' + benchtype specrand_f.cmd = [specrand_f.executable] + ['324342','24239'] -specrand_f.output = 'rand.24239.out' +specrand_f.output = 'rand.24239.out' \ No newline at end of file diff --git a/microresults/vector_loop/config.ini b/microresults/vector_loop/config.ini new file mode 100644 index 000000000..515ea51e9 --- /dev/null +++ b/microresults/vector_loop/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=3 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=65536 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=65536 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=65536 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 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+pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 system.cpu.fuPool.FUList5.opList23 system.cpu.fuPool.FUList5.opList24 system.cpu.fuPool.FUList5.opList25 + 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+pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +eventq_index=0 +opClass=SimdPredAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList0 system.cpu.fuPool.FUList8.opList1 system.cpu.fuPool.FUList8.opList2 system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=16384 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=16384 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=16384 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=a.out +cwd=/home/ben/ECE565/tage_scl +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=a.out +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= 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+[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=microresults/vector_loop/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/microresults/vector_loop/config.json b/microresults/vector_loop/config.json new file mode 100644 index 000000000..71df6a8a6 --- /dev/null +++ b/microresults/vector_loop/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + 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"clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/microresults/vector_loop/fs/proc/cpuinfo b/microresults/vector_loop/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/microresults/vector_loop/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/microresults/vector_loop/fs/proc/stat b/microresults/vector_loop/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/microresults/vector_loop/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/microresults/vector_loop/fs/sys/devices/system/cpu/online b/microresults/vector_loop/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/microresults/vector_loop/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/microresults/vector_loop/fs/sys/devices/system/cpu/possible b/microresults/vector_loop/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/microresults/vector_loop/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/microresults/vector_loop/stats.txt b/microresults/vector_loop/stats.txt new file mode 100644 index 000000000..24da9f6af --- /dev/null +++ b/microresults/vector_loop/stats.txt @@ -0,0 +1,1294 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2585854500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 179372 # Simulator instruction rate (inst/s) +host_mem_usage 715648 # Number of bytes of host memory used +host_op_rate 179417 # Simulator op (including micro ops) rate (op/s) +host_seconds 23.83 # Real time elapsed on the host +host_tick_rate 108498982 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4274925 # Number of instructions simulated +sim_ops 4276047 # Number of ops (including micro ops) simulated +sim_seconds 0.002586 # Number of seconds simulated +sim_ticks 2585854500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.574760 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 106075 # Number of BTB hits +system.cpu.branchPred.BTBLookups 106528 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 27 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 11941 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 132561 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 16 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 238 # Number of indirect misses. +system.cpu.branchPred.lookups 136976 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 75982 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 26970 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 17909 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 85043 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 20 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 13 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 2331 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1317 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 68 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2107 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 9 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 4897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2930 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2777 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 7660 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 8843 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 2838 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 9042 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 950 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1121 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 992 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 347 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2014 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 4673 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 19711 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 290 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 3576 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 304 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 22537 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 210 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1316 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 2328 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2168 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 796 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2269 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1906 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2868 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 7666 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 2771 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 7052 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 29 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 10411 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 4181 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1124 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 96 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 332 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2564 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 24742 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 66992 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 174 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 7046 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 71 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 17426221 # number of cc regfile reads +system.cpu.cc_regfile_writes 316440 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 11781 # The number of times a branch was mispredicted +system.cpu.commit.branches 104289 # Number of branches committed +system.cpu.commit.bw_lim_events 40181 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 812487 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 4274925 # Number of instructions committed +system.cpu.commit.committedOps 4276047 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 5042724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.847964 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.888683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1269697 25.18% 25.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3667949 72.74% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13110 0.26% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 387 0.01% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 295 0.01% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 49770 0.99% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.00% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1229 0.02% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 40181 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5042724 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 123 # Number of function calls committed. +system.cpu.commit.int_insts 4172071 # Number of committed integer instructions. +system.cpu.commit.loads 1374349 # Number of loads committed +system.cpu.commit.membars 14 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1680267 39.29% 39.29% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 50003 1.17% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 40.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1374349 32.14% 72.60% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1171428 27.40% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 4276047 # Class of committed instruction +system.cpu.commit.refs 2545777 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 0 # Number of committed Vector instructions. +system.cpu.committedInsts 4274925 # Number of Instructions Simulated +system.cpu.committedOps 4276047 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.209778 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.209778 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 4248863 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 92122 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 5211346 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 216086 # Number of cycles decode is idle +system.cpu.decode.RunCycles 137747 # Number of cycles decode is running +system.cpu.decode.SquashCycles 12396 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 624 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 534225 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 136976 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 476237 # Number of cache lines fetched +system.cpu.fetch.Cycles 4642665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 660 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 5654909 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 16 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 25116 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.026486 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 494062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 106342 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.093431 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 5149317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.098648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.467087 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 4082940 79.29% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 113472 2.20% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95346 1.85% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 169712 3.30% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 77749 1.51% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 57493 1.12% 89.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 58091 1.13% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 59132 1.15% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 435382 8.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 5149317 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 22393 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 12242 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 108007 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 0.849151 # Inst execution rate +system.cpu.iew.exec_refs 2615420 # number of memory reference insts executed +system.cpu.iew.exec_stores 1196990 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 96065 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1647566 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1429576 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 5088512 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1418430 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12762 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 4391565 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 12396 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 117 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1196275 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 806 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 103 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 273217 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 258148 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 806 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 8553 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3689 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 3439927 # num instructions consuming a value +system.cpu.iew.wb_count 4389180 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.895349 # average fanout of values written-back +system.cpu.iew.wb_producers 3079935 # num instructions producing a value +system.cpu.iew.wb_rate 0.848690 # insts written-back per cycle +system.cpu.iew.wb_sent 4390394 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 5683271 # number of integer regfile reads +system.cpu.int_regfile_writes 3031205 # number of integer regfile writes +system.cpu.ipc 0.826598 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.826598 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1725751 39.18% 39.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 50650 1.15% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 40.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1419824 32.24% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1208100 27.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 4404327 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 427 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.000097 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 2.11% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 2.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 335 78.45% 80.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83 19.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 4404752 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 13958461 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 4389180 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 5901681 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 5088467 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 4404327 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 812464 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3497640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 5149317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.855323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.651502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1287166 25.00% 25.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3486326 67.70% 92.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 268508 5.21% 97.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51777 1.01% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 53965 1.05% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 649 0.01% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 189 0.00% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 256 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 5149317 # Number of insts issued each cycle +system.cpu.iq.rate 0.851619 # Inst issue rate +system.cpu.iq.vec_alu_accesses 0 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 0 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 0 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 0 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1576713 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1189782 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1647566 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1429576 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 5705979 # number of misc regfile reads +system.cpu.misc_regfile_writes 57 # number of misc regfile writes +system.cpu.numCycles 5171710 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 2161696 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 3257288 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2090313 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 286561 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 6113 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 25217869 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 5131113 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 3852384 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 589164 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1923 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 12396 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2098202 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 595096 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 6718702 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 1298 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.skidInsts 3277533 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 16 # Number of vector rename lookups +system.cpu.rob.rob_reads 10090947 # The number of ROB reads +system.cpu.rob.rob_writes 10283695 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 16 # number of vector regfile reads +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 459 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 165 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 662 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 403 # Transaction distribution +system.membus.trans_dist::ReadExReq 56 # Transaction distribution +system.membus.trans_dist::ReadExResp 56 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 403 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 918 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 29376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 29376 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 459 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 459 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 459 # Request fanout histogram +system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2421750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 473 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 132 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 56 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 56 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 354 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 120 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 839 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 352 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 1191 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 42304 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 530 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.083019 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.276171 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 486 91.70% 91.70% # Request fanout histogram +system.tol2bus.snoop_fanout::1 44 8.30% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 530 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 463000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 267992 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 529500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 45 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 17 # number of demand (read+write) hits +system.l2.demand_hits::total 62 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 45 # number of overall hits +system.l2.overall_hits::.cpu.data 17 # number of overall hits +system.l2.overall_hits::total 62 # number of overall hits +system.l2.demand_misses::.cpu.inst 309 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 159 # number of demand (read+write) misses +system.l2.demand_misses::total 468 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 309 # number of overall misses +system.l2.overall_misses::.cpu.data 159 # number of overall misses +system.l2.overall_misses::total 468 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 23921500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 13087500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 37009000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 23921500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 13087500 # number of overall miss cycles +system.l2.overall_miss_latency::total 37009000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 354 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 176 # number of demand (read+write) accesses +system.l2.demand_accesses::total 530 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 354 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 176 # number of overall (read+write) accesses +system.l2.overall_accesses::total 530 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.872881 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.903409 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.883019 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.872881 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.903409 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.883019 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77415.857605 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82311.320755 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79079.059829 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77415.857605 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82311.320755 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79079.059829 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_hits::.cpu.data 8 # number of demand (read+write) MSHR hits +system.l2.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.l2.overall_mshr_hits::.cpu.data 8 # number of overall MSHR hits +system.l2.overall_mshr_hits::total 8 # number of overall MSHR hits +system.l2.demand_mshr_misses::.cpu.inst 309 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 151 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 460 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 309 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 151 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 460 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 20841500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 11023500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 31865000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 20841500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 11023500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 31865000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.872881 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.857955 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.867925 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.872881 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.857955 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.867925 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67448.220065 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 73003.311258 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69271.739130 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67448.220065 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 73003.311258 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69271.739130 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackClean_hits::.writebacks 121 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 121 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 121 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 121 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 56 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 56 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 4973000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 4973000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 56 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 56 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 88803.571429 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 88803.571429 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 56 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 56 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 4413000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 4413000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 78803.571429 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 78803.571429 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 45 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 45 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 309 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 309 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 23921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 23921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 354 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 354 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.872881 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.872881 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77415.857605 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77415.857605 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 309 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 309 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 20841500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 20841500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.872881 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.872881 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67448.220065 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67448.220065 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 17 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 17 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 103 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 8114500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 8114500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 120 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 120 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.858333 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.858333 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 78781.553398 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 78781.553398 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_hits::.cpu.data 8 # number of ReadSharedReq MSHR hits +system.l2.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits +system.l2.ReadSharedReq_mshr_misses::.cpu.data 95 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 6610500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 6610500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.791667 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.791667 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69584.210526 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69584.210526 # average ReadSharedReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 405.784549 # Cycle average of tags in use +system.l2.tags.total_refs 642 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 459 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.398693 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.cpu.inst 267.158077 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 138.626472 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.cpu.inst 0.008153 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.004231 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.012384 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::3 407 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 5667 # Number of tag accesses +system.l2.tags.data_accesses 5667 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 19712 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 9664 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 29376 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 19712 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 19712 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 308 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 151 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 459 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 7623012 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 3737256 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 11360268 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 7623012 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 7623012 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 7623012 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 3737256 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 11360268 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 308.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 151.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000545000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 1569 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 459 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 459 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 16 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 20 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 5 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 4377000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 2295000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 12983250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9535.95 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28285.95 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 371 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.83 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 459 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 240 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 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+system.mem_ctrls.bytesPerActivate::stdev 325.065031 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 26 30.23% 30.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 20 23.26% 53.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 13 15.12% 68.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 5 5.81% 74.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 5 5.81% 80.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 4.65% 84.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2 2.33% 87.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1 1.16% 88.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 10 11.63% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 86 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 29376 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 29376 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 11.36 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 11.36 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 0.09 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 0.09 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 2585764500 # Total gap between requests +system.mem_ctrls.avgGap 5633473.86 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 19712 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 9664 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 7623012.044954578392 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 3737255.905156303197 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 308 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 151 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 8184750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 4798500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26573.86 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31778.15 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.83 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 214200 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 110055 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 1263780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 204060480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 47849220 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 952674240 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 1206171975 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 466.450055 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 2476286000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 86320000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 23248500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 414120 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 216315 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 2013480 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 204060480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 48722460 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 951938880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 1207365735 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 466.911706 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 2474386000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 86320000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 25148500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 475760 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 475760 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 475760 # number of overall hits +system.cpu.icache.overall_hits::total 475760 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 477 # number of overall misses +system.cpu.icache.overall_misses::total 477 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 32144500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32144500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 32144500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32144500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 476237 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 476237 # number of demand (read+write) accesses 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 132 # number of writebacks +system.cpu.icache.writebacks::total 132 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 123 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 123 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 123 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 354 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 24952000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24952000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 24952000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24952000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000743 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000743 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000743 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000743 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 70485.875706 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70485.875706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 70485.875706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70485.875706 # average overall mshr miss latency +system.cpu.icache.replacements 132 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 475760 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 475760 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 477 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 32144500 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 1348.762040 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 208.433959 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.814195 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.814195 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 178 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.863281 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 952827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 952827 # Number of data accesses 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1392560 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 711 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 711 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 711 # number of overall misses +system.cpu.dcache.overall_misses::total 711 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 49054498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 49054498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 49054498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 49054498 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 1393271 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1393271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 1393271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1393271 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.000510 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000510 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.000510 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000510 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 68993.668073 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68993.668073 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 68993.668073 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68993.668073 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 534 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_mshr_hits::.cpu.data 535 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 535 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 535 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 13555998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13555998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 13555998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13555998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.000126 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000126 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.000126 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000126 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 77022.715909 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77022.715909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 77022.715909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77022.715909 # average overall mshr miss latency +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 221664 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 221664 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 240 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 240 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 14573000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14573000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 221904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 221904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001082 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 60720.833333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60720.833333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 120 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 120 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000541 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000541 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 70795.833333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70795.833333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 1170896 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1170896 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 471 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 34481498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34481498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 1171367 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1171367 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.000402 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000402 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 73209.125265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73209.125265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 56 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 56 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 5060498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5060498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.000048 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000048 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 90366.035714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90366.035714 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 30500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 30500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 14 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 14 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.071429 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.071429 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 30500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 30500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 159.545531 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1392763 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 176 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7913.426136 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 161000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 159.545531 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.155806 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.155806 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 176 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 160 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.171875 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2786774 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2786774 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2585854500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 2585854500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/GemsFDTD/config.ini b/outoforder/GemsFDTD/config.ini new file mode 100644 index 000000000..a20b9da6a --- /dev/null +++ b/outoforder/GemsFDTD/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc 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+power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/459.GemsFDTD//exe/GemsFDTD_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/GemsFDTD/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/GemsFDTD/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/GemsFDTD/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter 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+ "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/GemsFDTD/fs/proc/cpuinfo b/outoforder/GemsFDTD/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/GemsFDTD/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/GemsFDTD/fs/proc/stat b/outoforder/GemsFDTD/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/GemsFDTD/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/GemsFDTD/fs/sys/devices/system/cpu/online b/outoforder/GemsFDTD/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/GemsFDTD/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/GemsFDTD/fs/sys/devices/system/cpu/possible b/outoforder/GemsFDTD/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/GemsFDTD/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/GemsFDTD/ref.log b/outoforder/GemsFDTD/ref.log new file mode 100644 index 000000000..f40519fd2 --- /dev/null +++ b/outoforder/GemsFDTD/ref.log @@ -0,0 +1,5 @@ + Welcome to GemsFDTD + + EXECUTION HALTED ! (in Check_open) + Application could not open file yee.dat + The value of ios was: 2 diff --git a/outoforder/GemsFDTD/stats.txt b/outoforder/GemsFDTD/stats.txt new file mode 100644 index 000000000..b7e9878bc --- /dev/null +++ b/outoforder/GemsFDTD/stats.txt @@ -0,0 +1,1357 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 61962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 55156 # Simulator instruction rate (inst/s) +host_mem_usage 855244 # Number of bytes of host memory used +host_op_rate 67325 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.53 # Real time elapsed on the host +host_tick_rate 116355832 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 29355 # Number of instructions simulated +sim_ops 35849 # Number of ops (including micro ops) simulated +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 61962500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.723205 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 4252 # Number of BTB hits +system.cpu.branchPred.BTBLookups 5542 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 10 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8981 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 497 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 457 # Number of indirect misses. +system.cpu.branchPred.lookups 12734 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2775 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 2242 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2728 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 2289 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 99 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 265 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 82 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 24 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 20 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 56 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 9 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 16 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 48 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 19 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 157 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 4 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 50 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 3609 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 603 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 184 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 69 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 27 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 43 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 61 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 14 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 358 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 24 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1041 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 131 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 10477 # number of cc regfile reads +system.cpu.cc_regfile_writes 10350 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 934 # The number of times a branch was mispredicted +system.cpu.commit.branches 6765 # Number of branches committed +system.cpu.commit.bw_lim_events 1464 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 48 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14283 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 29435 # Number of instructions committed +system.cpu.commit.committedOps 35929 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 47276 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.759984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.826531 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36313 76.81% 76.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3795 8.03% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1998 4.23% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1237 2.62% 91.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 892 1.89% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 730 1.54% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 432 0.91% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 415 0.88% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1464 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 47276 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 609 # Number of function calls committed. +system.cpu.commit.int_insts 32730 # Number of committed integer instructions. +system.cpu.commit.loads 5438 # Number of loads committed +system.cpu.commit.membars 24 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 24199 67.35% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 53 0.15% 67.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 6 0.02% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.07% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 32 0.09% 67.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.08% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 38 0.11% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 5438 15.14% 83.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6102 16.98% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 35929 # Class of committed instruction +system.cpu.commit.refs 11540 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 477 # Number of committed Vector instructions. +system.cpu.committedInsts 29355 # Number of Instructions Simulated +system.cpu.committedOps 35849 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.221632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.221632 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 15232 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 516 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 4408 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 55880 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 23119 # Number of cycles decode is idle +system.cpu.decode.RunCycles 9540 # Number of cycles decode is running +system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1797 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 778 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 12734 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7861 # Number of cache lines fetched +system.cpu.fetch.Cycles 20839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 901 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 55013 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2968 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.102755 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 5333 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.443918 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 49646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.316078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.623215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 37422 75.38% 75.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1043 2.10% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1301 2.62% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1176 2.37% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1493 3.01% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 985 1.98% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 951 1.92% 89.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 638 1.29% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4637 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 49646 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 74280 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1117 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 8135 # Number of branches executed +system.cpu.iew.exec_nop 169 # number of nop insts executed +system.cpu.iew.exec_rate 0.366243 # Inst execution rate +system.cpu.iew.exec_refs 14525 # number of memory reference insts executed +system.cpu.iew.exec_stores 6953 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2520 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 7866 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8014 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 50287 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 7572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1305 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 45387 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 734 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 752 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 105 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 181 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2428 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1912 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 897 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 38852 # num instructions consuming a value +system.cpu.iew.wb_count 43582 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.561155 # average fanout of values written-back +system.cpu.iew.wb_producers 21802 # num instructions producing a value +system.cpu.iew.wb_rate 0.351678 # insts written-back per cycle +system.cpu.iew.wb_sent 44447 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 50533 # number of integer regfile reads +system.cpu.int_regfile_writes 31002 # number of integer regfile writes +system.cpu.ipc 0.236875 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.236875 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 31303 67.04% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 54 0.12% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.01% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.07% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.09% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 36 0.08% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 45 0.10% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 7886 16.89% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7275 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 46692 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 660 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014135 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 201 30.45% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.30% 30.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.45% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 201 30.45% 61.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 253 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 46706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 142541 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 43022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 63464 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 50040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 46692 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 49646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.940499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 34591 69.68% 69.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3579 7.21% 76.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 3204 6.45% 83.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2742 5.52% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2133 4.30% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1590 3.20% 96.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1016 2.05% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 427 0.86% 99.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 364 0.73% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 49646 # Number of insts issued each cycle +system.cpu.iq.rate 0.376773 # Inst issue rate +system.cpu.iq.vec_alu_accesses 637 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1294 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 560 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 945 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 112 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 7866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8014 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 35114 # number of misc regfile reads +system.cpu.misc_regfile_writes 97 # number of misc regfile writes +system.cpu.numCycles 123926 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3665 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 33835 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 210 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 24047 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 128 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 76045 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 53101 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 49590 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 9354 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1484 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2164 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15755 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 59261 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9439 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 343 # count of serializing insts renamed +system.cpu.rename.skidInsts 3984 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 80 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 803 # Number of vector rename lookups +system.cpu.rob.rob_reads 95673 # The number of ROB reads +system.cpu.rob.rob_writes 102806 # The number of ROB writes +system.cpu.timesIdled 740 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 621 # number of vector regfile reads +system.cpu.vec_regfile_writes 183 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1306 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 648 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 2137 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1064 # Transaction distribution +system.membus.trans_dist::ReadExReq 178 # Transaction distribution +system.membus.trans_dist::ReadExResp 178 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1065 # Transaction distribution +system.membus.trans_dist::InvalidateReq 63 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1306 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1306 # Request fanout histogram +system.membus.reqLayer0.occupancy 1614000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 6586250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1243 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 50 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 543 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 54 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 182 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 182 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1029 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 216 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 63 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 63 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2599 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1026 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3625 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 100480 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 129152 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1490 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001342 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.036625 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1488 99.87% 99.87% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1490 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1661500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 628500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1540500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 144 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 183 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 144 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 183 # number of overall hits +system.l2.demand_misses::.cpu.inst 885 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 359 # number of demand (read+write) misses +system.l2.demand_misses::total 1244 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 885 # number of overall misses +system.l2.overall_misses::.cpu.data 359 # number of overall misses +system.l2.overall_misses::total 1244 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69107000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 30532500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 99639500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69107000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 30532500 # number of overall miss cycles +system.l2.overall_miss_latency::total 99639500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1029 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 398 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1427 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1029 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 398 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1427 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.860058 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.902010 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.871759 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.860058 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.902010 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.871759 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 885 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 359 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1244 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 885 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 359 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1244 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60277000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 26942001 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 87219001 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60277000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 26942001 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 87219001 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.871759 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.871759 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 50 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 50 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 543 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 543 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 543 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 543 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 4 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 4 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 178 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 178 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 63 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 63 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19015.873016 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19015.873016 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 674.522414 # Cycle average of tags in use +system.l2.tags.total_refs 2071 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1248 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.659455 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.805164 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 455.337647 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 217.379603 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013896 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006634 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.020585 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1248 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.038086 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 18336 # Number of tag accesses +system.l2.tags.data_accesses 18336 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56576 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 22976 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 79552 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 884 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 359 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1243 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 913068388 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 370804922 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1283873310 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 913068388 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 370804922 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1283873310 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 884.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 359.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000554500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2436 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1243 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1243 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 151 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 25 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 12775500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6215000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 36081750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10277.96 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29027.96 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 971 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.12 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1243 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 698 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 361 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 260 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 297.107692 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.423498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.377322 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 30.00% 30.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 65 25.00% 55.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45 17.31% 72.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 19 7.31% 79.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 6.15% 85.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 3.46% 89.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 1.92% 91.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 2.31% 93.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 6.54% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 260 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 79552 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 79552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1283.87 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1283.87 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.03 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 61929000 # Total gap between requests +system.mem_ctrls.avgGap 49822.20 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56576 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 22976 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 913068388.137986779213 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 370804922.332055687904 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 884 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 359 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23954000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 12127750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27097.29 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33782.03 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1185240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 607200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4976580 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 27790920 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 390720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 39253140 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 633.498326 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 824000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 59318500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 756840 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3898440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 27598260 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 552960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 37488480 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 605.018842 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1232500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 58910000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6542 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6542 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6542 # number of overall hits +system.cpu.icache.overall_hits::total 6542 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1319 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1319 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1319 # number of overall misses +system.cpu.icache.overall_misses::total 1319 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 91010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 91010500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7861 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.167790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.167790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.167790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.167790 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 543 # number of writebacks +system.cpu.icache.writebacks::total 543 # number of writebacks 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of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72191000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.130899 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.130899 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70156.462585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70156.462585 # average overall mshr miss latency +system.cpu.icache.replacements 543 # number of replacements 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average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 290 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 72191000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72191000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.130899 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70156.462585 # average ReadReq mshr miss latency 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task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 16749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 16749 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 11600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 11622 # number of overall hits +system.cpu.dcache.overall_hits::total 11622 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1511 # number of overall misses +system.cpu.dcache.overall_misses::total 1511 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 98038926 # number of overall miss cycles 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number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 72346.492274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72346.492274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72339.434498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72339.434498 # average overall mshr miss latency +system.cpu.dcache.replacements 104 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 6518 # number of ReadReq hits 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296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 231.645691 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12141 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 461 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.336226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 231.645691 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 26849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 26849 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 61962500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/astar/config.ini b/outoforder/astar/config.ini new file mode 100644 index 000000000..7d7909b9e --- /dev/null +++ b/outoforder/astar/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 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+eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/exe/astar_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/473.astar/data/ref/input/rivers.cfg +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/exe/astar_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lake.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/astar/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/astar/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/astar/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/astar/config.json b/outoforder/astar/config.json new file mode 100644 index 000000000..9b5b90486 --- /dev/null +++ b/outoforder/astar/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + 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+ "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/astar/fs/proc/cpuinfo b/outoforder/astar/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/astar/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/astar/fs/proc/stat b/outoforder/astar/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/astar/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/astar/fs/sys/devices/system/cpu/online b/outoforder/astar/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/astar/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/astar/fs/sys/devices/system/cpu/possible b/outoforder/astar/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/astar/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/astar/lake.out b/outoforder/astar/lake.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/astar/stats.txt b/outoforder/astar/stats.txt new file mode 100644 index 000000000..acd77a432 --- /dev/null +++ b/outoforder/astar/stats.txt @@ -0,0 +1,1334 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 171482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 104443 # Simulator instruction rate (inst/s) +host_mem_usage 852360 # Number of bytes of host memory used +host_op_rate 130785 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.79 # Real time elapsed on the host +host_tick_rate 35817522 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500002 # Number of instructions simulated +sim_ops 626147 # Number of ops (including micro ops) simulated +sim_seconds 0.000171 # Number of seconds simulated +sim_ticks 171482000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.530541 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 33531 # Number of BTB hits +system.cpu.branchPred.BTBLookups 34380 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 940 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 70311 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 5 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 195 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 190 # Number of indirect misses. +system.cpu.branchPred.lookups 97566 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 52998 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 14599 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 52977 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 14620 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 49 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 11 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 2262 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1526 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3006 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 739 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1478 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 58 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 6 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 57977 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 434 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1528 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 760 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1497 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3004 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 745 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 738 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 744 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 8959 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 11 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 14 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 7880 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 130530 # number of cc regfile reads +system.cpu.cc_regfile_writes 130470 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted +system.cpu.commit.branches 93687 # Number of branches committed +system.cpu.commit.bw_lim_events 46805 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 10029 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500029 # Number of instructions committed +system.cpu.commit.committedOps 626174 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 283130 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.211613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.047100 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 138046 48.76% 48.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 50313 17.77% 66.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8889 3.14% 69.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8168 2.88% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13116 4.63% 77.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4715 1.67% 78.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8446 2.98% 81.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4632 1.64% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 46805 16.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 283130 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 7664 # Number of function calls committed. +system.cpu.commit.int_insts 578604 # Number of committed integer instructions. +system.cpu.commit.loads 99559 # Number of loads committed +system.cpu.commit.membars 46 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 402860 64.34% 64.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3010 0.48% 64.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 64.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 1486 0.24% 65.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 1492 0.24% 65.29% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 65.29% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 1 0.00% 65.29% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1489 0.24% 65.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1492 0.24% 65.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 18 0.00% 65.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 16 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 2 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 15 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 99559 15.90% 81.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 114707 18.32% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 626174 # Class of committed instruction +system.cpu.commit.refs 214266 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 6280 # Number of committed Vector instructions. +system.cpu.committedInsts 500002 # Number of Instructions Simulated +system.cpu.committedOps 626147 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.685927 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.685927 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 157998 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 350 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 33668 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 639989 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 34491 # Number of cycles decode is idle +system.cpu.decode.RunCycles 79367 # Number of cycles decode is running +system.cpu.decode.SquashCycles 655 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1243 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 12268 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 97566 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63193 # Number of cache lines fetched +system.cpu.fetch.Cycles 206346 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 629 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 517297 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1980 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.284478 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 77368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 41416 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.508308 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 284779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.266459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.167755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 166086 58.32% 58.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11064 3.89% 62.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14231 5.00% 67.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 12510 4.39% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3028 1.06% 72.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 14554 5.11% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 10124 3.56% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2698 0.95% 82.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 50484 17.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 284779 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 58186 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 696 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 94726 # Number of branches executed +system.cpu.iew.exec_nop 53 # number of nop insts executed +system.cpu.iew.exec_rate 1.845037 # Inst execution rate +system.cpu.iew.exec_refs 216299 # number of memory reference insts executed +system.cpu.iew.exec_stores 115245 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1778 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 101325 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 115870 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 636323 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 101054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 632783 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 136 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 655 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 148 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 59 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 131 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1764 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1153 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 625815 # num instructions consuming a value +system.cpu.iew.wb_count 631745 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.561303 # average fanout of values written-back +system.cpu.iew.wb_producers 351272 # num instructions producing a value +system.cpu.iew.wb_rate 1.842010 # insts written-back per cycle +system.cpu.iew.wb_sent 632131 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 748225 # number of integer regfile reads +system.cpu.int_regfile_writes 459977 # number of integer regfile writes +system.cpu.ipc 1.457881 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.457881 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 6 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 407939 64.38% 64.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3011 0.48% 64.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 64.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1486 0.23% 65.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 1492 0.24% 65.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 65.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 1 0.00% 65.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1490 0.24% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1493 0.24% 65.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 65.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 20 0.00% 65.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 23 0.00% 65.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 2 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101256 15.98% 81.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 115414 18.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 633681 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 12382 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019540 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1660 13.41% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2 0.02% 13.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 13.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1 0.01% 13.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 11 0.09% 13.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 13.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.02% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 13.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3074 24.83% 38.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7631 61.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 639662 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1551868 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 625429 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 639913 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 636187 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 633681 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6406 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 284779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.225168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.599312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 124088 43.57% 43.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26226 9.21% 52.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 30231 10.62% 63.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23784 8.35% 71.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15410 5.41% 77.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20742 7.28% 84.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17067 5.99% 90.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9959 3.50% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17272 6.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 284779 # Number of insts issued each cycle +system.cpu.iq.rate 1.847655 # Inst issue rate +system.cpu.iq.vec_alu_accesses 6395 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 12748 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 6316 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 6480 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 136 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1588 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 101325 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 115870 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 442359 # number of misc regfile reads +system.cpu.misc_regfile_writes 4659 # number of misc regfile writes +system.cpu.numCycles 342965 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 1939 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 593543 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 46 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 43937 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 948895 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 638486 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 606042 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 82167 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1045 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 655 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 16155 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 12467 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 754669 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 139926 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 9096 # count of serializing insts renamed +system.cpu.rename.skidInsts 77495 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 85 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 7943 # Number of vector rename lookups +system.cpu.rob.rob_reads 872255 # The number of ROB reads +system.cpu.rob.rob_writes 1274102 # The number of ROB writes +system.cpu.timesIdled 533 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 7846 # number of vector regfile reads +system.cpu.vec_regfile_writes 4580 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 965 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 329 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1357 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 816 # Transaction distribution +system.membus.trans_dist::ReadExReq 139 # Transaction distribution +system.membus.trans_dist::ReadExResp 139 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 1920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1920 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 61120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 61120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 965 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 965 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 965 # Request fanout histogram +system.membus.reqLayer0.occupancy 1200500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5059250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.0 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 879 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 303 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 9 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 140 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 140 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 765 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 10 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 10 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1833 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 553 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 2386 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 68352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 17280 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 85632 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1029 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000972 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.031174 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1028 99.90% 99.90% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1029 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 997500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 386000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1147500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 63 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 64 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 63 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 64 # number of overall hits +system.l2.demand_misses::.cpu.inst 702 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 253 # number of demand (read+write) misses +system.l2.demand_misses::total 955 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 702 # number of overall misses +system.l2.overall_misses::.cpu.data 253 # number of overall misses +system.l2.overall_misses::total 955 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 55600500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 21544500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 77145000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 55600500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 21544500 # number of overall miss cycles +system.l2.overall_miss_latency::total 77145000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 765 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 254 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1019 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 765 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 254 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1019 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.917647 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.996063 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.937193 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.917647 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.996063 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.937193 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79202.991453 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85156.126482 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80780.104712 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79202.991453 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85156.126482 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80780.104712 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 702 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 253 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 955 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 702 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 253 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 955 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 48580500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 19014500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 67595000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 48580500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 19014500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 67595000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.996063 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.937193 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.996063 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.937193 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75156.126482 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70780.104712 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75156.126482 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70780.104712 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 16 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 303 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 303 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 303 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 303 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 139 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 139 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 11261500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 11261500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 140 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 140 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.992857 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.992857 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 81017.985612 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 81017.985612 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 139 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 9871500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 9871500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.992857 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 71017.985612 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 71017.985612 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 63 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 63 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 702 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 55600500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 55600500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 765 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 765 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.917647 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.917647 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79202.991453 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79202.991453 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 702 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 702 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 48580500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 48580500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.917647 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.917647 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69202.991453 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69202.991453 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_misses::.cpu.data 114 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 114 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10283000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10283000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 90201.754386 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 90201.754386 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 114 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 114 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9143000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9143000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 80201.754386 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 80201.754386 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 191000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 191000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19100 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19100 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 839.096291 # Cycle average of tags in use +system.l2.tags.total_refs 1347 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 955 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.410471 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.cpu.inst 608.450718 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 230.645572 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.cpu.inst 0.018568 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.007039 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.025607 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.029144 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 11811 # Number of tag accesses +system.l2.tags.data_accesses 11811 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 44928 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 16192 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 61120 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 44928 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 702 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 253 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 955 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 261998344 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 94423905 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 356422248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 261998344 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 261998344 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 261998344 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 94423905 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 356422248 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 702.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 253.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000566000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 1902 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 955 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 955 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 20 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 45 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 96 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 158 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.22 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10336000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 4775000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 28242250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10823.04 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29573.04 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 745 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.01 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 955 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 513 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 286 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 291.047619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 182.955326 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 302.852290 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 65 30.95% 30.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 67 31.90% 62.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 24 11.43% 74.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 12 5.71% 80.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 3.81% 83.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 4.29% 88.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 1.43% 89.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.95% 90.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 20 9.52% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 210 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 61120 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 61120 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 356.42 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 356.42 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.78 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 45588000 # Total gap between requests +system.mem_ctrls.avgGap 47736.13 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 44928 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 16192 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 261998343.849500238895 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 94423904.549748659134 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 702 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 253 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 19686250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8556000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28043.09 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33818.18 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.01 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 406065 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 3291540 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 22458000 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46960800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 87402465 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 509.688859 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 121921500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 5644500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 43916000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 735420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 390885 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3527160 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 22871250 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 46612800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 87659595 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 511.188317 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 121001000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 5644500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 44836500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks 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miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 63192 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 63192 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 63192 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 63192 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015113 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 72456.543455 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72456.543455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 72456.543455 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72456.543455 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 939 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 303 # number of writebacks +system.cpu.icache.writebacks::total 303 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 190 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits 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# mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.012106 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.012106 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.012106 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 75137.253595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75137.253595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 75137.253595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75137.253595 # average overall mshr miss latency +system.cpu.icache.replacements 303 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 62237 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 62237 # number of ReadReq hits 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+system.cpu.icache.tags.tagsinuse 413.703759 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 63002 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 765 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 82.355556 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 413.703759 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.808015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 462 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 127149 # Number of tag accesses +system.cpu.icache.tags.data_accesses 127149 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 214376 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 214376 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 214384 # number of overall hits +system.cpu.dcache.overall_hits::total 214384 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 871 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 871 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 873 # number of overall misses +system.cpu.dcache.overall_misses::total 873 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 61890955 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 61890955 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 61890955 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 61890955 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 215247 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 215247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 215257 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 215257 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.004047 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004047 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.004056 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004056 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 71057.353617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71057.353617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 70894.564719 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70894.564719 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2750 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.354839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 609 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 609 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 609 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 609 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 264 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 22065995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22065995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 22250495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22250495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.001217 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001217 # mshr miss rate for demand accesses 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+system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.001113 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001113 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 91714.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91714.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 114029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 114029 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 626 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 626 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 42262457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42262457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 114655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 114655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.005460 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005460 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67511.912141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67511.912141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 11578497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11578497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.001247 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001247 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 80968.510490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80968.510490 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 46 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 46 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 46 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 46 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 219.888385 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 214749 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 264 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 813.443182 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 219.888385 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.429470 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.429470 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 239 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 430980 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 430980 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 171482000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 171482000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/benchlist.txt b/outoforder/benchlist.txt new file mode 100644 index 000000000..673136530 --- /dev/null +++ b/outoforder/benchlist.txt @@ -0,0 +1,20 @@ +astar +benchlist.txt +bwaves +bzip2 +cactusADM +calculix +GemsFDTD +gobmk +h264ref +hmmer +lbm +leslie3d +libquantum +mcf +milc +namd +omnetpp +povray +sjeng +xalancbmk diff --git a/outoforder/bwaves/config.ini b/outoforder/bwaves/config.ini new file mode 100644 index 000000000..717aa1884 --- /dev/null +++ b/outoforder/bwaves/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/410.bwaves/exe/bwaves_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/410.bwaves/exe/bwaves_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/bwaves/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/bwaves/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/bwaves/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/bwaves/config.json b/outoforder/bwaves/config.json new file mode 100644 index 000000000..359cc5bdb --- /dev/null +++ b/outoforder/bwaves/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/bwaves/fs/proc/cpuinfo b/outoforder/bwaves/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/bwaves/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/bwaves/fs/proc/stat b/outoforder/bwaves/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/bwaves/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/bwaves/fs/sys/devices/system/cpu/online b/outoforder/bwaves/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/bwaves/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/bwaves/fs/sys/devices/system/cpu/possible b/outoforder/bwaves/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/bwaves/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/bwaves/stats.txt b/outoforder/bwaves/stats.txt new file mode 100644 index 000000000..cd4c878c1 --- /dev/null +++ b/outoforder/bwaves/stats.txt @@ -0,0 +1,1362 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 215801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 125313 # Simulator instruction rate (inst/s) +host_mem_usage 854176 # Number of bytes of host memory used +host_op_rate 137627 # Simulator op (including micro ops) rate (op/s) +host_seconds 3.99 # Real time elapsed on the host +host_tick_rate 54081003 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_ops 549171 # Number of ops (including micro ops) simulated +sim_seconds 0.000216 # Number of seconds simulated +sim_ticks 215801500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.253021 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 65859 # Number of BTB hits +system.cpu.branchPred.BTBLookups 67030 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1481 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 107415 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3002 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3395 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 393 # Number of indirect misses. +system.cpu.branchPred.lookups 156966 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 66630 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 34101 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 63915 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 36816 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 130 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1230 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 88 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 238 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 40 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 207 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 247 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 110 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 56 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 50 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 360 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 385 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 592 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 23 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 498 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 679 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1203 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 563 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 75 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 209 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 290 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 11 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 118 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 90417 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 585 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 136 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 80 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1358 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 212 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 229 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 177 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1281 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 71 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 201 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 116 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 357 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 585 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 384 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 490 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 39 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 683 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1209 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 629 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 924 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 8968 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 37 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 94 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 18160 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 106 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 262236 # number of cc regfile reads +system.cpu.cc_regfile_writes 211752 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 1040 # The number of times a branch was mispredicted +system.cpu.commit.branches 147375 # Number of branches committed +system.cpu.commit.bw_lim_events 37643 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 24982 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500154 # Number of instructions committed +system.cpu.commit.committedOps 549325 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 363157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.653362 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 234192 64.49% 64.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 34814 9.59% 74.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16631 4.58% 78.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10852 2.99% 81.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10873 2.99% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7592 2.09% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7823 2.15% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2737 0.75% 89.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 37643 10.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 363157 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 17470 # Number of function calls committed. +system.cpu.commit.int_insts 468679 # Number of committed integer instructions. +system.cpu.commit.loads 59528 # Number of loads committed +system.cpu.commit.membars 4 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 11 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 449250 81.78% 81.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 67 0.01% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 35 0.01% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 81.80% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 42 0.01% 81.81% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 45 0.01% 81.82% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 81.82% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 49 0.01% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 81.83% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 59528 10.84% 92.66% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 40295 7.34% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 549325 # Class of committed instruction +system.cpu.commit.refs 99823 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 748 # Number of committed Vector instructions. +system.cpu.committedInsts 500000 # Number of Instructions Simulated +system.cpu.committedOps 549171 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.863208 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.863208 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 139354 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 450 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 65767 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 582542 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 103875 # Number of cycles decode is idle +system.cpu.decode.RunCycles 115800 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1114 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1532 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 6786 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 156966 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 103681 # Number of cache lines fetched +system.cpu.fetch.Cycles 245774 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 538539 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3110 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.363681 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 119547 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 87021 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.247762 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 366929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.615059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.546356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 233487 63.63% 63.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9379 2.56% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 26336 7.18% 73.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24507 6.68% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7723 2.10% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20744 5.65% 87.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14266 3.89% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7064 1.93% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 23423 6.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 366929 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 64675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1208 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 150507 # Number of branches executed +system.cpu.iew.exec_nop 234 # number of nop insts executed +system.cpu.iew.exec_rate 1.319077 # Inst execution rate +system.cpu.iew.exec_refs 107123 # number of memory reference insts executed +system.cpu.iew.exec_stores 41747 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 67173 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 63248 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 236 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43072 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 574720 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 65376 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1680 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 569319 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 313 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2552 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1114 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3610 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 125 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2300 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2990 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3717 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2762 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 304 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 562224 # num instructions consuming a value +system.cpu.iew.wb_count 564399 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.491276 # average fanout of values written-back +system.cpu.iew.wb_producers 276207 # num instructions producing a value +system.cpu.iew.wb_rate 1.307678 # insts written-back per cycle +system.cpu.iew.wb_sent 565317 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 613184 # number of integer regfile reads +system.cpu.int_regfile_writes 404259 # number of integer regfile writes +system.cpu.ipc 1.158469 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.158469 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 13 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 462748 81.04% 81.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 68 0.01% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 45 0.01% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 56 0.01% 81.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 53 0.01% 81.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.01% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65774 11.52% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42184 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 571002 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3742 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006553 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2984 79.74% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.05% 79.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.05% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 79.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 348 9.30% 89.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 406 10.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 573818 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1511010 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 563575 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 598693 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 574438 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 571002 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 25255 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 366929 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.556165 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 157895 43.03% 43.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67562 18.41% 61.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 47022 12.82% 74.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 39260 10.70% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16527 4.50% 89.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18825 5.13% 94.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11324 3.09% 97.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4673 1.27% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3841 1.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 366929 # Number of insts issued each cycle +system.cpu.iq.rate 1.322977 # Inst issue rate +system.cpu.iq.vec_alu_accesses 913 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1829 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 824 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1080 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 6271 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8405 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 63248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43072 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 385733 # number of misc regfile reads +system.cpu.misc_regfile_writes 17 # number of misc regfile writes +system.cpu.numCycles 431604 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 100687 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 600141 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 16790 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 106338 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1767 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1554 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 896570 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 578930 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 629566 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 118433 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7057 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1114 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 29680 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 29365 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 624354 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 10677 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 291 # count of serializing insts renamed +system.cpu.rename.skidInsts 40774 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 50 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1032 # Number of vector rename lookups +system.cpu.rob.rob_reads 899119 # The number of ROB reads +system.cpu.rob.rob_writes 1152477 # The number of ROB writes +system.cpu.timesIdled 621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 918 # number of vector regfile reads +system.cpu.vec_regfile_writes 239 # number of vector regfile writes +system.cpu.workload.numSyscalls 37 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2463 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 3928 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 8833 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1802 # Transaction distribution +system.membus.trans_dist::ReadExReq 540 # Transaction distribution +system.membus.trans_dist::ReadExResp 540 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1802 # Transaction distribution +system.membus.trans_dist::InvalidateReq 121 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 4805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4805 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 149888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149888 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2463 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2463 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2463 # Request fanout histogram +system.membus.reqLayer0.occupancy 2904500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 12358500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4224 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 911 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 371 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 2646 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 560 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 560 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 836 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 3388 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 121 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 121 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2043 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 11695 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 13738 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 77248 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 310976 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 388224 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 4905 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000204 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.014278 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 4904 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 4905 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 5698500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 5982500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.8 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1254000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 39 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 2403 # number of demand (read+write) hits +system.l2.demand_hits::total 2442 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 39 # number of overall hits +system.l2.overall_hits::.cpu.data 2403 # number of overall hits +system.l2.overall_hits::total 2442 # number of overall hits +system.l2.demand_misses::.cpu.inst 797 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1545 # number of demand (read+write) misses +system.l2.demand_misses::total 2342 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 797 # number of overall misses +system.l2.overall_misses::.cpu.data 1545 # number of overall misses +system.l2.overall_misses::total 2342 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61839000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 117175000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 179014000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61839000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 117175000 # number of overall miss cycles +system.l2.overall_miss_latency::total 179014000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 836 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 3948 # number of demand (read+write) accesses +system.l2.demand_accesses::total 4784 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 836 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 3948 # number of overall (read+write) accesses +system.l2.overall_accesses::total 4784 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.953349 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.391337 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.489548 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.953349 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.391337 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.489548 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77589.711418 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75841.423948 # average overall miss latency +system.l2.demand_avg_miss_latency::total 76436.379163 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77589.711418 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75841.423948 # average overall miss latency +system.l2.overall_avg_miss_latency::total 76436.379163 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 797 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1545 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2342 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 797 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1545 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2342 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53869000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 101725000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 155594000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53869000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 101725000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 155594000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.953349 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.391337 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.489548 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.953349 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.391337 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.489548 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67589.711418 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65841.423948 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 66436.379163 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67589.711418 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65841.423948 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 66436.379163 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 911 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 911 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 911 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 911 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 371 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 371 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 371 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 371 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 20 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 20 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 540 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 540 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 41602500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 41602500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 560 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 560 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.964286 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.964286 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77041.666667 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77041.666667 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 540 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 540 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 36202500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 36202500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.964286 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67041.666667 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67041.666667 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 39 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 39 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 797 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 797 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61839000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61839000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 836 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 836 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.953349 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.953349 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77589.711418 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77589.711418 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 797 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 797 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53869000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53869000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.953349 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.953349 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67589.711418 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67589.711418 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 2383 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 2383 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1005 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1005 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 75572500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 75572500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 3388 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 3388 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.296635 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.296635 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 75196.517413 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 75196.517413 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1005 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1005 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 65522500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 65522500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.296635 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.296635 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 65196.517413 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 65196.517413 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 121 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 121 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 121 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 121 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 121 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 121 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2304000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2304000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19041.322314 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19041.322314 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1680.965477 # Cycle average of tags in use +system.l2.tags.total_refs 8711 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2463 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.536744 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 82.177161 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 678.510759 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 920.277557 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.002508 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.020707 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.028085 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.051299 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2463 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2028 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.075165 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 73119 # Number of tag accesses +system.l2.tags.data_accesses 73119 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 51008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 98880 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 149888 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 51008 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 51008 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 797 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1545 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2342 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 236365364 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 458198854 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 694564218 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 236365364 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 236365364 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 236365364 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 458198854 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 694564218 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 797.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1545.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000572000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4694 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2342 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2342 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 148 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 274 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 278 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 227 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 233 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 229 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 76 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 38 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15557000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 11710000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 59469500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6642.61 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 25392.61 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2021 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.29 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2342 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1779 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 396 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 124 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 321 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 466.940810 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 291.879295 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 384.847144 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 69 21.50% 21.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 69 21.50% 42.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 24 7.48% 50.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26 8.10% 58.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 25 7.79% 66.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.74% 70.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.80% 72.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.56% 74.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 82 25.55% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 321 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 149888 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 149888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 694.56 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 694.56 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.43 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.43 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 206747500 # Total gap between requests +system.mem_ctrls.avgGap 88278.18 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 51008 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 98880 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 236365363.540105134249 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 458198854.039476096630 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 797 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1545 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21060000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 38409500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26424.09 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24860.52 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.29 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 742560 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 394680 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4833780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 16595280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 38151810 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 50740320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 111458430 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 516.485891 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 131469000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 7020000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 77312500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1549380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 823515 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 11888100 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 16595280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 85224120 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 11100480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 127180875 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 589.341942 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 27848750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 7020000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 180932750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 102601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 102601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 102601 # number of overall hits +system.cpu.icache.overall_hits::total 102601 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1079 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1079 # number of overall misses +system.cpu.icache.overall_misses::total 1079 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 79479499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 79479499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 79479499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 79479499 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 103680 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 103680 # number of demand (read+write) accesses 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 371 # number of writebacks +system.cpu.icache.writebacks::total 371 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 836 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 836 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 836 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 836 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 63517000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 63517000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 63517000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 63517000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.008063 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008063 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.008063 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008063 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 75977.272727 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75977.272727 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 75977.272727 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75977.272727 # average overall mshr miss latency +system.cpu.icache.replacements 371 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 102601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 102601 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1079 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 79479499 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 123.728469 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 419.185333 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.818721 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.818721 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 465 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 432 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.908203 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 208196 # Number of tag accesses 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of overall hits +system.cpu.dcache.overall_hits::total 88077 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 11978 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11978 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 11980 # number of overall misses +system.cpu.dcache.overall_misses::total 11980 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 493200886 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 493200886 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 493200886 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 493200886 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 100033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 100033 # number of demand (read+write) accesses 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blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 152 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.914474 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 911 # number of writebacks +system.cpu.dcache.writebacks::total 911 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 7912 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7912 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 7912 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7912 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 4066 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4066 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 4068 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4068 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 151857425 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151857425 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 152019925 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152019925 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.040647 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.040647 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.040657 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.040657 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 37348.112395 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37348.112395 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 37369.696411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37369.696411 # average overall mshr miss latency +system.cpu.dcache.replacements 3557 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 50465 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 50465 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 9275 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9275 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 346977500 # number of ReadReq miss cycles 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+system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 105361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 105361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.056662 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056662 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 31125.997046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31125.997046 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 37583 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37583 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 2590 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2590 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 142611450 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 142611450 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 40173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 40173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.064471 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.064471 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 55062.335907 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55062.335907 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 568 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 568 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 42996989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 42996989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.014139 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014139 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 75698.924296 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75698.924296 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 113 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 113 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3611936 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3611936 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 120 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 120 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.941667 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.941667 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31964.035398 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31964.035398 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 113 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 113 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3498936 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3498936 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.941667 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.941667 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30964.035398 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30964.035398 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 426.241122 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 92155 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4069 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.648071 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 426.241122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.832502 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.832502 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 204203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 204203 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 215801500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 215801500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/bzip2/config.ini b/outoforder/bzip2/config.ini new file mode 100644 index 000000000..94b291431 --- /dev/null +++ b/outoforder/bzip2/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] 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system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + 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+power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2/data/ref/input/input.source 1 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=input.source.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/bzip2/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/bzip2/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/bzip2/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state 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"system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/bzip2/fs/proc/cpuinfo b/outoforder/bzip2/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/bzip2/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/bzip2/fs/proc/stat b/outoforder/bzip2/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/bzip2/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/bzip2/fs/sys/devices/system/cpu/online b/outoforder/bzip2/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/bzip2/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/bzip2/fs/sys/devices/system/cpu/possible b/outoforder/bzip2/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/bzip2/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/bzip2/input.source.out b/outoforder/bzip2/input.source.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/bzip2/stats.txt b/outoforder/bzip2/stats.txt new file mode 100644 index 000000000..f4b704d22 --- /dev/null +++ b/outoforder/bzip2/stats.txt @@ -0,0 +1,1387 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 265450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 97329 # Simulator instruction rate (inst/s) +host_mem_usage 850704 # Number of bytes of host memory used +host_op_rate 102847 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.14 # Real time elapsed on the host +host_tick_rate 51669054 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500007 # Number of instructions simulated +sim_ops 528374 # Number of ops (including micro ops) simulated +sim_seconds 0.000265 # Number of seconds simulated +sim_ticks 265450500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.267875 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 77150 # Number of BTB hits +system.cpu.branchPred.BTBLookups 77719 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1449 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 102457 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 6 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 213 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 207 # Number of indirect misses. +system.cpu.branchPred.lookups 127041 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 50272 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 13213 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 44320 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 19165 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 61 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 17 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 3248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 308 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 811 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1770 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1513 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 433 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 902 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 979 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 963 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 855 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 334 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 655 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 595 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 960 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 1214 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 401 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1469 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1659 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 694 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1418 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 706 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 40 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 235 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 39495 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 389 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 372 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3284 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 317 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1006 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1322 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2368 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 841 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 517 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 965 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 994 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 245 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 434 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 423 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1016 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 516 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1462 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1842 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 755 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1677 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1544 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 22012 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 139 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 351 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 731 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 56 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 203148 # number of cc regfile reads +system.cpu.cc_regfile_writes 203373 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 1221 # The number of times a branch was mispredicted +system.cpu.commit.branches 85775 # Number of branches committed +system.cpu.commit.bw_lim_events 42248 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 149818 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500277 # Number of instructions committed +system.cpu.commit.committedOps 528644 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 468533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.128296 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.405357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 326775 69.74% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 61232 13.07% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17282 3.69% 86.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7872 1.68% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2799 0.60% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5191 1.11% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1841 0.39% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3293 0.70% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 42248 9.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 468533 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 452 # Number of function calls committed. +system.cpu.commit.int_insts 465265 # Number of committed integer instructions. +system.cpu.commit.loads 186291 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 9 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 257589 48.73% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 21 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 48.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 29 0.01% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 34 0.01% 48.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 36 0.01% 48.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 48.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 26 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 48.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 186291 35.24% 84.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 84606 16.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 528644 # Class of committed instruction +system.cpu.commit.refs 270897 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 224 # Number of committed Vector instructions. +system.cpu.committedInsts 500007 # Number of Instructions Simulated +system.cpu.committedOps 528374 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.061789 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.061789 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 293946 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 238 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 69270 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 696577 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 65517 # Number of cycles decode is idle +system.cpu.decode.RunCycles 102886 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2067 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 23753 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 127041 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 80126 # Number of cache lines fetched +system.cpu.fetch.Cycles 394258 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 687 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 712195 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4590 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239293 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 91541 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 77887 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.341481 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 488169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.524331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.662098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 322097 65.98% 65.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 46671 9.56% 75.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10753 2.20% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2677 0.55% 78.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13712 2.81% 81.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 37961 7.78% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1639 0.34% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7836 1.61% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 44823 9.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 488169 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1382 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 113193 # Number of branches executed +system.cpu.iew.exec_nop 344 # number of nop insts executed +system.cpu.iew.exec_rate 1.393734 # Inst execution rate +system.cpu.iew.exec_refs 397781 # number of memory reference insts executed +system.cpu.iew.exec_stores 111912 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 28098 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 219266 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 114644 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 682198 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 285869 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1706 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 739936 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 18704 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2067 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 18124 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2098 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 54687 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 48 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 27169 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 32965 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 30036 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 820 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 562 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 724643 # num instructions consuming a value +system.cpu.iew.wb_count 644037 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.575838 # average fanout of values written-back +system.cpu.iew.wb_producers 417277 # num instructions producing a value +system.cpu.iew.wb_rate 1.213100 # insts written-back per cycle +system.cpu.iew.wb_sent 669570 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 910184 # number of integer regfile reads +system.cpu.int_regfile_writes 467728 # number of integer regfile writes +system.cpu.ipc 0.941807 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.941807 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 342670 46.20% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 24 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 6 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 38 0.01% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 40 0.01% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 28 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 46.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 286573 38.64% 84.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 112218 15.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 741642 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 18124 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024438 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 745 4.11% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 4.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.02% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 4.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 16188 89.32% 93.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1186 6.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 759471 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1989258 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 643786 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 834889 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 681773 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 741642 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 153455 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 266 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 94555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 488169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.519232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 251315 51.48% 51.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 42165 8.64% 60.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 63076 12.92% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 39168 8.02% 81.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46548 9.54% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 22055 4.52% 95.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11472 2.35% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8438 1.73% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3932 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 488169 # Number of insts issued each cycle +system.cpu.iq.rate 1.396947 # Inst issue rate +system.cpu.iq.vec_alu_accesses 285 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 585 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 251 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 478 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 48589 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31042 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 219266 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 114644 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 573637 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 530902 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 73613 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 506606 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 9883 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 76961 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 37640 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1546 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1051627 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 690760 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 692058 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 113921 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 156928 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 2067 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 211678 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 185409 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 839757 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9929 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 204 # count of serializing insts renamed +system.cpu.rename.skidInsts 139713 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 486 # Number of vector rename lookups +system.cpu.rob.rob_reads 1094334 # The number of ROB reads +system.cpu.rob.rob_writes 1376605 # The number of ROB writes +system.cpu.timesIdled 374 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 333 # number of vector regfile reads +system.cpu.vec_regfile_writes 167 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1139 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6408 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4485 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 16 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 9857 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 16 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1871 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1131 # Transaction distribution +system.membus.trans_dist::CleanEvict 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 3391 # Transaction distribution +system.membus.trans_dist::ReadExResp 3391 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1871 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 11670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11670 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 409152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 409152 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 5269 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5269 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5269 # Request fanout histogram +system.membus.reqLayer0.occupancy 11696000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 27149000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1941 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4383 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 142 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1115 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3423 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3423 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 517 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1424 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 8 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 8 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1176 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 14053 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 15229 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 518336 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 560512 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1155 # Total snoops (count) +system.tol2bus.snoopTraffic 72384 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6527 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002605 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.050972 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6510 99.74% 99.74% # Request fanout histogram +system.tol2bus.snoop_fanout::1 17 0.26% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6527 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8322500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 7274500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 775500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 9 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 93 # number of demand (read+write) hits +system.l2.demand_hits::total 102 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 9 # number of overall hits +system.l2.overall_hits::.cpu.data 93 # number of overall hits +system.l2.overall_hits::total 102 # number of overall hits +system.l2.demand_misses::.cpu.inst 508 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4754 # number of demand (read+write) misses +system.l2.demand_misses::total 5262 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 508 # number of overall misses +system.l2.overall_misses::.cpu.data 4754 # number of overall misses +system.l2.overall_misses::total 5262 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40426500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 420799000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 461225500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40426500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 420799000 # number of overall miss cycles +system.l2.overall_miss_latency::total 461225500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 517 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 4847 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5364 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 517 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 4847 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5364 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.982592 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.980813 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.980984 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.982592 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.980813 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.980984 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 88514.724443 # average overall miss latency +system.l2.demand_avg_miss_latency::total 87652.128468 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 88514.724443 # average overall miss latency +system.l2.overall_avg_miss_latency::total 87652.128468 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1131 # number of writebacks +system.l2.writebacks::total 1131 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 508 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4754 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 5262 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 508 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4754 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 5262 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35346500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 373259000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 408605500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35346500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 373259000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 408605500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.980813 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.980984 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.980813 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.980984 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 78514.724443 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 77652.128468 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 78514.724443 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 77652.128468 # average overall mshr miss latency +system.l2.replacements 1155 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3252 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3252 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3252 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3252 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 142 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 142 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 142 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 142 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 32 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 32 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3391 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3391 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 312801500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 312801500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3423 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3423 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990651 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990651 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 92244.618107 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 92244.618107 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3391 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3391 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 278891500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 278891500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990651 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990651 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 82244.618107 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 82244.618107 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 61 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 61 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1363 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1363 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 107997500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 107997500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1424 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1424 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.957163 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.957163 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 79235.143067 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 79235.143067 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1363 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1363 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 94367500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 94367500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.957163 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.957163 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69235.143067 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69235.143067 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2780.756713 # Cycle average of tags in use +system.l2.tags.total_refs 9849 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 5274 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.867463 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 5.330732 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 396.005107 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2379.420874 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000163 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.012085 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.072614 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.084862 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4118 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 3842 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.125671 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 84122 # Number of tag accesses +system.l2.tags.data_accesses 84122 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32512 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 304256 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 336768 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 72384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 72384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 508 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4754 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 5262 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1131 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1131 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 122478579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1146187331 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1268665909 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 122478579 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 122478579 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 272683608 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 272683608 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 272683608 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 122478579 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1146187331 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1541349517 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1131.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 508.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4754.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000033068500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 69 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 69 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 10756 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 1039 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 5262 # Number of read requests accepted +system.mem_ctrls.writeReqs 1131 # Number of write requests accepted +system.mem_ctrls.readBursts 5262 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1131 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 353 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 365 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 362 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 271 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 285 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 73 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 74 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 65 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.38 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 18.16 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 91855000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 26310000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 190517500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 17456.29 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 36206.29 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4519 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 935 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 85.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.67 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 5262 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1131 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1713 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1379 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1181 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 969 # What read queue length does an incoming req see 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see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 127 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 136 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 73 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 911 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 447.156970 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 380.953092 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 191.857435 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 76 8.34% 8.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 84 9.22% 17.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44 4.83% 22.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 36 3.95% 26.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 626 68.72% 95.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 0.66% 95.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 1.21% 96.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.22% 97.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 26 2.85% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 911 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 69 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 72.130435 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 21.099648 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.712500 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 64 92.75% 92.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-255 1 1.45% 94.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::256-383 3 4.35% 98.55% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2560-2687 1 1.45% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 69 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 69 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 69 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 69 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 336768 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 70656 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 336768 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 72384 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1268.67 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 266.17 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1268.67 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 272.68 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 11.99 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 9.91 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 2.08 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 265104500 # Total gap between requests +system.mem_ctrls.avgGap 41467.93 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 304256 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 70656 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 122478578.868753314018 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1146187330.594593048096 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 266173919.431306421757 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 508 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4754 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1131 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14431750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 176085750 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 1775795750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28408.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 37039.49 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 1570111.18 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 85.31 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2891700 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1533180 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 17892840 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 2871000 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 113860350 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 6050880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 165997710 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 625.343369 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 14815750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8840000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 241794750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3619980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1924065 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 19677840 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 2891880 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 75650400 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 38227680 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 162889605 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 613.634576 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 98761750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 8840000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 157848750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 79431 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 79431 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 79431 # number of overall hits +system.cpu.icache.overall_hits::total 79431 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 694 # number of overall misses +system.cpu.icache.overall_misses::total 694 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 52763999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52763999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 52763999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52763999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 80125 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 80125 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 80125 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 80125 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.008661 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008661 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.008661 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008661 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76028.817003 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76028.817003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76028.817003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76028.817003 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 506 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 142 # number of writebacks +system.cpu.icache.writebacks::total 142 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 177 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 517 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 517 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 517 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 517 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41303999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41303999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.006452 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006452 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.006452 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006452 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.replacements 142 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 79431 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 79431 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 694 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 52763999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52763999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 80125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 80125 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.008661 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008661 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76028.817003 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76028.817003 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 517 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 517 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 41303999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41303999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.006452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79891.680851 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 333.054457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 79948 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 517 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 154.638298 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 333.054457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.650497 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.650497 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 160767 # Number of tag accesses +system.cpu.icache.tags.data_accesses 160767 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 239461 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 239461 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 239475 # number of overall hits +system.cpu.dcache.overall_hits::total 239475 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 7247 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7247 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 7250 # number of overall misses +system.cpu.dcache.overall_misses::total 7250 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 567154805 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 567154805 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 567154805 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 567154805 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 246708 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 246708 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 246725 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 246725 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.029375 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.029375 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.029385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029385 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 78260.632676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78260.632676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 78228.248966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78228.248966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183880 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 380 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 86.858762 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 3252 # number of writebacks +system.cpu.dcache.writebacks::total 3252 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2395 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2395 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2395 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2395 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 4852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 4855 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4855 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 429090975 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 429090975 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 429412975 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 429412975 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.019667 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019667 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.019678 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019678 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 88435.897568 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88435.897568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 88447.574665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88447.574665 # average overall mshr miss latency +system.cpu.dcache.replacements 4343 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 159786 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 159786 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 2356 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2356 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 162298000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 162298000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 162142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.014530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.014530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 68887.096774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68887.096774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 934 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 934 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1422 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1422 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 110566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.008770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 77753.867792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77753.867792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 79675 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 79675 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 4884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4884 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 404634307 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 404634307 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 84559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 84559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.057758 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.057758 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 82848.957207 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82848.957207 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1461 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1461 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3423 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3423 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 318309477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 318309477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.040481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.040481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 92991.375110 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92991.375110 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 14 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 14 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 17 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 17 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.176471 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.176471 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.176471 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 352.142630 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 244410 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.341916 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 352.142630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.687779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.687779 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 498469 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 498469 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265450500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 265450500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/cactusADM/benchADM.out b/outoforder/cactusADM/benchADM.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/cactusADM/config.ini b/outoforder/cactusADM/config.ini new file mode 100644 index 000000000..6513f8a2a --- /dev/null +++ b/outoforder/cactusADM/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//data/ref/input/benchADM.par +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false 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+possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/cactusADM/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/cactusADM/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/cactusADM/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/cactusADM/config.json b/outoforder/cactusADM/config.json new file mode 100644 index 000000000..fbc980a31 --- /dev/null +++ b/outoforder/cactusADM/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + 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"eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/cactusADM/fs/proc/cpuinfo b/outoforder/cactusADM/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/cactusADM/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/cactusADM/fs/proc/stat b/outoforder/cactusADM/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/cactusADM/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/cactusADM/fs/sys/devices/system/cpu/online b/outoforder/cactusADM/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/cactusADM/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/cactusADM/fs/sys/devices/system/cpu/possible b/outoforder/cactusADM/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/cactusADM/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/cactusADM/stats.txt b/outoforder/cactusADM/stats.txt new file mode 100644 index 000000000..2c39382e8 --- /dev/null +++ b/outoforder/cactusADM/stats.txt @@ -0,0 +1,1362 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 252609000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 103208 # Simulator instruction rate (inst/s) +host_mem_usage 857128 # Number of bytes of host memory used +host_op_rate 114986 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.84 # Real time elapsed on the host +host_tick_rate 52140172 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_ops 557084 # Number of ops (including micro ops) simulated +sim_seconds 0.000253 # Number of seconds simulated +sim_ticks 252609000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 96.229669 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 65849 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68429 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4990 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 106489 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2032 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2777 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 745 # Number of indirect misses. +system.cpu.branchPred.lookups 143454 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 48990 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 36778 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 46457 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 39311 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 489 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 155 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 8882 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1047 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 482 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1142 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2175 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 802 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 405 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 778 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1763 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1667 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2306 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 2943 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 2213 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1383 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 401 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 748 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2391 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 158 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 241 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 133 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 103 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 86 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1116 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 269 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 513 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 50714 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1488 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1343 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 542 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1710 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 2219 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1018 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 476 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3158 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1859 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1912 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1999 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 2279 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3727 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1980 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 463 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 2315 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 704 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 229 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 296 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 236 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 143 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 29737 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 251 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 883 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 12429 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 353 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 181308 # number of cc regfile reads +system.cpu.cc_regfile_writes 174297 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4210 # The number of times a branch was mispredicted +system.cpu.commit.branches 113984 # Number of branches committed +system.cpu.commit.bw_lim_events 30043 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 135 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 72352 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500881 # Number of instructions committed +system.cpu.commit.committedOps 557965 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 417242 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.337269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.276335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 223446 53.55% 53.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 95268 22.83% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32570 7.81% 84.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13505 3.24% 87.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 9016 2.16% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4186 1.00% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4752 1.14% 91.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4456 1.07% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30043 7.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 417242 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 10056 # Number of function calls committed. +system.cpu.commit.int_insts 500858 # Number of committed integer instructions. +system.cpu.commit.loads 90383 # Number of loads committed +system.cpu.commit.membars 124 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 8 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 398836 71.48% 71.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 276 0.05% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 8 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 12 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 30 0.01% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 71.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 71.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 40 0.01% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90383 16.20% 87.75% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 68325 12.25% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 557965 # Class of committed instruction +system.cpu.commit.refs 158708 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 891 # Number of committed Vector instructions. +system.cpu.committedInsts 500000 # Number of Instructions Simulated +system.cpu.committedOps 557084 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.010438 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.010438 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 171402 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 798 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 63581 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 662888 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 125168 # Number of cycles decode is idle +system.cpu.decode.RunCycles 114490 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4266 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3012 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 13367 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 143454 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 107850 # Number of cache lines fetched +system.cpu.fetch.Cycles 268840 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2503 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 627802 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10092 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.283944 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 154710 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 80310 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.242633 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 428693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.633558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.684815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 272898 63.66% 63.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 19865 4.63% 68.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36528 8.52% 76.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13111 3.06% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12791 2.98% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 14005 3.27% 86.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12134 2.83% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4840 1.13% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 42521 9.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 428693 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 76526 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4895 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 122244 # Number of branches executed +system.cpu.iew.exec_nop 1102 # number of nop insts executed +system.cpu.iew.exec_rate 1.198045 # Inst execution rate +system.cpu.iew.exec_refs 172591 # number of memory reference insts executed +system.cpu.iew.exec_stores 73509 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 8477 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 101973 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1202 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 77636 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 630849 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 99082 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5639 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 605275 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2515 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4266 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2569 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 86 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1403 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 29 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 344 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11575 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 9296 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3176 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1719 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 549816 # num instructions consuming a value +system.cpu.iew.wb_count 600201 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.582462 # average fanout of values written-back +system.cpu.iew.wb_producers 320247 # num instructions producing a value +system.cpu.iew.wb_rate 1.188002 # insts written-back per cycle +system.cpu.iew.wb_sent 602862 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 703554 # number of integer regfile reads +system.cpu.int_regfile_writes 431478 # number of integer regfile writes +system.cpu.ipc 0.989670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.989670 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 435592 71.30% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 296 0.05% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 8 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 12 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 31 0.01% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 18 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 47 0.01% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 71.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 100200 16.40% 87.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 74658 12.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 610918 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 6615 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010828 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2595 39.23% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.05% 39.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.03% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 39.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1904 28.78% 68.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2111 31.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 616493 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1655418 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 599258 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 701196 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 629578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 610918 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 169 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 72580 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 310 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 34 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 43964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 428693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.425071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.893801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 205459 47.93% 47.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 73499 17.14% 65.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 50866 11.87% 76.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34810 8.12% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25924 6.05% 91.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17451 4.07% 95.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10250 2.39% 97.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4666 1.09% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5768 1.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 428693 # Number of insts issued each cycle +system.cpu.iq.rate 1.209214 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1031 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2032 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 943 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1169 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2896 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3780 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 101973 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77636 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 479264 # number of misc regfile reads +system.cpu.misc_regfile_writes 509 # number of misc regfile writes +system.cpu.numCycles 505219 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 11207 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 561605 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 95 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 131776 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 254 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 984962 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 646848 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 651140 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 121638 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 3816 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4266 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 14145 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 89434 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 752942 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 145661 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 8105 # count of serializing insts renamed +system.cpu.rename.skidInsts 56085 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 170 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1073 # Number of vector rename lookups +system.cpu.rob.rob_reads 1017204 # The number of ROB reads +system.cpu.rob.rob_writes 1272290 # The number of ROB writes +system.cpu.timesIdled 1465 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 955 # number of vector regfile reads +system.cpu.vec_regfile_writes 178 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1719 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2482 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 5922 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1117 # Transaction distribution +system.membus.trans_dist::ReadExReq 536 # Transaction distribution +system.membus.trans_dist::ReadExResp 536 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1117 # Transaction distribution +system.membus.trans_dist::InvalidateReq 66 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3372 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 105792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 105792 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1719 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1719 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1719 # Request fanout histogram +system.membus.reqLayer0.occupancy 2133500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 8781000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2814 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 304 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2040 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 138 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 560 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 560 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2503 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 311 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 66 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 66 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 7046 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 2316 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 9362 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 290752 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 75200 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 365952 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3440 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000291 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.017050 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3439 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3440 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 5305000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1339999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3754500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1601 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 120 # number of demand (read+write) hits +system.l2.demand_hits::total 1721 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1601 # number of overall hits +system.l2.overall_hits::.cpu.data 120 # number of overall hits +system.l2.overall_hits::total 1721 # number of overall hits +system.l2.demand_misses::.cpu.inst 902 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 751 # number of demand (read+write) misses +system.l2.demand_misses::total 1653 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 902 # number of overall misses +system.l2.overall_misses::.cpu.data 751 # number of overall misses +system.l2.overall_misses::total 1653 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 70709000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 59990500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 130699500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 70709000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 59990500 # number of overall miss cycles +system.l2.overall_miss_latency::total 130699500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2503 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 871 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3374 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2503 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 871 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3374 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.360368 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.862227 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.489923 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.360368 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.862227 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.489923 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78391.352550 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79880.825566 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79068.058076 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78391.352550 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79880.825566 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79068.058076 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 902 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 751 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1653 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 902 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 751 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1653 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 61689000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 52480500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 114169500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 61689000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 52480500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 114169500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.360368 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.862227 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.489923 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.360368 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.862227 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.489923 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68391.352550 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69880.825566 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69068.058076 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68391.352550 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69880.825566 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69068.058076 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 304 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 304 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 304 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 304 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2040 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2040 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2040 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2040 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 24 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 24 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 536 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 536 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 42152500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 42152500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 560 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 560 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.957143 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.957143 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78642.723881 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78642.723881 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 536 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 536 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 36792500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 36792500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.957143 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.957143 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68642.723881 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68642.723881 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1601 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1601 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 902 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 902 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 70709000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 70709000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2503 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2503 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.360368 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.360368 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78391.352550 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78391.352550 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 902 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 902 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 61689000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 61689000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.360368 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.360368 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68391.352550 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68391.352550 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 96 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 96 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 215 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 17838000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 17838000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 311 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 311 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.691318 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.691318 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 82967.441860 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 82967.441860 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 215 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 15688000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 15688000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.691318 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.691318 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72967.441860 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 72967.441860 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 66 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 66 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 66 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 66 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 66 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 66 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1249000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1249000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18924.242424 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18924.242424 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1267.818811 # Cycle average of tags in use +system.l2.tags.total_refs 5855 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1695 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.454277 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 22.433470 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 731.698974 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 513.686366 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000685 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.022330 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.015676 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.038691 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1695 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1532 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.051727 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 49063 # Number of tag accesses +system.l2.tags.data_accesses 49063 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 57728 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 48064 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 105792 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 57728 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 902 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 751 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1653 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 228527091 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 190270339 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 418797430 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 228527091 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 228527091 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 228527091 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 190270339 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 418797430 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 902.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 751.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3320 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1653 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1653 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 116 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 78 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 41 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 16 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 195 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 167 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 145 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 180 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 120 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 85 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.25 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15156000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 8265000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 46149750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9168.78 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27918.78 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1304 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.89 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1653 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1110 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 381 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 125 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming 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write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 348 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 303.816092 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 189.522898 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.791722 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 111 31.90% 31.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 100 28.74% 60.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 38 10.92% 71.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 22 6.32% 77.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 4.60% 82.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.74% 86.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 14 4.02% 90.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.44% 91.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 29 8.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 348 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 105792 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 105792 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 418.80 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 418.80 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.27 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.27 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 251765500 # Total gap between requests +system.mem_ctrls.avgGap 152308.23 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 57728 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 48064 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 228527091.275449424982 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 190270338.744858652353 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 902 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 751 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 24576750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 21573000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27246.95 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28725.70 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.89 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1320900 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 702075 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 5826240 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 19668480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 81818940 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 28102080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 137438715 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 544.076874 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 72348500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8320000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 171940500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1170960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 618585 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5976180 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 19668480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 96119670 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 16059360 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 139613235 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 552.685118 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 40915000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 8320000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 203374000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 104947 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 104947 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 104947 # number of overall hits +system.cpu.icache.overall_hits::total 104947 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2901 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2901 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2901 # number of overall misses +system.cpu.icache.overall_misses::total 2901 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 109040999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109040999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 109040999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109040999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 107848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 107848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107848 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.026899 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.026899 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.026899 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.026899 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 37587.383316 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37587.383316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 37587.383316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37587.383316 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 607 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.583333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2040 # number of writebacks +system.cpu.icache.writebacks::total 2040 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 398 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 398 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 398 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2503 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2503 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2503 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2503 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 91375500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 91375500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 91375500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 91375500 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.023209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.023209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.023209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.023209 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 36506.392329 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36506.392329 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 36506.392329 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36506.392329 # average overall mshr miss latency +system.cpu.icache.replacements 2040 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 104947 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 104947 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2901 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 109040999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109040999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 107848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.026899 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.026899 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 37587.383316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37587.383316 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 398 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 398 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 2503 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2503 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 91375500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 91375500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.023209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.023209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 36506.392329 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36506.392329 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 405.005786 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107450 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2503 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 42.928486 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 405.005786 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.791027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.791027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 463 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 358 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.904297 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 218199 # Number of tag accesses +system.cpu.icache.tags.data_accesses 218199 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 161990 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161990 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 162278 # number of overall hits +system.cpu.dcache.overall_hits::total 162278 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 2977 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2977 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 2979 # number of overall misses +system.cpu.dcache.overall_misses::total 2979 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 197449428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 197449428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 197449428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 197449428 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 164967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 164967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 165257 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165257 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.018046 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018046 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.018026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018026 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 66324.967417 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66324.967417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 66280.439074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66280.439074 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3137 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.010204 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 304 # number of writebacks +system.cpu.dcache.writebacks::total 304 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2050 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2050 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2050 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 929 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 929 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 64262968 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 64262968 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 64439468 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 64439468 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.005619 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005619 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.005622 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005622 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 69323.590076 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69323.590076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 69364.335845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69364.335845 # average overall mshr miss latency +system.cpu.dcache.replacements 442 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 96041 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 96041 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 691 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 691 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 39702500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39702500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 96732 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 96732 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.007143 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007143 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 57456.584660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57456.584660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 390 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 390 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 301 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 18980500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18980500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.003112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 63058.139535 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63058.139535 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 65937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 65937 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 2233 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2233 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 156060955 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 156060955 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 68170 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 68170 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.032756 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032756 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 69888.470667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69888.470667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1660 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1660 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 573 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 573 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 43649495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 43649495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.008405 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008405 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 76177.129145 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76177.129145 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 288 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 288 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 290 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 290 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.006897 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.006897 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.006897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.006897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 12 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 12 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 53 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 53 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1685973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1685973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 65 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 65 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.815385 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.815385 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31810.811321 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31810.811321 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 53 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 53 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1632973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1632973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.815385 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.815385 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30810.811321 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30810.811321 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 134 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 134 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 142 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 142 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.056338 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056338 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 21750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 8 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 166000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.056338 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056338 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 20750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 124 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 124 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 413.808412 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 937 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 174.464248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 413.808412 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.808220 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.808220 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.966797 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 331983 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 331983 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 252609000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 252609000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/calculix/beampic.log b/outoforder/calculix/beampic.log new file mode 100644 index 000000000..f2915065d --- /dev/null +++ b/outoforder/calculix/beampic.log @@ -0,0 +1,2 @@ + *ERROR in openfile: input file /data/ref/input/hyperviscoplastic.inp.inp + does not exist diff --git a/outoforder/calculix/config.ini b/outoforder/calculix/config.ini new file mode 100644 index 000000000..ce86ebe85 --- /dev/null +++ b/outoforder/calculix/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 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system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true 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+id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross -i /data/ref/input/hyperviscoplastic.inp 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"PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/calculix/fs/proc/cpuinfo b/outoforder/calculix/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/calculix/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/calculix/fs/proc/stat b/outoforder/calculix/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/calculix/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/calculix/fs/sys/devices/system/cpu/online b/outoforder/calculix/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/calculix/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/calculix/fs/sys/devices/system/cpu/possible b/outoforder/calculix/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/calculix/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/calculix/stats.txt b/outoforder/calculix/stats.txt new file mode 100644 index 000000000..b18091568 --- /dev/null +++ b/outoforder/calculix/stats.txt @@ -0,0 +1,1359 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 56861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 45939 # Simulator instruction rate (inst/s) +host_mem_usage 856744 # Number of bytes of host memory used +host_op_rate 55521 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.51 # Real time elapsed on the host +host_tick_rate 110960481 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 23532 # Number of instructions simulated +sim_ops 28450 # Number of ops (including micro ops) simulated +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56861000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.498652 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 3688 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4821 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8019 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 34 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 465 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 431 # Number of indirect misses. +system.cpu.branchPred.lookups 11185 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2360 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 1810 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2273 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 1897 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 124 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 31 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 112 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 37 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 2916 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 558 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 93 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 66 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 347 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 15 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 859 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 8625 # number of cc regfile reads +system.cpu.cc_regfile_writes 8679 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 834 # The number of times a branch was mispredicted +system.cpu.commit.branches 5605 # Number of branches committed +system.cpu.commit.bw_lim_events 1239 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 54 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 23588 # Number of instructions committed +system.cpu.commit.committedOps 28506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 39891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.714597 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.779156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30973 77.64% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3276 8.21% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1731 4.34% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 879 2.20% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 598 1.50% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 551 1.38% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 436 1.09% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208 0.52% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1239 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39891 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 490 # Number of function calls committed. +system.cpu.commit.int_insts 25886 # Number of committed integer instructions. +system.cpu.commit.loads 4020 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 19666 68.99% 69.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.15% 69.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.01% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.09% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 26 0.09% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.10% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 30 0.11% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 4020 14.10% 83.66% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4658 16.34% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 28506 # Class of committed instruction +system.cpu.commit.refs 8678 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 413 # Number of committed Vector instructions. +system.cpu.committedInsts 23532 # Number of Instructions Simulated +system.cpu.committedOps 28450 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.832696 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.832696 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 13004 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 460 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3802 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 47302 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 19734 # Number of cycles decode is idle +system.cpu.decode.RunCycles 7777 # Number of cycles decode is running +system.cpu.decode.SquashCycles 869 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1546 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 710 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 11185 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6474 # Number of cache lines fetched +system.cpu.fetch.Cycles 17733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 47366 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2642 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.098353 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22801 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4581 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.416503 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 42094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.317646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 31882 75.74% 75.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1052 2.50% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1015 2.41% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 717 1.70% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1034 2.46% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 1.74% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1010 2.40% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 843 2.00% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3810 9.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 42094 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 71629 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 997 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 6864 # Number of branches executed +system.cpu.iew.exec_nop 122 # number of nop insts executed +system.cpu.iew.exec_rate 0.326908 # Inst execution rate +system.cpu.iew.exec_refs 11357 # number of memory reference insts executed +system.cpu.iew.exec_stores 5453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2304 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 6339 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 89 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6321 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 42090 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 5904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1114 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 37177 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 869 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1371 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 86 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1663 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 188 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 31510 # num instructions consuming a value +system.cpu.iew.wb_count 35773 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.563504 # average fanout of values written-back +system.cpu.iew.wb_producers 17756 # num instructions producing a value +system.cpu.iew.wb_rate 0.314563 # insts written-back per cycle +system.cpu.iew.wb_sent 36351 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 41177 # number of integer regfile reads +system.cpu.int_regfile_writes 25395 # number of integer regfile writes +system.cpu.ipc 0.206924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.206924 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 8 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 26234 68.51% 68.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.11% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.01% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 28 0.07% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.07% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 32 0.08% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.09% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 6191 16.17% 85.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5691 14.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 38291 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 555 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189 34.05% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.18% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.36% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 118 21.26% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 245 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 38309 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 118302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 35311 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 54736 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 41879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 38291 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13517 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 42094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.909655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29929 71.10% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2997 7.12% 78.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2546 6.05% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2071 4.92% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1657 3.94% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1133 2.69% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 951 2.26% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 490 1.16% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 320 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42094 # Number of insts issued each cycle +system.cpu.iq.rate 0.336704 # Inst issue rate +system.cpu.iq.vec_alu_accesses 529 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1074 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 462 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 769 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 6339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6321 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 28736 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 113723 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3701 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 26781 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 202 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 20563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 64176 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 44669 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 42396 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 7626 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 751 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 869 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1430 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15615 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 49589 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 7905 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 302 # count of serializing insts renamed +system.cpu.rename.skidInsts 3721 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 688 # Number of vector rename lookups +system.cpu.rob.rob_reads 80411 # The number of ROB reads +system.cpu.rob.rob_writes 86307 # The number of ROB writes +system.cpu.timesIdled 663 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 512 # number of vector regfile reads +system.cpu.vec_regfile_writes 137 # number of vector regfile writes +system.cpu.workload.numSyscalls 17 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1251 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 502 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1817 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1026 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution +system.membus.trans_dist::ReadExResp 168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1027 # Transaction distribution +system.membus.trans_dist::InvalidateReq 56 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1251 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1251 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1251 # Request fanout histogram +system.membus.reqLayer0.occupancy 1533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 6321500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1089 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 27 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 440 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 33 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 171 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 171 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 925 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 165 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 56 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 56 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2289 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 844 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3133 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 87296 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 23232 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 110528 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001519 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.038954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1315 99.85% 99.85% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.15% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1375500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 532000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1386000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 42 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 66 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 42 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 66 # number of overall hits +system.l2.demand_misses::.cpu.inst 883 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 312 # number of demand (read+write) misses +system.l2.demand_misses::total 1195 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 883 # number of overall misses +system.l2.overall_misses::.cpu.data 312 # number of overall misses +system.l2.overall_misses::total 1195 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 68520500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 25782500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 94303000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 68520500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 25782500 # number of overall miss cycles +system.l2.overall_miss_latency::total 94303000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 925 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 336 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1261 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 925 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 336 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1261 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.954595 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.928571 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.947661 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.954595 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.928571 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.947661 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 883 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 312 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1195 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 883 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 312 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1195 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 59700500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 22662500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 82363000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 59700500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 22662500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 82363000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.947661 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.947661 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 27 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 27 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 440 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 440 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 440 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 440 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 168 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 168 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 56 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 56 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19000 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19000 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 638.816237 # Cycle average of tags in use +system.l2.tags.total_refs 1760 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1196 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.471572 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 0.787737 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 434.030626 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 203.997874 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000024 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013246 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006226 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.019495 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1196 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1019 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.036499 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 15732 # Number of tag accesses +system.l2.tags.data_accesses 15732 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56448 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 19968 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 76416 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 882 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 312 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1194 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 992736674 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 351172157 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1343908830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 992736674 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 351172157 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1343908830 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 883.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 312.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000542000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2358 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1195 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1195 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 126 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 91 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.77 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10859000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 5975000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 33265250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9087.03 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27837.03 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 963 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.59 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1195 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 132 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 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# What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 225 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 336.213333 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 219.600202 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.995257 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 57 25.33% 25.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 62 27.56% 52.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 32 14.22% 67.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 7.56% 74.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 4.44% 79.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 15 6.67% 85.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.67% 88.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 3.56% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 18 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 225 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 76480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 76480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1345.03 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1345.03 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.51 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.51 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 56833500 # Total gap between requests +system.mem_ctrls.avgGap 47559.41 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 19968 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 993862225.426918268204 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 351172156.662738919258 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 883 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 312 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23476250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 9789000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26586.92 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31375.00 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 849660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4448220 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 24871380 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 890400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 35806155 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 629.713776 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 2123000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 52918000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 806820 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 4076940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 25828980 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 84000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 35509080 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 624.489193 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 11500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 55029500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 5295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 5295 # number of overall hits +system.cpu.icache.overall_hits::total 5295 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1177 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1177 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1177 # number of overall misses +system.cpu.icache.overall_misses::total 1177 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 86127996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86127996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 86127996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86127996 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 6472 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6472 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 6472 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6472 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.181860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.181860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.181860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.181860 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1005 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 440 # number of writebacks +system.cpu.icache.writebacks::total 440 # number of writebacks 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overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70369497 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.142923 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.142923 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.142923 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.142923 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 76075.131892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76075.131892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 76075.131892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76075.131892 # average overall mshr miss latency +system.cpu.icache.replacements 440 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 6472 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6472 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.181860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.181860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 73175.867460 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73175.867460 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 252 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 70369497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70369497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.142923 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142923 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 76075.131892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76075.131892 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 317.135421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6219 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 924 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.730519 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 317.135421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13868 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13868 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 8767 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 8767 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 8789 # number of overall hits +system.cpu.dcache.overall_hits::total 8789 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1306 # number of overall misses +system.cpu.dcache.overall_misses::total 1306 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 85332929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85332929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 85332929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85332929 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 10069 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 10069 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 10095 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 10095 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.129308 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129308 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.129371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129371 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 65539.884025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65539.884025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 65339.149311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65339.149311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3235 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.010204 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 27 # number of writebacks +system.cpu.dcache.writebacks::total 27 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 915 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 915 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 915 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 915 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 391 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 391 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 27768467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27768467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 28171467 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28171467 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71753.144703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71753.144703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72049.787724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72049.787724 # average overall mshr miss latency +system.cpu.dcache.replacements 60 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 5042 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 397 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 26851000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26851000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 5439 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 5439 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.072991 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.072991 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 67634.760705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67634.760705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 223.007274 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 9264 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.632653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 223.007274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 332 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.648438 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 20752 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 20752 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 56861000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/gobmk/capture.out b/outoforder/gobmk/capture.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/gobmk/config.ini b/outoforder/gobmk/config.ini new file mode 100644 index 000000000..01d99479d --- /dev/null +++ b/outoforder/gobmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true 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+[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState 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+cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/gobmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/gobmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/gobmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/gobmk/config.json b/outoforder/gobmk/config.json new file mode 100644 index 000000000..20862a3df --- /dev/null +++ b/outoforder/gobmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "outoforder/gobmk/fs/proc" + ], + "eventq_index": 0, + "cxx_class": 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"system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/gobmk/fs/proc/cpuinfo b/outoforder/gobmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/gobmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/gobmk/fs/proc/stat b/outoforder/gobmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/gobmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/gobmk/fs/sys/devices/system/cpu/online b/outoforder/gobmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/gobmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/gobmk/fs/sys/devices/system/cpu/possible b/outoforder/gobmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/gobmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/gobmk/stats.txt b/outoforder/gobmk/stats.txt new file mode 100644 index 000000000..4ed1756ae --- /dev/null +++ b/outoforder/gobmk/stats.txt @@ -0,0 +1,1342 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 241088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 111859 # Simulator instruction rate (inst/s) +host_mem_usage 857644 # Number of bytes of host memory used +host_op_rate 112692 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.47 # Real time elapsed on the host +host_tick_rate 53931755 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500004 # Number of instructions simulated +sim_ops 503758 # Number of ops (including micro ops) simulated +sim_seconds 0.000241 # Number of seconds simulated +sim_ticks 241088500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.448447 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 86006 # Number of BTB hits +system.cpu.branchPred.BTBLookups 86483 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 844 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 87511 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 134 # Number of indirect misses. +system.cpu.branchPred.lookups 95963 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 9619 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 70864 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 4842 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 75641 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 65 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 763 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 46 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 40 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 275 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 136 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 60 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 145 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 215 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 206 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 108 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 36 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 61 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 62 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 79 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 269 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 10 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 75734 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 285 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 40 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 64 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 301 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 52 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 248 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 125 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 68 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 212 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 183 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 270 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 165 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 329 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 82 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 95 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 3403 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 40 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 100 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2727 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 248871 # number of cc regfile reads +system.cpu.cc_regfile_writes 249177 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 649 # The number of times a branch was mispredicted +system.cpu.commit.branches 87811 # Number of branches committed +system.cpu.commit.bw_lim_events 10637 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 24177 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500215 # Number of instructions committed +system.cpu.commit.committedOps 503969 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 447880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.125232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.187481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 318303 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 33833 7.55% 78.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19206 4.29% 82.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11938 2.67% 85.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4768 1.06% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4302 0.96% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44019 9.83% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 874 0.20% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10637 2.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 447880 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2417 # Number of function calls committed. +system.cpu.commit.int_insts 423441 # Number of committed integer instructions. +system.cpu.commit.loads 144014 # Number of loads committed +system.cpu.commit.membars 16 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 283767 56.31% 56.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 449 0.09% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 56.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 16 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 56.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 144014 28.58% 84.99% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 75669 15.01% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 503969 # Class of committed instruction +system.cpu.commit.refs 219683 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 248 # Number of committed Vector instructions. +system.cpu.committedInsts 500004 # Number of Instructions Simulated +system.cpu.committedOps 503758 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.964348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.964348 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 344022 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 84517 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 536132 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 29733 # Number of cycles decode is idle +system.cpu.decode.RunCycles 57180 # Number of cycles decode is running +system.cpu.decode.SquashCycles 828 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 670 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 19562 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 95963 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15255 # Number of cache lines fetched +system.cpu.fetch.Cycles 426567 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 545858 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2046 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.199020 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 23707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 88734 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.132067 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 451325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.221964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.365251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 344814 76.40% 76.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4126 0.91% 77.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 12872 2.85% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1334 0.30% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 14717 3.26% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 735 0.16% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61867 13.71% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2994 0.66% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7866 1.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 451325 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 30853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 729 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 91059 # Number of branches executed +system.cpu.iew.exec_nop 257 # number of nop insts executed +system.cpu.iew.exec_rate 1.116789 # Inst execution rate +system.cpu.iew.exec_refs 242856 # number of memory reference insts executed +system.cpu.iew.exec_stores 78361 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 3112 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 149919 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 78904 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 528180 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 164495 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 538491 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 17058 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 828 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 17072 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 5155 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 5889 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 3227 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 446 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 634199 # num instructions consuming a value +system.cpu.iew.wb_count 520364 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.534402 # average fanout of values written-back +system.cpu.iew.wb_producers 338917 # num instructions producing a value +system.cpu.iew.wb_rate 1.079195 # insts written-back per cycle +system.cpu.iew.wb_sent 522939 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 685587 # number of integer regfile reads +system.cpu.int_regfile_writes 355992 # number of integer regfile writes +system.cpu.ipc 1.036970 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.036970 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 295604 54.81% 54.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 501 0.09% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 25 0.00% 54.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 54.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 54.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 54.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 164662 30.53% 85.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 78498 14.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 539352 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 8160 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015129 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 123 1.51% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.02% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7959 97.54% 99.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 75 0.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 547199 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1537620 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 520088 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 551651 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 527890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 539352 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 24116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 15028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 451325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.195041 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.102010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 312694 69.28% 69.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20244 4.49% 73.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17623 3.90% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22255 4.93% 82.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 27482 6.09% 88.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 25400 5.63% 94.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2766 0.61% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19315 4.28% 99.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3546 0.79% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 451325 # Number of insts issued each cycle +system.cpu.iq.rate 1.118574 # Inst issue rate +system.cpu.iq.vec_alu_accesses 308 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 619 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 276 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 424 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2492 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2394 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 149919 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 78904 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 435580 # number of misc regfile reads +system.cpu.misc_regfile_writes 65 # number of misc regfile writes +system.cpu.numCycles 482178 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 21108 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 583420 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3317 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 39514 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 3789 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 945402 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 531386 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 614919 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 66726 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 311187 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 828 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 318950 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 31422 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 679556 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4199 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.skidInsts 107617 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 409 # Number of vector rename lookups +system.cpu.rob.rob_reads 963543 # The number of ROB reads +system.cpu.rob.rob_writes 1059798 # The number of ROB writes +system.cpu.timesIdled 311 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 318 # number of vector regfile reads +system.cpu.vec_regfile_writes 92 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 11708 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 10918 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 22685 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 464 # Transaction distribution +system.membus.trans_dist::ReadExReq 8419 # Transaction distribution +system.membus.trans_dist::ReadExResp 8419 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 464 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 20591 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 20591 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 568512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 568512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 11708 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 11708 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 11708 # Request fanout histogram +system.membus.reqLayer0.occupancy 15938000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 45405500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 504 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 10790 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 51 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 77 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 8438 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 8435 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 385 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 119 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2825 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 821 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 33628 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 34449 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 1238016 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1265920 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 11767 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000085 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.009219 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 11766 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 11767 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 22183500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 9.2 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 14243500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 577500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 8 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 48 # number of demand (read+write) hits +system.l2.demand_hits::total 56 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 8 # number of overall hits +system.l2.overall_hits::.cpu.data 48 # number of overall hits +system.l2.overall_hits::total 56 # number of overall hits +system.l2.demand_misses::.cpu.inst 377 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 8509 # number of demand (read+write) misses +system.l2.demand_misses::total 8886 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 377 # number of overall misses +system.l2.overall_misses::.cpu.data 8509 # number of overall misses +system.l2.overall_misses::total 8886 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 30084500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 646495500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 676580000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 30084500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 646495500 # number of overall miss cycles +system.l2.overall_miss_latency::total 676580000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 385 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 8557 # number of demand (read+write) accesses +system.l2.demand_accesses::total 8942 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 385 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 8557 # number of overall (read+write) accesses +system.l2.overall_accesses::total 8942 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.979221 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.994391 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.993737 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.979221 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.994391 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.993737 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75977.846986 # average overall miss latency +system.l2.demand_avg_miss_latency::total 76139.995499 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75977.846986 # average overall miss latency +system.l2.overall_avg_miss_latency::total 76139.995499 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 377 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 8509 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 8886 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 377 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 8509 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 8886 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 26314500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 561435500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 587750000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 26314500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 561435500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 587750000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.994391 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.994391 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65981.372664 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 66143.371596 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65981.372664 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 66143.371596 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 10790 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 10790 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 10790 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 10790 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 51 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 51 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 51 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 51 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 16 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 16 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 8422 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 8422 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 638706000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 638706000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 8438 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 8438 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.998104 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.998104 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75837.805747 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75837.805747 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 8422 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 8422 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 554516000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 554516000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.998104 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.998104 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65841.367846 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65841.367846 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19206.725664 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19206.725664 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 5962.309136 # Cycle average of tags in use +system.l2.tags.total_refs 19856 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 11708 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.695934 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 2359.447010 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 348.161881 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 3254.700246 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.072005 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.010625 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.099326 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.181955 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 11708 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 472 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4212 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 7024 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.357300 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 193180 # Number of tag accesses +system.l2.tags.data_accesses 193180 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 24128 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 544384 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 568512 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 377 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 8506 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 8883 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 100079431 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2258025580 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2358105011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 100079431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 100079431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 100079431 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2258025580 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2358105011 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 377.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 8506.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000585000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 17774 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 8883 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 8883 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 610 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 543 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 523 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 584 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 526 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 535 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 525 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 516 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 518 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 583 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 601 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 544 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 572 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 656 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 481 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.93 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 54715250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 44415000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 221271500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6159.55 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24909.55 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 8182 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.11 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 8883 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2427 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 2325 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 2480 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1643 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 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see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 700 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 811.062857 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 630.289698 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 363.315761 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 61 8.71% 8.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 7.71% 16.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 31 4.43% 20.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 1.29% 22.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 2.71% 24.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 0.86% 25.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 1.57% 27.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 0.71% 28.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 504 72.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 700 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 568512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 568512 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2358.11 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2358.11 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 18.42 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 18.42 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 240986000 # Total gap between requests +system.mem_ctrls.avgGap 27128.90 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 24128 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 544384 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 100079431.412116304040 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2258025579.818199634552 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 377 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 8506 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 10808750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 210462750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28670.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24742.86 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 92.11 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2620380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1388970 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 32279940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 18439200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 62792340 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 39700320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 157221150 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 652.130442 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 101176000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 7800000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 132112500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 2384760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1267530 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 31144680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 18439200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 58713420 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 43135200 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 155084790 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 643.269131 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 110178250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 7800000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 123110250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 14752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 14752 # number of overall hits +system.cpu.icache.overall_hits::total 14752 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 503 # number of overall misses +system.cpu.icache.overall_misses::total 503 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 38236998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38236998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 38236998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38236998 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 15255 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15255 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 15255 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15255 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.032973 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032973 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.032973 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032973 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76017.888668 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76017.888668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76017.888668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76017.888668 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 51 # number of writebacks +system.cpu.icache.writebacks::total 51 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 118 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 385 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 385 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 385 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 385 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 30755499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30755499 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 311.300510 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15137 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 385 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39.316883 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 311.300510 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.608009 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.608009 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30895 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 154911 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 154911 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 154916 # number of overall hits +system.cpu.dcache.overall_hits::total 154916 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 69562 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 69562 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 69564 # number of overall misses +system.cpu.dcache.overall_misses::total 69564 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 4335251869 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4335251869 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 4335251869 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4335251869 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 224473 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 224473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 224480 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 224480 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.309890 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.309890 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.309890 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.309890 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 62322.128015 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62322.128015 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62320.336223 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62320.336223 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 297663 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5493 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.189514 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 10790 # number of writebacks +system.cpu.dcache.writebacks::total 10790 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 58182 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 58182 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 58182 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 58182 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 11380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11380 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 11382 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 11382 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 750689510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 750689510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 750888510 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 750888510 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.050697 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050697 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.050704 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050704 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 65965.686292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65965.686292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 65971.578809 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65971.578809 # average overall mshr miss latency +system.cpu.dcache.replacements 10867 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 148478 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148478 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 148820 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148820 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.002298 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002298 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 66397 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 66397 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 4225005353 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4225005353 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 72830 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 72830 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.911671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.911671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63632.473651 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63632.473651 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 57957 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57957 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 8440 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8440 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 652636494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 652636494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.115886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.115886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 77326.598815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77326.598815 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 474.402124 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 166329 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11379 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.617190 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 474.402124 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.926567 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.926567 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 460407 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 460407 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 241088500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 241088500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/h264ref/config.ini b/outoforder/h264ref/config.ini new file mode 100644 index 000000000..4ffc2234d --- /dev/null +++ b/outoforder/h264ref/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 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power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + 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+clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//exe/h264ref_base.amd64-armcross -d /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//exe/h264ref_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=foreman_ref_encoder_baseline.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain 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+[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 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"system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/h264ref/foreman_ref_encoder_baseline.out b/outoforder/h264ref/foreman_ref_encoder_baseline.out new file mode 100644 index 000000000..52c97f4e8 --- /dev/null +++ b/outoforder/h264ref/foreman_ref_encoder_baseline.out @@ -0,0 +1,3 @@ +Setting Default Parameters... +Parsing Configfile /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg..................................................................................................... + diff --git a/outoforder/h264ref/fs/proc/cpuinfo b/outoforder/h264ref/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/h264ref/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/h264ref/fs/proc/stat b/outoforder/h264ref/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/h264ref/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/h264ref/fs/sys/devices/system/cpu/online b/outoforder/h264ref/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/h264ref/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/h264ref/fs/sys/devices/system/cpu/possible b/outoforder/h264ref/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/h264ref/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/h264ref/stats.txt b/outoforder/h264ref/stats.txt new file mode 100644 index 000000000..6f44c27c9 --- /dev/null +++ b/outoforder/h264ref/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 182784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 136538 # Simulator instruction rate (inst/s) +host_mem_usage 854052 # Number of bytes of host memory used +host_op_rate 152863 # Simulator op (including micro ops) rate (op/s) +host_seconds 2.97 # Real time elapsed on the host +host_tick_rate 61620506 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 404970 # Number of instructions simulated +sim_ops 453431 # Number of ops (including micro ops) simulated +sim_seconds 0.000183 # Number of seconds simulated +sim_ticks 182784500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 96.009202 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 69695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 72592 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 8 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4076 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 102227 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 418 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1049 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 631 # Number of indirect misses. +system.cpu.branchPred.lookups 136457 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 66625 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 18738 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 44665 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 40698 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 57 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 9904 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1003 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 714 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 662 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2209 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 654 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 708 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 4799 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1081 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1832 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 825 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1857 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1058 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1044 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 424 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 757 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1046 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 773 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 950 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1657 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1011 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 156 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 335 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 46618 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 786 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3277 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 416 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 539 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 6416 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 599 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2356 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 888 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 887 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1797 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 4845 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1705 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1913 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 912 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1087 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 920 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1393 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1055 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 775 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1090 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1709 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 34908 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 168 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 947 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 8368 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 121 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 188694 # number of cc regfile reads +system.cpu.cc_regfile_writes 181404 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3081 # The number of times a branch was mispredicted +system.cpu.commit.branches 113779 # Number of branches committed +system.cpu.commit.bw_lim_events 9761 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 47211 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 405226 # Number of instructions committed +system.cpu.commit.committedOps 453687 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 282466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.606165 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.996099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108243 38.32% 38.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 63776 22.58% 60.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49902 17.67% 78.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20051 7.10% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13675 4.84% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 10042 3.56% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2156 0.76% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4860 1.72% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 9761 3.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 282466 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 7544 # Number of function calls committed. +system.cpu.commit.int_insts 391118 # Number of committed integer instructions. +system.cpu.commit.loads 53629 # Number of loads committed +system.cpu.commit.membars 246 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 11 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 373891 82.41% 82.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 128 0.03% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 4 0.00% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 9 0.00% 82.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 9 0.00% 82.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 375 0.08% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 82.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 33 0.01% 82.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 82.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 43 0.01% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 44 0.01% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 42 0.01% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 82.57% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 53629 11.82% 94.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 25468 5.61% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 453687 # Class of committed instruction +system.cpu.commit.refs 79097 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2794 # Number of committed Vector instructions. +system.cpu.committedInsts 404970 # Number of Instructions Simulated +system.cpu.committedOps 453431 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.902709 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.902709 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 46298 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1088 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 68885 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 519819 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 122615 # Number of cycles decode is idle +system.cpu.decode.RunCycles 115377 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3133 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3602 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 2711 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 136457 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 92422 # Number of cache lines fetched +system.cpu.fetch.Cycles 152260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 485690 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 489 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 8418 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.373272 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 132898 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 78481 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.328583 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 290134 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.872717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.680965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 166227 57.29% 57.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 18234 6.28% 63.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23702 8.17% 71.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4941 1.70% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13532 4.66% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24530 8.45% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3154 1.09% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19336 6.66% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 16478 5.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 290134 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 75436 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3352 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 119652 # Number of branches executed +system.cpu.iew.exec_nop 412 # number of nop insts executed +system.cpu.iew.exec_rate 1.331813 # Inst execution rate +system.cpu.iew.exec_refs 90712 # number of memory reference insts executed +system.cpu.iew.exec_stores 27232 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 15288 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 61281 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 404 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 578 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 28437 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 500946 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 63480 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 486871 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 6948 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3133 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7222 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 480 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 655 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 7652 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2969 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2195 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 456972 # num instructions consuming a value +system.cpu.iew.wb_count 479571 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.549522 # average fanout of values written-back +system.cpu.iew.wb_producers 251116 # num instructions producing a value +system.cpu.iew.wb_rate 1.311845 # insts written-back per cycle +system.cpu.iew.wb_sent 480595 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 518416 # number of integer regfile reads +system.cpu.int_regfile_writes 336713 # number of integer regfile writes +system.cpu.ipc 1.107777 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.107777 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 92 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 397903 81.00% 81.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 141 0.03% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 12 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 15 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 9 0.00% 81.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 504 0.10% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.01% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 45 0.01% 81.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.01% 81.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 51 0.01% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64796 13.19% 94.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 27598 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 491250 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5758 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011721 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3005 52.19% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.02% 52.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.03% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 52.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1119 19.43% 71.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1631 28.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 492538 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1270488 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 476500 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 543000 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 500130 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 491250 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 47102 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 391 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 137 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 34927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 290134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.693183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.849936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99883 34.43% 34.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 70212 24.20% 58.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 46683 16.09% 74.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19052 6.57% 81.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19950 6.88% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19386 6.68% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11922 4.11% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2114 0.73% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 932 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290134 # Number of insts issued each cycle +system.cpu.iq.rate 1.343792 # Inst issue rate +system.cpu.iq.vec_alu_accesses 4378 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 8295 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 3071 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 4664 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 207 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 153 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 61281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 28437 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 337755 # number of misc regfile reads +system.cpu.misc_regfile_writes 1378 # number of misc regfile writes +system.cpu.numCycles 365570 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23496 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 489437 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1748 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 125297 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 653 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 769495 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 512551 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 560059 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 115036 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 4963 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3133 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 8520 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 70622 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 542232 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 14652 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 836 # count of serializing insts renamed +system.cpu.rename.skidInsts 13164 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 3314 # Number of vector rename lookups +system.cpu.rob.rob_reads 773252 # The number of ROB reads +system.cpu.rob.rob_writes 1009500 # The number of ROB writes +system.cpu.timesIdled 1222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2634 # number of vector regfile reads +system.cpu.vec_regfile_writes 765 # number of vector regfile writes +system.cpu.workload.numSyscalls 20 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1886 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2788 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 6575 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1461 # Transaction distribution +system.membus.trans_dist::ReadExReq 363 # Transaction distribution +system.membus.trans_dist::ReadExResp 363 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1461 # Transaction distribution +system.membus.trans_dist::InvalidateReq 62 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3710 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 116736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116736 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1886 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1886 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1886 # Request fanout histogram +system.membus.reqLayer0.occupancy 2371500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9628750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3293 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 641 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1526 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 621 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 426 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 426 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2024 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1270 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 67 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 67 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 5573 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4788 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 10361 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 227136 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 376704 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3787 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000264 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.016250 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3786 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3787 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 5454500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2577500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3034500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1103 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 792 # number of demand (read+write) hits +system.l2.demand_hits::total 1895 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1103 # number of overall hits +system.l2.overall_hits::.cpu.data 792 # number of overall hits +system.l2.overall_hits::total 1895 # number of overall hits +system.l2.demand_misses::.cpu.inst 921 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 904 # number of demand (read+write) misses +system.l2.demand_misses::total 1825 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 921 # number of overall misses +system.l2.overall_misses::.cpu.data 904 # number of overall misses +system.l2.overall_misses::total 1825 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 72634500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 71937500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 144572000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 72634500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 71937500 # number of overall miss cycles +system.l2.overall_miss_latency::total 144572000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2024 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1696 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3720 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2024 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1696 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3720 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.455040 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.533019 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.490591 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.455040 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.533019 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.490591 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78864.820847 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79576.880531 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79217.534247 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78864.820847 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79576.880531 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79217.534247 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 921 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 904 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1825 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 921 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 904 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1825 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 63434500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 62897500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 126332000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 63434500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 62897500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 126332000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.533019 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.490591 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.533019 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.490591 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69576.880531 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69223.013699 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69576.880531 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69223.013699 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 641 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 641 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 641 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 641 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1526 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1526 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1526 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1526 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 63 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 63 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 363 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 363 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 28112500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 28112500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 426 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 426 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.852113 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.852113 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77444.903581 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77444.903581 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 363 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 363 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 24482500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 24482500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.852113 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.852113 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67444.903581 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67444.903581 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1103 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1103 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 921 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 921 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 72634500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 72634500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2024 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2024 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.455040 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.455040 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78864.820847 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78864.820847 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 921 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 921 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 63434500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 63434500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.455040 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.455040 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68875.678610 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68875.678610 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 729 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 729 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 541 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 541 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 43825000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 43825000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1270 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1270 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.425984 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.425984 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81007.393715 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81007.393715 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 541 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 541 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 38415000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 38415000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.425984 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.425984 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71007.393715 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71007.393715 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 5 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 5 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 62 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 62 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 67 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 67 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.925373 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.925373 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 62 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 62 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1179500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1179500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.925373 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.925373 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19024.193548 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19024.193548 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1322.433314 # Cycle average of tags in use +system.l2.tags.total_refs 6511 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1877 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.468833 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 39.648283 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 630.978547 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 651.806484 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001210 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.019256 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.019892 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.040357 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 192 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.057129 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 54469 # Number of tag accesses +system.l2.tags.data_accesses 54469 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 58880 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 57856 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 116736 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 58880 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 58880 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 920 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 904 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1824 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 322127970 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 316525745 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 638653715 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 322127970 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 322127970 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 322127970 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 316525745 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 638653715 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 920.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 904.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000580000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3628 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1824 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1824 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 189 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 197 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 155 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 101 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 127 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 89 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 17018000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 9120000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 51218000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9330.04 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28080.04 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1498 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 82.13 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1824 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 952 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 538 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 224 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 91 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 5 # What read queue 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What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 316 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 362.531646 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 212.877483 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 353.211294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 106 33.54% 33.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 61 19.30% 52.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 35 11.08% 63.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 24 7.59% 71.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 13 4.11% 75.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.80% 79.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 3.48% 82.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.58% 84.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 49 15.51% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 316 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 116736 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 116736 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 638.65 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 638.65 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.99 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.99 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 182676500 # Total gap between requests +system.mem_ctrls.avgGap 100151.59 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 58880 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 57856 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 322127970.369478821754 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 316525744.797835707664 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 920 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 904 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 25584250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 25633750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27808.97 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28355.92 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 792540 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 402270 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4441080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 14136720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 50495160 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 27667200 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 97934970 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 535.794720 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 71508750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 5980000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 105295750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1535100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 796950 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 8582280 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 14136720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 41640780 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 35123520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 101815350 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 557.023982 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 90912250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 5980000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 85892250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 90131 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 90131 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 90131 # number of overall hits +system.cpu.icache.overall_hits::total 90131 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2289 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2289 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2289 # number of overall misses +system.cpu.icache.overall_misses::total 2289 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 103808498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 103808498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 103808498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 103808498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 92420 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 92420 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 92420 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 92420 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.024767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.024767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.024767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.024767 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 45351.025775 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45351.025775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 45351.025775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45351.025775 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1564 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1526 # number of writebacks +system.cpu.icache.writebacks::total 1526 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 265 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 265 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 265 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 265 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2024 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 87359998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 87359998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 87359998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 87359998 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.021900 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.021900 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.021900 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.021900 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 43162.054348 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43162.054348 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 43162.054348 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43162.054348 # average overall mshr miss latency +system.cpu.icache.replacements 1526 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 90131 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 90131 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2289 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2289 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 103808498 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 45.553139 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 423.494175 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.827137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.827137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 497 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 186863 # Number of tag accesses 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of overall hits +system.cpu.dcache.overall_hits::total 78433 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 5469 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5469 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 5471 # number of overall misses +system.cpu.dcache.overall_misses::total 5471 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 256552675 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 256552675 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 256552675 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 256552675 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 83882 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 83882 # number of demand (read+write) accesses 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blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 516 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.976744 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 641 # number of writebacks +system.cpu.dcache.writebacks::total 641 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3710 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3710 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3710 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3710 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 1759 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1759 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 1761 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1761 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 84641943 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84641943 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 84826943 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84826943 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.020970 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.020970 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.020988 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.020988 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 48119.353610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48119.353610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 48169.757524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48169.757524 # average overall mshr miss latency +system.cpu.dcache.replacements 1262 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 55579 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 55579 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3076 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3076 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 130689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 130689500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 58655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 58655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.052442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 42486.833550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42486.833550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 53189500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53189500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.021584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 42013.823065 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42013.823065 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 22834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22834 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 2333 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2333 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 123942720 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 123942720 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 25167 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 25167 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.092701 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.092701 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 53125.897985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53125.897985 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 433 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 433 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 29591988 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29591988 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.017205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 68341.773672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68341.773672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 20 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 20 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 22 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 22 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.090909 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.090909 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.090909 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1920455 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1920455 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32007.583333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32007.583333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1860455 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1860455 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31007.583333 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31007.583333 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 258 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 258 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 214000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 214000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.019011 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.019011 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007605 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007605 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 246 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 246 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 246 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 246 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 433.592808 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 80700 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 45.774248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 433.592808 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.846861 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.846861 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 170589 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 170589 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 182784500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 182784500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/hmmer/bombesin.out b/outoforder/hmmer/bombesin.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/hmmer/config.ini b/outoforder/hmmer/config.ini new file mode 100644 index 000000000..59ac929cc --- /dev/null +++ b/outoforder/hmmer/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 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+opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] 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+type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 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+tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/hmmer/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/hmmer/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/hmmer/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/hmmer/config.json b/outoforder/hmmer/config.json new file mode 100644 index 000000000..d95c03539 --- /dev/null +++ b/outoforder/hmmer/config.json @@ -0,0 +1,1821 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "outoforder/hmmer/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "outoforder/hmmer/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "outoforder/hmmer/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", 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"GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + 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"prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "write_allocator": null, + "size": 32768, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.tol2bus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 4, + "writeback_clean": false, + "tags": { + "tag_latency": 2, + "replacement_policy": "system.cpu.dcache.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 2, 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"addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + 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"clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + 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"size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/hmmer/fs/proc/cpuinfo b/outoforder/hmmer/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/hmmer/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/hmmer/fs/proc/stat b/outoforder/hmmer/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/hmmer/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/hmmer/fs/sys/devices/system/cpu/online b/outoforder/hmmer/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/hmmer/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/hmmer/fs/sys/devices/system/cpu/possible b/outoforder/hmmer/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/hmmer/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/hmmer/stats.txt b/outoforder/hmmer/stats.txt new file mode 100644 index 000000000..4e470973b --- /dev/null +++ b/outoforder/hmmer/stats.txt @@ -0,0 +1,1343 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 219840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 98226 # Simulator instruction rate (inst/s) +host_mem_usage 855380 # Number of bytes of host memory used +host_op_rate 124605 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.09 # Real time elapsed on the host +host_tick_rate 43185489 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500007 # Number of instructions simulated +sim_ops 634311 # Number of ops (including micro ops) simulated +sim_seconds 0.000220 # Number of seconds simulated +sim_ticks 219840000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.357413 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 66794 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68607 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4474 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 103716 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 295 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 957 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 662 # Number of indirect misses. +system.cpu.branchPred.lookups 133728 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 47293 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 28019 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 44730 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 30582 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 253 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 64 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 4975 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1524 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 236 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 166 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3341 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 309 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 908 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 548 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1072 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 479 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 695 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 732 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 449 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 843 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 636 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 546 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 420 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 413 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 905 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 908 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 478 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1273 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 182 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 674 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 51818 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1018 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 847 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1540 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3027 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 493 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 719 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3492 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 760 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 524 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 849 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 669 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 612 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 696 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 576 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 641 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 453 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 707 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 795 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 931 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 880 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 920 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1120 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 18130 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 335 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1399 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 9971 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 171 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 151551 # number of cc regfile reads +system.cpu.cc_regfile_writes 140722 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3823 # The number of times a branch was mispredicted +system.cpu.commit.branches 99379 # Number of branches committed +system.cpu.commit.bw_lim_events 42143 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 256 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 118914 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 501127 # Number of instructions committed +system.cpu.commit.committedOps 635431 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 337407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.883277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.745616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 173654 51.47% 51.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 46706 13.84% 65.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26411 7.83% 73.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21506 6.37% 79.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 12342 3.66% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5705 1.69% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6232 1.85% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2708 0.80% 87.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 42143 12.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 337407 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 7811 # Number of function calls committed. +system.cpu.commit.int_insts 562736 # Number of committed integer instructions. +system.cpu.commit.loads 93271 # Number of loads committed +system.cpu.commit.membars 236 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 501 0.08% 0.08% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 378496 59.57% 59.64% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3603 0.57% 60.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 23 0.00% 60.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 1038 0.16% 60.38% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 60.38% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 5192 0.82% 61.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 5160 0.81% 62.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 7224 1.14% 63.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1054 0.17% 63.31% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 7569 1.19% 64.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1013 0.16% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 1516 0.24% 64.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 1280 0.20% 65.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2064 0.32% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.43% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 93271 14.68% 80.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 126423 19.90% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 635431 # Class of committed instruction +system.cpu.commit.refs 219694 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 47105 # Number of committed Vector instructions. +system.cpu.committedInsts 500007 # Number of Instructions Simulated +system.cpu.committedOps 634311 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.879350 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.879350 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 130142 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 662 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 65154 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 810678 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 83315 # Number of cycles decode is idle +system.cpu.decode.RunCycles 126620 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3908 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2505 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 10506 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 133728 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 82576 # Number of cache lines fetched +system.cpu.fetch.Cycles 243747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1688 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 688136 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9118 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.304148 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 106070 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 77060 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.565080 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 354491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.384848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.115971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197359 55.67% 55.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 12022 3.39% 59.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14361 4.05% 63.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15554 4.39% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 15827 4.46% 71.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15573 4.39% 76.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 23049 6.50% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7434 2.10% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53312 15.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 354491 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 85190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 6601 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 107355 # Number of branches executed +system.cpu.iew.exec_nop 1407 # number of nop insts executed +system.cpu.iew.exec_rate 1.584719 # Inst execution rate +system.cpu.iew.exec_refs 239930 # number of memory reference insts executed +system.cpu.iew.exec_stores 131547 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 19190 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 116229 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 303 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 600 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 145339 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 754729 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 108383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9468 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 696771 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 123 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 240 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3908 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 390 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 241 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 65 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 82 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 22956 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 18916 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 65 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1895 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4706 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 598879 # num instructions consuming a value +system.cpu.iew.wb_count 688394 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.568941 # average fanout of values written-back +system.cpu.iew.wb_producers 340727 # num instructions producing a value +system.cpu.iew.wb_rate 1.565667 # insts written-back per cycle +system.cpu.iew.wb_sent 692436 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 816038 # number of integer regfile reads +system.cpu.int_regfile_writes 426895 # number of integer regfile writes +system.cpu.ipc 1.137204 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.137204 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 548 0.08% 0.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 422034 59.76% 59.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3658 0.52% 60.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 28 0.00% 60.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1039 0.15% 60.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 4 0.00% 60.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5193 0.74% 61.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5160 0.73% 61.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 7224 1.02% 62.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1054 0.15% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 7628 1.08% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1128 0.16% 64.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1667 0.24% 64.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1386 0.20% 64.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2307 0.33% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 65.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 111369 15.77% 80.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 134813 19.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 706240 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 21849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.030937 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3799 17.39% 17.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 13 0.06% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 17.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 1032 4.72% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 51 0.23% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 46 0.21% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 22.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3463 15.85% 38.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 13445 61.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 678577 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1692190 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 640481 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 820562 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 753019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 706240 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 303 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 118989 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1236 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 102726 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 354491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.992265 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.409693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 161859 45.66% 45.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37387 10.55% 56.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26714 7.54% 63.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40239 11.35% 75.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 27997 7.90% 82.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19873 5.61% 88.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 13771 3.88% 92.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12479 3.52% 96.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14172 4.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 354491 # Number of insts issued each cycle +system.cpu.iq.rate 1.606255 # Inst issue rate +system.cpu.iq.vec_alu_accesses 48964 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 97865 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 47913 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 51813 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11885 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 116229 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 145339 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 565970 # number of misc regfile reads +system.cpu.misc_regfile_writes 21651 # number of misc regfile writes +system.cpu.numCycles 439681 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 20233 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 582052 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 510 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 89352 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 280 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1298765 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 790749 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 703883 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 129927 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 72367 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3908 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 76370 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 121776 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 951558 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 34701 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1965 # count of serializing insts renamed +system.cpu.rename.skidInsts 31075 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 306 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 61895 # Number of vector rename lookups +system.cpu.rob.rob_reads 1049154 # The number of ROB reads +system.cpu.rob.rob_writes 1525825 # The number of ROB writes +system.cpu.timesIdled 845 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 59491 # number of vector regfile reads +system.cpu.vec_regfile_writes 45369 # number of vector regfile writes +system.cpu.workload.numSyscalls 19 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1805 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1160 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 3269 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1411 # Transaction distribution +system.membus.trans_dist::ReadExReq 381 # Transaction distribution +system.membus.trans_dist::ReadExResp 381 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1411 # Transaction distribution +system.membus.trans_dist::InvalidateReq 13 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3597 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 114688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 114688 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1805 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1805 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1805 # Request fanout histogram +system.membus.reqLayer0.occupancy 2256500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 9483500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1706 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 213 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 817 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 130 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 390 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 390 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1309 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 397 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 13 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 13 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3435 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1943 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 5378 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 136064 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 64000 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 200064 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2109 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000474 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.021775 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2108 99.95% 99.95% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.05% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2109 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 2664500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1187499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1963999 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 241 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 63 # number of demand (read+write) hits +system.l2.demand_hits::total 304 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 241 # number of overall hits +system.l2.overall_hits::.cpu.data 63 # number of overall hits +system.l2.overall_hits::total 304 # number of overall hits +system.l2.demand_misses::.cpu.inst 1068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 724 # number of demand (read+write) misses +system.l2.demand_misses::total 1792 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1068 # number of overall misses +system.l2.overall_misses::.cpu.data 724 # number of overall misses +system.l2.overall_misses::total 1792 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 83627500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 58511500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 142139000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 83627500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 58511500 # number of overall miss cycles +system.l2.overall_miss_latency::total 142139000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1309 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 787 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2096 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1309 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 787 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2096 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.815890 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.919949 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.854962 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.815890 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.919949 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.854962 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80816.988950 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79318.638393 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80816.988950 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79318.638393 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 724 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1792 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 724 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1792 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 72947500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 51271500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 124219000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 72947500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 51271500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 124219000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.815890 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.919949 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.854962 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.815890 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.919949 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.854962 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70816.988950 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69318.638393 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70816.988950 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69318.638393 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 213 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 213 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 213 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 213 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 816 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 816 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 816 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 816 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 9 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 9 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 381 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 381 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 30422500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 30422500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 390 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 390 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.976923 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.976923 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79849.081365 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79849.081365 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 381 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 381 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 26612500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 26612500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.976923 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.976923 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69849.081365 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69849.081365 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 241 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 241 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 83627500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1309 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1309 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.815890 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.815890 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78302.902622 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.815890 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.815890 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 54 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 54 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 397 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 397 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.863980 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.863980 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.863980 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.863980 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 13 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 13 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 13 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 13 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18961.538462 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18961.538462 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1387.518506 # Cycle average of tags in use +system.l2.tags.total_refs 3255 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1800 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.808333 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 5.104599 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 894.431114 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 487.982793 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000156 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.027296 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.014892 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.042344 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1800 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1664 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.054932 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 27944 # Number of tag accesses +system.l2.tags.data_accesses 27944 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 68352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 46336 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 114688 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 724 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1792 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 310917031 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 210771470 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 521688501 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 310917031 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 310917031 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 310917031 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 210771470 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 521688501 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 724.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000559500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3579 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1792 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1792 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 37 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 28 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 177 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 178 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 215 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 133 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 78 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.44 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 16827250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 8960000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 50427250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9390.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28140.21 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1409 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.63 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1792 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1046 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 532 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 382 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 300.062827 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 196.143595 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 284.444509 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 114 29.84% 29.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 97 25.39% 55.24% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 59 15.45% 70.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 33 8.64% 79.32% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 26 6.81% 86.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 3.66% 89.79% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 1.05% 90.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 2.09% 92.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 27 7.07% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 382 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 114688 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 114688 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 521.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 521.69 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.08 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.08 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 218912500 # Total gap between requests +system.mem_ctrls.avgGap 122160.99 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 68352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 46336 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 310917030.567685604095 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 210771470.160116434097 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 724 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 28999750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 21427500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27153.32 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 29595.99 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.63 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1420860 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 751410 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 5990460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 17209920.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 90190530 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 8468640 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 124031820 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 564.191321 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 21246750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 7280000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 191313250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1313760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 698280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6804420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 17209920.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 88510170 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 9883680 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 124420230 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 565.958106 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 24958000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 7280000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 187602000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 80920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 80920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 80920 # number of overall hits +system.cpu.icache.overall_hits::total 80920 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1656 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1656 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1656 # number of overall misses +system.cpu.icache.overall_misses::total 1656 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 108256496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108256496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 108256496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108256496 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 82576 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82576 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 82576 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82576 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.020054 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.020054 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.020054 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.020054 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65372.280193 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65372.280193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65372.280193 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65372.280193 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 922 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.086957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 817 # number of writebacks +system.cpu.icache.writebacks::total 817 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 347 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 347 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 347 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1309 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88171497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88171497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88171497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88171497 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.015852 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015852 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.015852 # mshr miss rate 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+system.cpu.icache.tags.avg_refs 62.818182 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 440.701258 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.860745 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.860745 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 492 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 473 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.960938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 166461 # Number of tag accesses +system.cpu.icache.tags.data_accesses 166461 # Number of data accesses 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number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 2961 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2961 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 2971 # number of overall misses +system.cpu.dcache.overall_misses::total 2971 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 185120364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185120364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 185120364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185120364 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 234688 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 234688 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 234880 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 234880 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.012617 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.012617 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.012649 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.012649 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 62519.542047 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62519.542047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62309.109391 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62309.109391 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7524 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.258824 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 213 # number of writebacks +system.cpu.dcache.writebacks::total 213 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2166 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 795 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.overall_mshr_miss_rate::total 0.003406 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 75941.503145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75941.503145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 75969.368750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75969.368750 # average overall mshr miss latency +system.cpu.dcache.replacements 343 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 107370 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 107370 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1062 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1062 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 74225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 74225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 108432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 108432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.009794 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009794 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 69891.713748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69891.713748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 392 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 392 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 28862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28862000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.003615 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 73627.551020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73627.551020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 124357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 124357 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1892 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1892 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 110673367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110673367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 126249 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 126249 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.014986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 58495.437104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58495.437104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1496 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1496 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 396 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 396 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 31296498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 31296498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.003137 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003137 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 79031.560606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79031.560606 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 182 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 182 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 192 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 192 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.052083 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.052083 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.026042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.026042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 261 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 261 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 261 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 261 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 236 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 236 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 350.411222 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 233206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 800 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 291.507500 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 350.411222 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.684397 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.684397 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 471554 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 471554 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 219840000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 219840000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/lbm/config.ini b/outoforder/lbm/config.ini new file mode 100644 index 000000000..f68c04ae3 --- /dev/null +++ b/outoforder/lbm/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 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+opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] 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+eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross 20 reference.dat 0 1 /home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//data/ref/input/100_100_130_ldc.of +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lbm.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= 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+[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/lbm/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/lbm/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/lbm/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/lbm/config.json b/outoforder/lbm/config.json new file mode 100644 index 000000000..152323a7b --- /dev/null +++ b/outoforder/lbm/config.json @@ -0,0 +1,1815 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": 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"power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + 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[ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/lbm/fs/proc/cpuinfo b/outoforder/lbm/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/lbm/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/lbm/fs/proc/stat b/outoforder/lbm/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/lbm/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/lbm/fs/sys/devices/system/cpu/online b/outoforder/lbm/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/lbm/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/lbm/fs/sys/devices/system/cpu/possible b/outoforder/lbm/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/lbm/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/lbm/lbm.out b/outoforder/lbm/lbm.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/lbm/stats.txt b/outoforder/lbm/stats.txt new file mode 100644 index 000000000..48d43e150 --- /dev/null +++ b/outoforder/lbm/stats.txt @@ -0,0 +1,1387 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2311942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 31937 # Simulator instruction rate (inst/s) +host_mem_usage 854804 # Number of bytes of host memory used +host_op_rate 72258 # Simulator op (including micro ops) rate (op/s) +host_seconds 15.66 # Real time elapsed on the host +host_tick_rate 147673365 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_ops 1131248 # Number of ops (including micro ops) simulated +sim_seconds 0.002312 # Number of seconds simulated +sim_ticks 2311942500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.660812 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 40446 # Number of BTB hits +system.cpu.branchPred.BTBLookups 40995 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 681 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 42559 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 184 # Number of indirect misses. +system.cpu.branchPred.lookups 43958 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 1019 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 35515 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 885 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 35649 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 7 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 16 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 13 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 36104 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 11 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 6 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 6 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 3 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 382 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 113457 # number of cc regfile reads +system.cpu.cc_regfile_writes 113426 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 458 # The number of times a branch was mispredicted +system.cpu.commit.branches 37145 # Number of branches committed +system.cpu.commit.bw_lim_events 1796 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 25 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 61677 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500019 # Number of instructions committed +system.cpu.commit.committedOps 1131267 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 4573302 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.247363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.948683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 4161660 91.00% 91.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 105271 2.30% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 131377 2.87% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 96504 2.11% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 606 0.01% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13673 0.30% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 48332 1.06% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 14083 0.31% 99.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1796 0.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4573302 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 212 # Number of function calls committed. +system.cpu.commit.int_insts 1094966 # Number of committed integer instructions. +system.cpu.commit.loads 1635 # Number of loads committed +system.cpu.commit.membars 14 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 18 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 428068 37.84% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 35 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 2 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 37.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 5 0.00% 37.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 37.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 50 0.00% 37.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 37.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 75 0.01% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 72 0.01% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 50 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 37.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1635 0.14% 38.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 701254 61.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1131267 # Class of committed instruction +system.cpu.commit.refs 702889 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 664832 # Number of committed Vector instructions. +system.cpu.committedInsts 500000 # Number of Instructions Simulated +system.cpu.committedOps 1131248 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 9.247772 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.247772 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 4369539 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 226 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 39139 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1235190 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 52633 # Number of cycles decode is idle +system.cpu.decode.RunCycles 46970 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1852 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 110361 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 43958 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 83596 # Number of cache lines fetched +system.cpu.fetch.Cycles 4484173 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 474 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 577728 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4150 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.009507 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 95060 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 40868 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.124944 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 4581355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.282931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.402353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 4377771 95.56% 95.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 462 0.01% 95.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 40699 0.89% 96.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 306 0.01% 96.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 404 0.01% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 356 0.01% 96.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40268 0.88% 97.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 288 0.01% 97.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 120801 2.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4581355 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 536 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 39231 # Number of branches executed +system.cpu.iew.exec_nop 39 # number of nop insts executed +system.cpu.iew.exec_rate 0.261035 # Inst execution rate +system.cpu.iew.exec_refs 749237 # number of memory reference insts executed +system.cpu.iew.exec_stores 746687 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 6958 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2762 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 747150 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1209545 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2550 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 596 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1206995 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1665664 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1852 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1664339 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 69096 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 25 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1127 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 45891 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 431 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 656495 # num instructions consuming a value +system.cpu.iew.wb_count 1188304 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.471144 # average fanout of values written-back +system.cpu.iew.wb_producers 309304 # num instructions producing a value +system.cpu.iew.wb_rate 0.256992 # insts written-back per cycle +system.cpu.iew.wb_sent 1206648 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1246301 # number of integer regfile reads +system.cpu.int_regfile_writes 420815 # number of integer regfile writes +system.cpu.ipc 0.108134 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.108134 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 457746 37.91% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 2 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 37.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 61 0.01% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 92 0.01% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 84 0.01% 37.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 37.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 37.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2674 0.22% 38.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 746802 61.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1207592 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 17308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014333 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98 0.57% 0.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.02% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 0.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.02% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 50 0.29% 0.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 17153 99.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 500531 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5582274 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 496323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 538009 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1209473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1207592 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 78249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 71088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 4581355 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.263588 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.932985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4143331 90.44% 90.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93292 2.04% 92.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 147111 3.21% 95.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59017 1.29% 96.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79707 1.74% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 36777 0.80% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 16289 0.36% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4068 0.09% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1763 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4581355 # Number of insts issued each cycle +system.cpu.iq.rate 0.261164 # Inst issue rate +system.cpu.iq.vec_alu_accesses 724348 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1431647 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 691981 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 749763 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2762 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 747150 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 2323953 # number of misc regfile reads +system.cpu.misc_regfile_writes 60 # number of misc regfile writes +system.cpu.numCycles 4623886 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 1671684 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 501631 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 103313 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3504487 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1215949 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 540291 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 106355 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 2649533 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1852 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2695181 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 38653 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1255866 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 102 # count of serializing insts renamed +system.cpu.rename.skidInsts 885642 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 711211 # Number of vector rename lookups +system.cpu.rob.rob_reads 5746484 # The number of ROB reads +system.cpu.rob.rob_writes 2393962 # The number of ROB writes +system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 707415 # number of vector regfile reads +system.cpu.vec_regfile_writes 352 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 55007 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 143183 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 87296 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 175498 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 391 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 54788 # Transaction distribution +system.membus.trans_dist::CleanEvict 219 # Transaction distribution +system.membus.trans_dist::ReadExReq 86105 # Transaction distribution +system.membus.trans_dist::ReadExResp 86104 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 1439 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 229919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 229919 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 9057536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 9057536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 88176 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 88176 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 88176 # Request fanout histogram +system.membus.reqLayer0.occupancy 383917000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 16.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 450562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 656 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 141843 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 151 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 701 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 86107 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 86104 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 542 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 1439 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 1439 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 262462 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 263697 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 44352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 11089408 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 11133760 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 55399 # Total snoops (count) +system.tol2bus.snoopTraffic 3506496 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 143601 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002730 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.052176 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 143209 99.73% 99.73% # Request fanout histogram +system.tol2bus.snoop_fanout::1 392 0.27% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 143601 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 174954000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 130046500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 813000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 23 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 24 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 23 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 24 # number of overall hits +system.l2.demand_misses::.cpu.inst 519 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 86220 # number of demand (read+write) misses +system.l2.demand_misses::total 86739 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 519 # number of overall misses +system.l2.overall_misses::.cpu.data 86220 # number of overall misses +system.l2.overall_misses::total 86739 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40762500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 8387891500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 8428654000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40762500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 8387891500 # number of overall miss cycles +system.l2.overall_miss_latency::total 8428654000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 542 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 86221 # number of demand (read+write) accesses +system.l2.demand_accesses::total 86763 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 542 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 86221 # number of overall (read+write) accesses +system.l2.overall_accesses::total 86763 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.957565 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999988 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.999723 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.957565 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999988 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.999723 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 97284.754117 # average overall miss latency +system.l2.demand_avg_miss_latency::total 97172.598255 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 97284.754117 # average overall miss latency +system.l2.overall_avg_miss_latency::total 97172.598255 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 54789 # number of writebacks +system.l2.writebacks::total 54789 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 86220 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 86739 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 86220 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 86739 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35572500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 7525721500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 7561294000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35572500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 7525721500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 7561294000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999988 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.999723 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999988 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.999723 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 87285.102064 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 87172.944120 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 87285.102064 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 87172.944120 # average overall mshr miss latency +system.l2.replacements 55399 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 87054 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 87054 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 87054 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 87054 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 151 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 151 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 151 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 151 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 86107 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 86107 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 8378523500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 8378523500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 86107 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 86107 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 97303.628044 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 97303.628044 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 86107 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 86107 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 7517483500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 7517483500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 87303.976448 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 87303.976448 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 1439 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 1439 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 1439 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 1439 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 1439 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 1439 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 27086000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 27086000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18822.793607 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18822.793607 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 27672.813836 # Cycle average of tags in use +system.l2.tags.total_refs 174055 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 88167 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.974151 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 448.244239 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 145.553837 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 27079.015761 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.013679 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.004442 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.826386 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.844507 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 345 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 3121 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 29302 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1492143 # Number of tag accesses +system.l2.tags.data_accesses 1492143 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 5517952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 5551168 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 3506432 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 3506432 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 86218 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 86737 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 54788 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 54788 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 14367139 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2386716798 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2401083937 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 14367139 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 14367139 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1516660557 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1516660557 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1516660557 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 14367139 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2386716798 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3917744494 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 54788.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 86218.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000010576500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 3422 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 3422 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 207649 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 51420 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 86737 # Number of read requests accepted +system.mem_ctrls.writeReqs 54788 # Number of write requests accepted +system.mem_ctrls.readBursts 86737 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 54788 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 5469 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 5465 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 5436 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 5424 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5401 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 5368 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 5306 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 5321 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 5372 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 5479 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 5423 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 5423 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 5429 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 5439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 5450 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 5532 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 3454 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 3453 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 3454 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3372 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 3382 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 3381 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 3334 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 3348 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 3393 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 3456 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 3455 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 19.19 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 2314251500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 433685000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 3940570250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 26681.25 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 45431.25 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 80200 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 50450 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.46 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.08 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 86737 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 54788 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 24203 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 23736 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 25213 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 13577 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 164 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1117 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2154 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3341 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 3464 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3463 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 3792 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 3680 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 3927 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 3641 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 4025 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 5142 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 5218 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 4101 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 3821 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 3612 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 10843 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 835.045652 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 689.593017 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 323.296619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 673 6.21% 6.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 593 5.47% 11.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 380 3.50% 15.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 202 1.86% 17.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 410 3.78% 20.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 164 1.51% 22.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 467 4.31% 26.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1381 12.74% 39.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 6573 60.62% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 10843 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 3422 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 25.344828 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.772874 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 554.647773 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 3421 99.97% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.03% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 3422 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 3422 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.002922 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.002802 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.063905 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3414 99.77% 99.77% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 0.18% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 0.06% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 3422 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 5551168 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 3504768 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 5551168 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 3506432 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2401.08 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1515.94 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2401.08 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1516.66 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 30.60 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 18.76 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 11.84 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 2311926500 # Total gap between requests +system.mem_ctrls.avgGap 16335.82 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 5517952 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 3504768 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 14367139.321155261248 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2386716797.671222209930 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1515940816.002127885818 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 86218 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 54788 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14227250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 3926343000 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 41441099250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27412.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 45539.71 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 756390.07 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.32 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 38763060 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 20591670 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 310925580 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 143988480 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 181933440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 758781150 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 248812320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 1703795700 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 736.954185 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 624585000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 76960000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 1610397500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 38698800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 20557515 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 308376600 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 141869160 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 181933440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 747675840 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 258164160 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 1697275515 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 734.133965 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 648640250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 76960000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 1586342250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 82888 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 82888 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 82888 # number of overall hits +system.cpu.icache.overall_hits::total 82888 # number of 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2389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 106465 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 106465 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 594772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 594772 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 42757817903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42757817903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 701237 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 701237 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.848175 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.848175 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 71889.426373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71889.426373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 507233 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 507233 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 87539 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 87539 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 8584345998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8584345998 # number of WriteReq MSHR miss cycles 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+system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 506.192053 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 196304 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 87657 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 2.239456 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 506.192053 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.988656 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.988656 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 347 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1495035 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1495035 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2311942500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 2311942500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/leslie3d/config.ini b/outoforder/leslie3d/config.ini new file mode 100644 index 000000000..94ae07867 --- /dev/null +++ b/outoforder/leslie3d/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//data/ref/input/leslie3d.in +kvmInSE=false +maxStackSize=67108864 +output=leslie3d.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/leslie3d/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/leslie3d/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/leslie3d/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/leslie3d/config.json b/outoforder/leslie3d/config.json new file mode 100644 index 000000000..e66d27a78 --- /dev/null +++ b/outoforder/leslie3d/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "outoforder/leslie3d/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "outoforder/leslie3d/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "outoforder/leslie3d/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": 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0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/leslie3d/fs/proc/cpuinfo b/outoforder/leslie3d/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/leslie3d/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/leslie3d/fs/proc/stat b/outoforder/leslie3d/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/leslie3d/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/leslie3d/fs/sys/devices/system/cpu/online b/outoforder/leslie3d/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/leslie3d/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/leslie3d/fs/sys/devices/system/cpu/possible b/outoforder/leslie3d/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/leslie3d/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/leslie3d/leslie3d.stdout b/outoforder/leslie3d/leslie3d.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/leslie3d/stats.txt b/outoforder/leslie3d/stats.txt new file mode 100644 index 000000000..7af5f09d5 --- /dev/null +++ b/outoforder/leslie3d/stats.txt @@ -0,0 +1,1361 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 317412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 124270 # Simulator instruction rate (inst/s) +host_mem_usage 856216 # Number of bytes of host memory used +host_op_rate 131017 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.02 # Real time elapsed on the host +host_tick_rate 78885961 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_ops 527167 # Number of ops (including micro ops) simulated +sim_seconds 0.000317 # Number of seconds simulated +sim_ticks 317412000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.537070 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 122992 # Number of BTB hits +system.cpu.branchPred.BTBLookups 124818 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 3114 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 137475 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1729 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2702 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 973 # Number of indirect misses. +system.cpu.branchPred.lookups 152544 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 97627 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 13124 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 13010 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 97741 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 71 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 3485 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 97 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 176 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2489 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 2967 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 3567 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 175 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 149 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 6039 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 9892 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 123 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 811 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 12760 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 20355 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 45 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 900 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 5824 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 308 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 247 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1078 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1366 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 482 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 212 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 196 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 23950 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 811 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2629 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2287 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 2963 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 673 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 914 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2852 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 6049 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 126 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 9919 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 12761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 695 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 31 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 20335 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 6591 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 311 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 240 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 326 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 2413 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 73839 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 100 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 675 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 5816 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 229 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 336989 # number of cc regfile reads +system.cpu.cc_regfile_writes 338550 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2495 # The number of times a branch was mispredicted +system.cpu.commit.branches 121767 # Number of branches committed +system.cpu.commit.bw_lim_events 10401 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 62802 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 501042 # Number of instructions committed +system.cpu.commit.committedOps 528209 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 558634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.945537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.773279 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391824 70.14% 70.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47228 8.45% 78.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15785 2.83% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18566 3.32% 84.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69196 12.39% 97.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2033 0.36% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1651 0.30% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1950 0.35% 98.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10401 1.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 558634 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 4620 # Number of function calls committed. +system.cpu.commit.int_insts 425736 # Number of committed integer instructions. +system.cpu.commit.loads 35378 # Number of loads committed +system.cpu.commit.membars 138 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 3 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 378885 71.73% 71.73% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 384 0.07% 71.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 94 0.02% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.82% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.01% 71.83% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 15 0.00% 71.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 10 0.00% 71.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 12 0.00% 71.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 72 0.01% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.85% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 35378 6.70% 78.55% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 113316 21.45% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 528209 # Class of committed instruction +system.cpu.commit.refs 148694 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2101 # Number of committed Vector instructions. +system.cpu.committedInsts 500000 # Number of Instructions Simulated +system.cpu.committedOps 527167 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.269650 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.269650 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 403823 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 633 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117071 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 622674 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 64568 # Number of cycles decode is idle +system.cpu.decode.RunCycles 73985 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2747 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2198 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 22764 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 152544 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 33076 # Number of cache lines fetched +system.cpu.fetch.Cycles 503864 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 626041 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6732 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.240293 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 60525 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 130537 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.986163 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 567887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.161721 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.096994 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417651 73.54% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5040 0.89% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4823 0.85% 75.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6304 1.11% 76.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 105214 18.53% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5198 0.92% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2375 0.42% 96.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5224 0.92% 97.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 16058 2.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 567887 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 66938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2896 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 131859 # Number of branches executed +system.cpu.iew.exec_nop 1577 # number of nop insts executed +system.cpu.iew.exec_rate 0.909104 # Inst execution rate +system.cpu.iew.exec_refs 162195 # number of memory reference insts executed +system.cpu.iew.exec_stores 121549 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 7262 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 41845 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 850 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 124469 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 596057 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40646 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4450 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 577122 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2190 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2747 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2206 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 6778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2895 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 6467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 11153 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1828 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1068 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 700278 # num instructions consuming a value +system.cpu.iew.wb_count 569460 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.416330 # average fanout of values written-back +system.cpu.iew.wb_producers 291547 # num instructions producing a value +system.cpu.iew.wb_rate 0.897035 # insts written-back per cycle +system.cpu.iew.wb_sent 574781 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 697723 # number of integer regfile reads +system.cpu.int_regfile_writes 331972 # number of integer regfile writes +system.cpu.ipc 0.787619 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.787619 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 416938 71.69% 71.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385 0.07% 71.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 96 0.02% 71.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 43 0.01% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 21 0.00% 71.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 14 0.00% 71.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 71.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 79 0.01% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 71.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41481 7.13% 78.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 122484 21.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 581572 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3746 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006441 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1156 30.86% 30.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.03% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.03% 30.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.05% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 30.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1706 45.54% 76.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 880 23.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 582917 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1730378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 567290 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 659309 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 594268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 581572 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 212 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 67312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 40667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 567887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.024098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.681716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 381520 67.18% 67.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31797 5.60% 72.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31396 5.53% 78.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 39374 6.93% 85.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 65781 11.58% 96.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8177 1.44% 98.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5684 1.00% 99.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2516 0.44% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1642 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 567887 # Number of insts issued each cycle +system.cpu.iq.rate 0.916114 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2397 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 4664 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2170 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2523 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1322 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 41845 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 124469 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 439317 # number of misc regfile reads +system.cpu.misc_regfile_writes 561 # number of misc regfile writes +system.cpu.numCycles 634825 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 9836 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 613494 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 76 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 77389 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1532 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1098043 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 608830 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 707058 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 83342 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 370647 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 2747 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 373771 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 93559 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 732430 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20802 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 866 # count of serializing insts renamed +system.cpu.rename.skidInsts 171274 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 212 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 2276 # Number of vector rename lookups +system.cpu.rob.rob_reads 1136332 # The number of ROB reads +system.cpu.rob.rob_writes 1191338 # The number of ROB writes +system.cpu.timesIdled 955 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2115 # number of vector regfile reads +system.cpu.vec_regfile_writes 186 # number of vector regfile writes +system.cpu.workload.numSyscalls 35 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 12000 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 11832 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 24643 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 981 # Transaction distribution +system.membus.trans_dist::ReadExReq 10938 # Transaction distribution +system.membus.trans_dist::ReadExResp 10935 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 981 # Transaction distribution +system.membus.trans_dist::InvalidateReq 81 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 23916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 23916 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 762624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 762624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 12000 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 12000 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 12000 # Request fanout histogram +system.membus.reqLayer0.occupancy 16764000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 62040250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1786 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 10600 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1033 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 199 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 10944 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 10940 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1496 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 290 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 81 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 81 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4025 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 33425 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 37450 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 161856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 1397120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1558976 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 12811 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000312 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.017668 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 12807 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 4 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 12811 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 23954500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.5 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 16885500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2244000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 663 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 147 # number of demand (read+write) hits +system.l2.demand_hits::total 810 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 663 # number of overall hits +system.l2.overall_hits::.cpu.data 147 # number of overall hits +system.l2.overall_hits::total 810 # number of overall hits +system.l2.demand_misses::.cpu.inst 833 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 11087 # number of demand (read+write) misses +system.l2.demand_misses::total 11920 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 833 # number of overall misses +system.l2.overall_misses::.cpu.data 11087 # number of overall misses +system.l2.overall_misses::total 11920 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 65230000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 833348000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 898578000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 65230000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 833348000 # number of overall miss cycles +system.l2.overall_miss_latency::total 898578000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1496 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 11234 # number of demand (read+write) accesses +system.l2.demand_accesses::total 12730 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1496 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 11234 # number of overall (read+write) accesses +system.l2.overall_accesses::total 12730 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.556818 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.986915 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.936371 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.556818 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.986915 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.936371 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75164.426806 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75384.060403 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75164.426806 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75384.060403 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 833 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 11087 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 11920 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 833 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 11087 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 11920 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 56900000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 722518000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 779418000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 56900000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 722518000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 779418000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.986915 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.936371 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.986915 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.936371 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65168.034635 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65387.416107 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65168.034635 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65387.416107 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 10600 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 10600 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 10600 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 10600 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1031 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1031 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1031 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1031 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 5 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 5 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 10939 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 10939 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 820763000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 820763000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 10944 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 10944 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999543 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999543 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75030.898620 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75030.898620 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 10939 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 10939 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 711413000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 711413000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999543 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999543 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65034.555261 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65034.555261 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 81 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 81 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18827.160494 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18827.160494 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 4834.588967 # Cycle average of tags in use +system.l2.tags.total_refs 24554 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 11997 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.046678 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 56.181370 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 746.282898 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 4032.124699 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001715 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.022775 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.123051 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.147540 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 11997 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4386 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 7119 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.366119 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 209109 # Number of tag accesses +system.l2.tags.data_accesses 209109 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 53312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 709312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 762624 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 833 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 11083 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 11916 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 167958363 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2234672917 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2402631280 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 167958363 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 167958363 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 167958363 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2234672917 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2402631280 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 833.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 11086.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 23868 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 11919 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 11919 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 739 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 748 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 680 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 750 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 708 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 701 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 726 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 724 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 801 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 870 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 848 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 808 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 716 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 701 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 731 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 668 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.53 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 64477500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 59595000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 287958750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5409.64 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24159.64 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 10936 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 91.75 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 11919 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 3453 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 3387 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 3862 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1210 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 776.602851 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 580.089826 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 381.700251 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 102 10.39% 10.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 85 8.66% 19.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48 4.89% 23.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23 2.34% 26.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 26 2.65% 28.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.92% 29.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 16 1.63% 31.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 9 0.92% 32.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 664 67.62% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 982 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 762816 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 762816 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2403.24 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2403.24 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 18.78 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 18.78 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 317397000 # Total gap between requests +system.mem_ctrls.avgGap 26629.50 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 53312 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 709504 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 167958363.262888610363 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2235277809.282572746277 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 833 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 11086 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 22622500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 265336250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27157.86 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 23934.35 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 91.75 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3748500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1988580 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 43853880 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 24585600.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 98183640 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 39205440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 211565640 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 666.533212 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 98373750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 10400000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 208638250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3270120 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1738110 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 41240640 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 24585600.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 95921880 # Energy for active background per rank (pJ) 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# Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.904297 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 67646 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67646 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 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WriteReq hits +system.cpu.dcache.WriteReq_hits::total 26205 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 86878 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 86878 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 5428367764 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5428367764 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 113083 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 113083 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.768268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.768268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 62482.651120 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62482.651120 # average WriteReq miss latency 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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 615000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 435.153299 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 73608 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11311 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.507647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 435.153299 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.849909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.849909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 311053 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 311053 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 317412000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 317412000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/libquantum/config.ini b/outoforder/libquantum/config.ini new file mode 100644 index 000000000..f9f6318b8 --- /dev/null +++ b/outoforder/libquantum/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/libquantum/config.json b/outoforder/libquantum/config.json new file mode 100644 index 000000000..7f20b2ad9 --- /dev/null +++ b/outoforder/libquantum/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/libquantum/fs/proc/cpuinfo b/outoforder/libquantum/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/libquantum/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/libquantum/fs/proc/stat b/outoforder/libquantum/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/libquantum/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/libquantum/fs/sys/devices/system/cpu/online b/outoforder/libquantum/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/libquantum/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/libquantum/fs/sys/devices/system/cpu/possible b/outoforder/libquantum/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/libquantum/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/libquantum/ref.out b/outoforder/libquantum/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/libquantum/stats.txt b/outoforder/libquantum/stats.txt new file mode 100644 index 000000000..6306b31b2 --- /dev/null +++ b/outoforder/libquantum/stats.txt @@ -0,0 +1,1343 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 77921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 127557 # Simulator instruction rate (inst/s) +host_mem_usage 850876 # Number of bytes of host memory used +host_op_rate 128782 # Simulator op (including micro ops) rate (op/s) +host_seconds 3.92 # Real time elapsed on the host +host_tick_rate 19877482 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500003 # Number of instructions simulated +sim_ops 504832 # Number of ops (including micro ops) simulated +sim_seconds 0.000078 # Number of seconds simulated +sim_ticks 77921500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.302339 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 70314 # Number of BTB hits +system.cpu.branchPred.BTBLookups 70808 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 783 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 74556 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 15 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 182 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 167 # Number of indirect misses. +system.cpu.branchPred.lookups 77161 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 3886 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 67634 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 3764 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 67756 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 57 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 8267 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 117 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 19 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 8 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 149 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 18 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 49 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8280 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 165 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 60 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 16378 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 359 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 24073 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 181 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 5 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 37 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 13097 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 355 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 50 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 121 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8175 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 24 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 24 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 156 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 50 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 8367 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 78 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 61 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 16379 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 350 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 24076 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 57693 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 7 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 57 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 508 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 50 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 210708 # number of cc regfile reads +system.cpu.cc_regfile_writes 211838 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 551 # The number of times a branch was mispredicted +system.cpu.commit.branches 73188 # Number of branches committed +system.cpu.commit.bw_lim_events 10553 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 10886 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500067 # Number of instructions committed +system.cpu.commit.committedOps 504896 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 113070 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 4.465340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.296748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 32049 28.34% 28.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7532 6.66% 35.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2243 1.98% 36.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1686 1.49% 38.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1162 1.03% 39.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1766 1.56% 41.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2635 2.33% 43.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 53444 47.27% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10553 9.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113070 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 303 # Number of function calls committed. +system.cpu.commit.int_insts 429575 # Number of committed integer instructions. +system.cpu.commit.loads 138548 # Number of loads committed +system.cpu.commit.membars 18 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 10 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 290404 57.52% 57.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 467 0.09% 57.61% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.00% 57.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 254 0.05% 57.66% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1016 0.20% 57.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 395 0.08% 57.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 1397 0.28% 58.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 1397 0.28% 58.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 14 0.00% 58.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 142 0.03% 58.53% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 58.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 32 0.01% 58.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 58.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 37 0.01% 58.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 40 0.01% 58.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 58.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 158 0.03% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 58.58% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 138548 27.44% 86.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 70578 13.98% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 504896 # Class of committed instruction +system.cpu.commit.refs 209126 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 7513 # Number of committed Vector instructions. +system.cpu.committedInsts 500003 # Number of Instructions Simulated +system.cpu.committedOps 504832 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.311688 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.311688 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 26976 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 236 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 70208 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 520454 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 16724 # Number of cycles decode is idle +system.cpu.decode.RunCycles 65431 # Number of cycles decode is running +system.cpu.decode.SquashCycles 583 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 799 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 5064 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 77161 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7035 # Number of cache lines fetched +system.cpu.fetch.Cycles 96386 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 475 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 518676 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.495114 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 17557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 70837 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.328153 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 114778 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 4.579832 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.272070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 36078 31.43% 31.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1462 1.27% 32.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1349 1.18% 33.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1159 1.01% 34.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2004 1.75% 36.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1104 0.96% 37.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1410 1.23% 38.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65665 57.21% 96.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4547 3.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 114778 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 41067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 647 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 74195 # Number of branches executed +system.cpu.iew.exec_nop 100 # number of nop insts executed +system.cpu.iew.exec_rate 3.284873 # Inst execution rate +system.cpu.iew.exec_refs 211263 # number of memory reference insts executed +system.cpu.iew.exec_stores 71270 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1783 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 140267 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 161 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 71911 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 515902 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 139993 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 904 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 511931 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1782 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 583 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1788 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 490 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 101 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1713 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 468 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 179 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 640410 # num instructions consuming a value +system.cpu.iew.wb_count 510629 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.560477 # average fanout of values written-back +system.cpu.iew.wb_producers 358935 # num instructions producing a value +system.cpu.iew.wb_rate 3.276518 # insts written-back per cycle +system.cpu.iew.wb_sent 511237 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 710370 # number of integer regfile reads +system.cpu.int_regfile_writes 360360 # number of integer regfile writes +system.cpu.ipc 3.208335 # IPC: Instructions Per Cycle +system.cpu.ipc_total 3.208335 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 295768 57.67% 57.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 470 0.09% 57.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 9 0.00% 57.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 254 0.05% 57.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1016 0.20% 58.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 395 0.08% 58.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 1399 0.27% 58.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 1399 0.27% 58.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 14 0.00% 58.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 143 0.03% 58.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 38 0.01% 58.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.01% 58.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.01% 58.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 161 0.03% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 140234 27.34% 86.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 71442 13.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 512838 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1381 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002693 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 209 15.13% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 53 3.84% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.07% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.07% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.14% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 19.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 888 64.30% 83.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 227 16.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 506504 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1126563 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 503084 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 518723 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 515766 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 512838 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 87 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8901 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 114778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 4.468086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 3.104646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29255 25.49% 25.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 4516 3.93% 29.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 3470 3.02% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3851 3.36% 35.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4831 4.21% 40.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8460 7.37% 47.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7457 6.50% 53.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 40041 34.89% 88.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12897 11.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 114778 # Number of insts issued each cycle +system.cpu.iq.rate 3.290693 # Inst issue rate +system.cpu.iq.vec_alu_accesses 7704 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 15356 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 7545 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 8041 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 143 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 140267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 71911 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 384325 # number of misc regfile reads +system.cpu.misc_regfile_writes 4546 # number of misc regfile writes +system.cpu.numCycles 155845 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3641 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 576355 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1335 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 19561 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 246 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 966818 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 518388 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 590184 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 67611 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 14155 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 583 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 17686 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 13788 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 718018 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 5696 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 196 # count of serializing insts renamed +system.cpu.rename.skidInsts 26812 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 11778 # Number of vector rename lookups +system.cpu.rob.rob_reads 618039 # The number of ROB reads +system.cpu.rob.rob_writes 1033309 # The number of ROB writes +system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 11402 # number of vector regfile reads +system.cpu.vec_regfile_writes 6325 # number of vector regfile writes +system.cpu.workload.numSyscalls 7 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1286 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1957 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4799 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 586 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution +system.membus.trans_dist::ReadExResp 183 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 586 # Transaction distribution +system.membus.trans_dist::InvalidateReq 517 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2055 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 49216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 49216 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1286 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1286 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1286 # Request fanout histogram +system.membus.reqLayer0.occupancy 1520500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4080250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 784 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1722 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 123 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 112 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 496 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 288 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 519 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 519 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1115 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 6526 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7641 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 39616 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 227136 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 266752 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2842 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000352 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.018758 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2841 99.96% 99.96% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.04% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2842 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 4244500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 5.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 3000000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 3.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 744000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 11 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1543 # number of demand (read+write) hits +system.l2.demand_hits::total 1554 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 11 # number of overall hits +system.l2.overall_hits::.cpu.data 1543 # number of overall hits +system.l2.overall_hits::total 1554 # number of overall hits +system.l2.demand_misses::.cpu.inst 485 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 284 # number of demand (read+write) misses +system.l2.demand_misses::total 769 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 485 # number of overall misses +system.l2.overall_misses::.cpu.data 284 # number of overall misses +system.l2.overall_misses::total 769 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 38718000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 23089500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 61807500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 38718000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 23089500 # number of overall miss cycles +system.l2.overall_miss_latency::total 61807500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 496 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1827 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2323 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 496 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1827 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2323 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.977823 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.155446 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.331037 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.977823 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.155446 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.331037 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79830.927835 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81301.056338 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80373.862159 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79830.927835 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81301.056338 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80373.862159 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 485 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 284 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 769 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 485 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 284 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 769 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 33868000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 20249500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 54117500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 33868000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 20249500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 54117500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.977823 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.155446 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.331037 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.977823 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.155446 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.331037 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69830.927835 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71301.056338 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70373.862159 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69830.927835 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71301.056338 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70373.862159 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1722 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1722 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1722 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1722 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 123 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 123 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 123 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 123 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1356 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1356 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 183 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 183 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 14521500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 14521500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1539 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.118908 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.118908 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79352.459016 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79352.459016 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 183 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 183 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 12691500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 12691500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.118908 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.118908 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69352.459016 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69352.459016 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 11 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 485 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 485 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 38718000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 38718000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.977823 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.977823 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79830.927835 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79830.927835 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 485 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 485 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 33868000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 33868000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.977823 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.977823 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69830.927835 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69830.927835 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 187 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 187 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 101 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 8568000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 8568000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 288 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 288 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.350694 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.350694 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 84831.683168 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 84831.683168 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 101 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 7558000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 7558000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.350694 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.350694 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 74831.683168 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 74831.683168 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 517 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 517 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 519 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 519 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.996146 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.996146 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 517 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 517 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 9885500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 9885500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.996146 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.996146 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19120.889749 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19120.889749 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 678.880608 # Cycle average of tags in use +system.l2.tags.total_refs 4281 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 981 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 4.363914 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 109.181954 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 378.622224 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 191.076431 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003332 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.011555 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.005831 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.020718 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 979 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 915 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.029877 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 39365 # Number of tag accesses +system.l2.tags.data_accesses 39365 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 31040 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 18176 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 49216 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 31040 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 31040 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 485 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 284 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 769 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 398349621 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 233260397 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 631610018 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 398349621 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 398349621 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 398349621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 233260397 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 631610018 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 485.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 284.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000574000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 1506 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 769 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 769 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 157 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 69 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 117 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 29 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 87 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 8027000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 3845000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 22445750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10438.23 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29188.23 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 589 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.59 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 769 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 406 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 232 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 91 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 180 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 273.422222 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 173.167321 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 285.322320 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 63 35.00% 35.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 45 25.00% 60.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 35 19.44% 79.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 5 2.78% 82.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 5 2.78% 85.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 3.89% 88.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 2.78% 91.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 1.11% 92.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 7.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 180 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 49216 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 49216 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 631.61 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 631.61 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.93 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.93 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 73151500 # Total gap between requests +system.mem_ctrls.avgGap 95125.49 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 31040 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 18176 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 398349621.093023121357 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 233260396.681275397539 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 485 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 284 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 13904500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8541250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28669.07 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 30074.82 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 76.59 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 357000 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 189750 # Energy for precharge commands per rank (pJ) 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latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77055.467188 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 144 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 496 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 39589499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39589499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.070515 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.070515 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79817.538306 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79817.538306 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 300.123792 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6890 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.891129 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 300.123792 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.586179 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.586179 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 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replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 139132 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 139132 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 460 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 460 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 19300500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19300500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 139592 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 139592 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.003295 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003295 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 41957.608696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41957.608696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 174 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 286 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 286 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10826500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10826500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 37854.895105 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37854.895105 # average ReadReq mshr miss latency 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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20245.134241 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 24 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.083333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 516 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 516 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 16680590 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 16680590 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 516 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 516 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32326.724806 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32326.724806 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 516 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 516 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 16164590 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 16164590 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31326.724806 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31326.724806 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 21 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 18 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 18 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 18 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 18 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 360.886272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 189840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 80.920716 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 360.886272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.704856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.704856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 422776 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 422776 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 77921500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 77921500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/mcf/config.ini b/outoforder/mcf/config.ini new file mode 100644 index 000000000..9a54f4a24 --- /dev/null +++ b/outoforder/mcf/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//data/ref/input/inp.in +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=inp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/mcf/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/mcf/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/mcf/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/mcf/config.json b/outoforder/mcf/config.json new file mode 100644 index 000000000..31039c0a7 --- /dev/null +++ b/outoforder/mcf/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "outoforder/mcf/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "outoforder/mcf/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "outoforder/mcf/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/mcf/fs/proc/cpuinfo b/outoforder/mcf/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/mcf/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/mcf/fs/proc/stat b/outoforder/mcf/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/mcf/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/mcf/fs/sys/devices/system/cpu/online b/outoforder/mcf/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/mcf/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/mcf/fs/sys/devices/system/cpu/possible b/outoforder/mcf/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/mcf/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/mcf/inp.out b/outoforder/mcf/inp.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/mcf/stats.txt b/outoforder/mcf/stats.txt new file mode 100644 index 000000000..4c909c6d0 --- /dev/null +++ b/outoforder/mcf/stats.txt @@ -0,0 +1,1361 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 264692500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 95843 # Simulator instruction rate (inst/s) +host_mem_usage 850776 # Number of bytes of host memory used +host_op_rate 108768 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.22 # Real time elapsed on the host +host_tick_rate 50729222 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500007 # Number of instructions simulated +sim_ops 567519 # Number of ops (including micro ops) simulated +sim_seconds 0.000265 # Number of seconds simulated +sim_ticks 264692500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.730970 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 46369 # Number of BTB hits +system.cpu.branchPred.BTBLookups 46965 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 771 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 91817 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1546 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 202 # Number of indirect misses. +system.cpu.branchPred.lookups 114935 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 58884 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 30226 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 58216 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 30894 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 42 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 3273 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2056 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1471 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2100 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 297 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 593 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 627 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 111 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 110 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 69 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 31 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 23 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 77073 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 346 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 583 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2687 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 893 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2025 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 295 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2419 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 594 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 293 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 627 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 299 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 291 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 111 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 181 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 118 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 11403 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 38 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 5848 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 234708 # number of cc regfile reads +system.cpu.cc_regfile_writes 222669 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 529 # The number of times a branch was mispredicted +system.cpu.commit.branches 111003 # Number of branches committed +system.cpu.commit.bw_lim_events 31353 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 11839 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500326 # Number of instructions committed +system.cpu.commit.committedOps 567838 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 466917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.216143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.306191 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 304830 65.29% 65.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 56068 12.01% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29315 6.28% 83.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15284 3.27% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 12901 2.76% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3887 0.83% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7528 1.61% 92.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5751 1.23% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 31353 6.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 466917 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 5524 # Number of function calls committed. +system.cpu.commit.int_insts 493938 # Number of committed integer instructions. +system.cpu.commit.loads 85388 # Number of loads committed +system.cpu.commit.membars 626 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 413 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385176 67.83% 67.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2986 0.53% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 947 0.17% 68.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 945 0.17% 68.76% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 834 0.15% 68.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 1130 0.20% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.11% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85388 15.04% 84.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 90016 15.85% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 567838 # Class of committed instruction +system.cpu.commit.refs 175404 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 9935 # Number of committed Vector instructions. +system.cpu.committedInsts 500007 # Number of Instructions Simulated +system.cpu.committedOps 567519 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.058757 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058757 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 185113 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 245 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 46419 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 583641 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 173231 # Number of cycles decode is idle +system.cpu.decode.RunCycles 104879 # Number of cycles decode is running +system.cpu.decode.SquashCycles 610 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 4907 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 114935 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 76589 # Number of cache lines fetched +system.cpu.fetch.Cycles 258777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 495 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 519644 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1704 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.217110 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 209058 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 53763 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.981598 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 468740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.257497 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.532477 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 352356 75.17% 75.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 12153 2.59% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10797 2.30% 80.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14664 3.13% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18956 4.04% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 10263 2.19% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3350 0.71% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5147 1.10% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 41054 8.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 468740 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 60646 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 619 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 112177 # Number of branches executed +system.cpu.iew.exec_nop 351 # number of nop insts executed +system.cpu.iew.exec_rate 1.108307 # Inst execution rate +system.cpu.iew.exec_refs 188762 # number of memory reference insts executed +system.cpu.iew.exec_stores 91174 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1890 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 87046 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 91807 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 579979 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 97588 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 742 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 586722 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 5541 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 610 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5552 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 707 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5366 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 8309 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1787 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 551526 # num instructions consuming a value +system.cpu.iew.wb_count 574836 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.512792 # average fanout of values written-back +system.cpu.iew.wb_producers 282818 # num instructions producing a value +system.cpu.iew.wb_rate 1.085854 # insts written-back per cycle +system.cpu.iew.wb_sent 575392 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 666101 # number of integer regfile reads +system.cpu.int_regfile_writes 383834 # number of integer regfile writes +system.cpu.ipc 0.944504 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944504 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 431 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 390886 66.54% 66.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2989 0.51% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1003 0.17% 67.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1000 0.17% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 872 0.15% 67.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 1166 0.20% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97779 16.64% 84.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 91338 15.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 587467 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14351 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024429 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3069 21.39% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 21.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3994 27.83% 49.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7284 50.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 590368 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1636373 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 564649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 580732 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 578968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 587467 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 12092 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 7830 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 468740 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.253290 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.968210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 284816 60.76% 60.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43908 9.37% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36692 7.83% 77.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 32332 6.90% 84.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25095 5.35% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19973 4.26% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 13658 2.91% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7142 1.52% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5124 1.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 468740 # Number of insts issued each cycle +system.cpu.iq.rate 1.109714 # Inst issue rate +system.cpu.iq.vec_alu_accesses 11019 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 21724 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 10187 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 11023 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 8057 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3889 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 87046 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91807 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 400377 # number of misc regfile reads +system.cpu.misc_regfile_writes 2505 # number of misc regfile writes +system.cpu.numCycles 529386 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 6229 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 605477 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2973 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 175253 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 119 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 936864 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 581793 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 619189 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 108011 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 47886 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 610 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 53244 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 661666 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 125393 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1958 # count of serializing insts renamed +system.cpu.rename.skidInsts 19550 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 661 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 12901 # Number of vector rename lookups +system.cpu.rob.rob_reads 1014591 # The number of ROB reads +system.cpu.rob.rob_writes 1161200 # The number of ROB writes +system.cpu.timesIdled 3889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 12450 # number of vector regfile reads +system.cpu.vec_regfile_writes 5202 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2656 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 7798 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 16467 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 948 # Transaction distribution +system.membus.trans_dist::ReadExReq 1693 # Transaction distribution +system.membus.trans_dist::ReadExResp 1693 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 948 # Transaction distribution +system.membus.trans_dist::InvalidateReq 15 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5297 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5297 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 169024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 169024 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2656 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2656 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2656 # Request fanout histogram +system.membus.reqLayer0.occupancy 3131000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 13728250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 6946 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1828 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 5547 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 423 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1708 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1708 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 5906 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1040 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 15 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 15 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 17359 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 7777 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 25136 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 732992 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 292864 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1025856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 8669 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.010740 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 8668 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 8669 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 15608500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 5.9 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 4129500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 8859000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 3.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 5386 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 627 # number of demand (read+write) hits +system.l2.demand_hits::total 6013 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 5386 # number of overall hits +system.l2.overall_hits::.cpu.data 627 # number of overall hits +system.l2.overall_hits::total 6013 # number of overall hits +system.l2.demand_misses::.cpu.inst 520 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2121 # number of demand (read+write) misses +system.l2.demand_misses::total 2641 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 520 # number of overall misses +system.l2.overall_misses::.cpu.data 2121 # number of overall misses +system.l2.overall_misses::total 2641 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40890000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 183916500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 224806500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40890000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 183916500 # number of overall miss cycles +system.l2.overall_miss_latency::total 224806500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 5906 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2748 # number of demand (read+write) accesses +system.l2.demand_accesses::total 8654 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 5906 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2748 # number of overall (read+write) accesses +system.l2.overall_accesses::total 8654 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.088046 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.771834 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.305177 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.088046 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.771834 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.305177 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 86712.164074 # average overall miss latency +system.l2.demand_avg_miss_latency::total 85121.734192 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 86712.164074 # average overall miss latency +system.l2.overall_avg_miss_latency::total 85121.734192 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 520 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2121 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2641 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 520 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2121 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2641 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35690000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 162706500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35690000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 162706500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.088046 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.771834 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.305177 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.088046 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.771834 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.305177 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 76712.164074 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 75121.734192 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 76712.164074 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 75121.734192 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1828 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1828 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1828 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1828 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 5546 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 5546 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 5546 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 5546 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 15 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 15 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 1693 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 1693 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 143068000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 143068000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1708 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1708 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.991218 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.991218 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 84505.611341 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 84505.611341 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 1693 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 1693 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 126138000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 126138000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.991218 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.991218 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 74505.611341 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 74505.611341 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 5386 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 5386 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 5906 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 5906 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.088046 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.088046 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.088046 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.088046 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 612 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 612 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 428 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 428 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 40848500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 40848500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1040 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1040 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.411538 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.411538 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 95440.420561 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 95440.420561 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 428 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 428 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 36568500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 36568500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.411538 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.411538 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 85440.420561 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 85440.420561 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 15 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 15 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18966.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18966.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1531.745481 # Cycle average of tags in use +system.l2.tags.total_refs 16451 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2654 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 6.198568 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 9.752263 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 486.606587 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1035.386630 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000298 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.014850 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.031597 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.046745 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2654 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 741 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1829 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.080994 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 134382 # Number of tag accesses +system.l2.tags.data_accesses 134382 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33280 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 135744 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 169024 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 520 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2121 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2641 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 125730801 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 512836593 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 638567394 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 125730801 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 125730801 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 125730801 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 512836593 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 638567394 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 520.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2121.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000696500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5276 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2641 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2641 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 194 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 147 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 294 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 133 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 162 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 146 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 181 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 148 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 145 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 191 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.53 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 39623500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 13205000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 89142250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 15003.22 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 33753.22 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2307 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.35 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2641 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1297 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 630 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 380 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 323 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 333 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 506.426426 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 311.531063 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 408.329271 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 63 18.92% 18.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 84 25.23% 44.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 19 5.71% 49.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 5.11% 54.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 14 4.20% 59.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 3.30% 62.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.40% 64.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 19 5.71% 70.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 98 29.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 333 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 169024 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 169024 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 638.57 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 638.57 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.99 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.99 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 264198000 # Total gap between requests +system.mem_ctrls.avgGap 100037.11 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33280 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 135744 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 125730800.834931105375 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 512836593.405555546284 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 520 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2121 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14303500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 74838750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27506.73 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 35284.65 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 87.35 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1120980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 592020 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 8296680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 108620340 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 10172160 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 149085300 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 563.239608 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 25543500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8580000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 230569000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1263780 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 671715 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 10560060 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 84573180 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 30422400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 147774255 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 558.286521 # Core power per rank (mW) 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cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 714 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.088235 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1828 # number of writebacks +system.cpu.dcache.writebacks::total 1828 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2543 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2543 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2543 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2543 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 2760 # number of demand (read+write) MSHR misses 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cycles +system.cpu.dcache.WriteReq_miss_latency::total 263688622 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 89381 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 89381 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.037670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78315.599050 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78315.599050 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1659 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1659 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1708 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1708 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 146524950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 146524950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.019109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.019109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 85787.441452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85787.441452 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 319 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 319 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 27 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 27 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 346 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 346 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.078035 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.078035 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.005780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 337 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 337 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 299 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 299 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 4322000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4322000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 636 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 636 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.470126 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.470126 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 14454.849498 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14454.849498 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 298 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 298 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.001572 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001572 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 626 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 626 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 626 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 626 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 439.742165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169419 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 61.317047 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 439.742165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.858871 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.858871 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 347333 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 347333 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 264692500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 264692500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/milc/config.ini b/outoforder/milc/config.ini new file mode 100644 index 000000000..6e3bd3d1d --- /dev/null +++ b/outoforder/milc/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//data/ref/input/su3imp.in +kvmInSE=false +maxStackSize=67108864 +output=su3imp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/milc/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/milc/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/milc/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/milc/config.json b/outoforder/milc/config.json new file mode 100644 index 000000000..e3c2a1911 --- /dev/null +++ b/outoforder/milc/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "outoforder/milc/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "outoforder/milc/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": 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"beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/milc/fs/proc/cpuinfo b/outoforder/milc/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/milc/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/milc/fs/proc/stat b/outoforder/milc/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/milc/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/milc/fs/sys/devices/system/cpu/online b/outoforder/milc/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/milc/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/milc/fs/sys/devices/system/cpu/possible b/outoforder/milc/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/milc/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/milc/stats.txt b/outoforder/milc/stats.txt new file mode 100644 index 000000000..f97a0e419 --- /dev/null +++ b/outoforder/milc/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 394634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 84837 # Simulator instruction rate (inst/s) +host_mem_usage 852204 # Number of bytes of host memory used +host_op_rate 88189 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.89 # Real time elapsed on the host +host_tick_rate 66955501 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_ops 519782 # Number of ops (including micro ops) simulated +sim_seconds 0.000395 # Number of seconds simulated +sim_ticks 394634500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.662235 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 34674 # Number of BTB hits +system.cpu.branchPred.BTBLookups 35504 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1066 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 24549 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 82 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 306 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 224 # Number of indirect misses. +system.cpu.branchPred.lookups 75243 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 11438 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 4278 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 8488 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 7228 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 18 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 234 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 319 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 751 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 274 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 38 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 137 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 222 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 81 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 154 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 133 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 369 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 373 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 220 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 653 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 37 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 87 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 101 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 10 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 36 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 10035 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 387 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 174 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 920 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 62 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 104 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 8 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 132 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 221 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 59 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 154 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 80 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 240 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 100 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 370 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 829 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 778 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 94 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 29 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 4962 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 14 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 70 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 24684 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 38649 # number of cc regfile reads +system.cpu.cc_regfile_writes 38403 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 763 # The number of times a branch was mispredicted +system.cpu.commit.branches 46517 # Number of branches committed +system.cpu.commit.bw_lim_events 32074 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 169 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 251381 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500214 # Number of instructions committed +system.cpu.commit.committedOps 519996 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 708256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.734192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832190 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 523244 73.88% 73.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98580 13.92% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 30877 4.36% 92.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 5138 0.73% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10383 1.47% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3423 0.48% 94.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2750 0.39% 95.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1787 0.25% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32074 4.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 708256 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 15117 # Number of function calls committed. +system.cpu.commit.int_insts 508795 # Number of committed integer instructions. +system.cpu.commit.loads 80724 # Number of loads committed +system.cpu.commit.membars 142 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 35 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 264515 50.87% 50.88% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 76922 14.79% 65.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 29279 5.63% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 83 0.02% 71.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 138 0.03% 71.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 140 0.03% 71.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 103 0.02% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 80724 15.52% 86.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 68057 13.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 519996 # Class of committed instruction +system.cpu.commit.refs 148781 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1073 # Number of committed Vector instructions. +system.cpu.committedInsts 500000 # Number of Instructions Simulated +system.cpu.committedOps 519782 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.578540 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.578540 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 536534 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 305 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 34659 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 868569 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 70465 # Number of cycles decode is idle +system.cpu.decode.RunCycles 107286 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2662 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1033 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 24483 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 75243 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 108258 # Number of cache lines fetched +system.cpu.fetch.Cycles 612404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1571 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 879551 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 5930 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.095332 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 126000 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 59440 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.114385 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 741430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.230815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.583832 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 573209 77.31% 77.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 12393 1.67% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27011 3.64% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9062 1.22% 83.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13274 1.79% 85.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17605 2.37% 88.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14026 1.89% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5115 0.69% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69735 9.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 741430 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 47840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 1768 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 67881 # Number of branches executed +system.cpu.iew.exec_nop 270 # number of nop insts executed +system.cpu.iew.exec_rate 0.961391 # Inst execution rate +system.cpu.iew.exec_refs 236791 # number of memory reference insts executed +system.cpu.iew.exec_stores 99636 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 162124 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 137767 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 214 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 114619 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 848825 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 137155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1761 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 758797 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8166 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 23395 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2662 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 35772 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 1777 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 139 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 57030 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 46546 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1548 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 798522 # num instructions consuming a value +system.cpu.iew.wb_count 726234 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.644928 # average fanout of values written-back +system.cpu.iew.wb_producers 514989 # num instructions producing a value +system.cpu.iew.wb_rate 0.920134 # insts written-back per cycle +system.cpu.iew.wb_sent 757854 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1114660 # number of integer regfile reads +system.cpu.int_regfile_writes 626145 # number of integer regfile writes +system.cpu.ipc 0.633497 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.633497 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 392594 51.62% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 97010 12.76% 64.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 33029 4.34% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 85 0.01% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 140 0.02% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 140 0.02% 68.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 107 0.01% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 137603 18.09% 86.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 99817 13.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 760560 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 569963 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.749399 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3745 0.66% 0.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 296923 52.10% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 259424 45.52% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 98.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5649 0.99% 99.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4219 0.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1329286 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2842891 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 725144 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1175947 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 848341 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 760560 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 328675 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12740 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 252846 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 741430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.025801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.612910 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 439908 59.33% 59.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 98918 13.34% 72.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 88098 11.88% 84.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 47640 6.43% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22785 3.07% 94.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23188 3.13% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11492 1.55% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8714 1.18% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 687 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 741430 # Number of insts issued each cycle +system.cpu.iq.rate 0.963625 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1202 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2360 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1090 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1315 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2085 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 117 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 137767 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 114619 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 464473 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.numCycles 789270 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 225171 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 460424 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 46219 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 76105 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 125 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1358709 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 857035 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 750721 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 120646 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 253872 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 2662 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 303814 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 290211 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1308001 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 13032 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 390 # count of serializing insts renamed +system.cpu.rename.skidInsts 112277 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 223 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1492 # Number of vector rename lookups +system.cpu.rob.rob_reads 1423158 # The number of ROB reads +system.cpu.rob.rob_writes 1576040 # The number of ROB writes +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1321 # number of vector regfile reads +system.cpu.vec_regfile_writes 571 # number of vector regfile writes +system.cpu.workload.numSyscalls 26 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 5312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 13525 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 7743 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 25 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 16163 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 25 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 753 # Transaction distribution +system.membus.trans_dist::WritebackDirty 5291 # Transaction distribution +system.membus.trans_dist::CleanEvict 21 # Transaction distribution +system.membus.trans_dist::ReadExReq 7453 # Transaction distribution +system.membus.trans_dist::ReadExResp 7451 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 753 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 21729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 21729 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 863680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 863680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 8213 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 8213 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 8213 # Request fanout histogram +system.membus.reqLayer0.occupancy 36986500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 9.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 43105000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 959 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 12609 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 412 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 59 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 7454 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 7452 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 816 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 143 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 7 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 7 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2044 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 22537 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 24581 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 78592 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 954432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1033024 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 5337 # Total snoops (count) +system.tol2bus.snoopTraffic 338624 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 13757 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001890 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.043434 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 13731 99.81% 99.81% # Request fanout histogram +system.tol2bus.snoop_fanout::1 26 0.19% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 13757 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 15811500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 4.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 11396000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1224000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 203 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4 # number of demand (read+write) hits +system.l2.demand_hits::total 207 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 203 # number of overall hits +system.l2.overall_hits::.cpu.data 4 # number of overall hits +system.l2.overall_hits::total 207 # number of overall hits +system.l2.demand_misses::.cpu.inst 613 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 7593 # number of demand (read+write) misses +system.l2.demand_misses::total 8206 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 613 # number of overall misses +system.l2.overall_misses::.cpu.data 7593 # number of overall misses +system.l2.overall_misses::total 8206 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 47921500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 649532000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 697453500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 47921500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 649532000 # number of overall miss cycles +system.l2.overall_miss_latency::total 697453500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 816 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 7597 # number of demand (read+write) accesses +system.l2.demand_accesses::total 8413 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 816 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 7597 # number of overall (read+write) accesses +system.l2.overall_accesses::total 8413 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.751225 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999473 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.975395 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.751225 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999473 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.975395 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85543.526933 # average overall miss latency +system.l2.demand_avg_miss_latency::total 84993.114794 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85543.526933 # average overall miss latency +system.l2.overall_avg_miss_latency::total 84993.114794 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 5291 # number of writebacks +system.l2.writebacks::total 5291 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 613 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 7593 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 8206 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 613 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 7593 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 8206 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 41791500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 573622000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 615413500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 41791500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 573622000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 615413500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999473 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.975395 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999473 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.975395 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75546.160938 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 74995.552035 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75546.160938 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 74995.552035 # average overall mshr miss latency +system.l2.replacements 5337 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 7318 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 7318 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 7318 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 7318 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 411 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 411 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 411 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 411 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 7453 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 7453 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 637472000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 637472000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 7454 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 7454 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999866 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999866 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85532.268885 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85532.268885 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 7453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 7453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 562962000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 562962000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999866 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999866 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75534.952368 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75534.952368 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2372.997442 # Cycle average of tags in use +system.l2.tags.total_refs 16153 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 8207 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.968198 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.441749 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 557.053842 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1814.501850 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000044 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.017000 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.055374 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.072418 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2870 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1842 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 822 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.087585 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 137503 # Number of tag accesses +system.l2.tags.data_accesses 137503 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 39232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 485952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 525184 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 338624 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 338624 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 613 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 7593 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 8206 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 5291 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 5291 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 99413508 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1231397660 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1330811168 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 99413508 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 99413508 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 858069936 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 858069936 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 858069936 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 99413508 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1231397660 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2188881104 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 5291.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 613.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 7593.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000013500250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 329 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 329 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 21072 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 4941 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 8206 # Number of read requests accepted +system.mem_ctrls.writeReqs 5291 # Number of write requests accepted +system.mem_ctrls.readBursts 8206 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 5291 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 512 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 525 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 574 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 501 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 502 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 491 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 490 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 472 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 585 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 497 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 538 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 468 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 491 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 548 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 520 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 492 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 334 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 325 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 328 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 333 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 330 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 17.58 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 117301250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 41030000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 271163750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 14294.57 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 33044.57 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 7050 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 4569 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 85.91 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.35 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 8206 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 5291 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 4028 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 3834 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 207 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 128 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 334 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 329 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1841 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 464.130364 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 420.174497 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 142.399256 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 99 5.38% 5.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 108 5.87% 11.24% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 28 1.52% 12.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 88 4.78% 17.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1490 80.93% 98.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 0.43% 98.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 0.16% 99.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 0.22% 99.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 0.71% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1841 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 329 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 24.924012 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.272522 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 161.535308 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 328 99.70% 99.70% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2944-3071 1 0.30% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 329 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 329 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.018237 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.015495 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.330791 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 328 99.70% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.30% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 329 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 525184 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 337280 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 525184 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 338624 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1330.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 854.66 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1330.81 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 858.07 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 17.07 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.40 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 6.68 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 394581500 # Total gap between requests +system.mem_ctrls.avgGap 29234.76 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 39232 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 485952 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 337280 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 99413507.942159131169 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1231397660.366744518280 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 854664252.618562221527 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 613 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 7593 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 5291 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 16555500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 254608250 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 6416270250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27007.34 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33531.97 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 1212676.29 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 86.09 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 6783000 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 3574890 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 29552460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 13765140 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 30732000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 169681020 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 8650560 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 262739070 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 665.778258 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 21115250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 13000000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 360519250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6475980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3411705 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 29038380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 13744260 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 30732000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 170917350 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 7609440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 261929115 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 663.725840 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 18430750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 13000000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 363203750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 107265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 107265 # number of overall hits +system.cpu.icache.overall_hits::total 107265 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 993 # number of overall misses +system.cpu.icache.overall_misses::total 993 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 62276498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62276498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 62276498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62276498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 108258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 108258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 108258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 108258 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.009173 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009173 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.009173 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009173 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 62715.506546 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62715.506546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 62715.506546 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62715.506546 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 943 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.583333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 412 # number of writebacks +system.cpu.icache.writebacks::total 412 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 177 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 816 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 816 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 816 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 816 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 51375498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51375498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 51375498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51375498 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.007538 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007538 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.007538 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007538 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62960.169118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62960.169118 # average overall mshr miss latency +system.cpu.icache.replacements 412 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 107265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107265 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 62276498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62276498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 108258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 108258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.009173 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009173 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 62715.506546 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62715.506546 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 51375498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51375498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.007538 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007538 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 62960.169118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62960.169118 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 387.662594 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 108081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 816 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 132.452206 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 387.662594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.757154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.757154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 404 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 217332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 217332 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 141391 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 141391 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 141442 # number of overall hits +system.cpu.dcache.overall_hits::total 141442 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 63096 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 63096 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 63101 # number of overall misses +system.cpu.dcache.overall_misses::total 63101 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 4799519236 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4799519236 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 4799519236 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4799519236 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 204487 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 204487 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 204543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 204543 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.308558 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.308558 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.308497 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.308497 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 76066.933498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76066.933498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 76060.906103 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76060.906103 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 47848 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1793 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.686001 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 7318 # number of writebacks +system.cpu.dcache.writebacks::total 7318 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 55496 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 55496 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 55496 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 55496 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 7600 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7600 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 7603 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 7603 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 660691996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 660691996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 660926496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 660926496 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.037166 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037166 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.037171 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037171 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 86933.157368 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86933.157368 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 86929.698277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86929.698277 # average overall mshr miss latency +system.cpu.dcache.replacements 7331 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 136256 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136256 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 295 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 295 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 23351500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23351500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 136551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 136551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.002160 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 79157.627119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79157.627119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.001018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 84978.417266 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84978.417266 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5135 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5135 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 62794 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 62794 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 4775945238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4775945238 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 67929 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 67929 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.924406 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.924406 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 76057.350033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76057.350033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 55340 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 55340 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 7454 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 7454 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 648664498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 648664498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.109732 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.109732 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 87022.336732 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87022.336732 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 51 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 56 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.089286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 234500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.053571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 264000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 259.223775 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 149352 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 7602 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.646409 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 259.223775 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.506296 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.506296 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.529297 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 417306 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 417306 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 394634500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 394634500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/milc/su3imp.out b/outoforder/milc/su3imp.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/namd/config.ini b/outoforder/namd/config.ini new file mode 100644 index 000000000..a5e2cdb12 --- /dev/null +++ b/outoforder/namd/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 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+response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross --input /home/min/a/ece565/benchspec-2020/CPU2006/444.namd//data/all/input/namd.input --iterations 1 --output namd.out +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=namd.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/namd/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/namd/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/namd/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/namd/config.json b/outoforder/namd/config.json new file mode 100644 index 000000000..1876f1b92 --- /dev/null +++ b/outoforder/namd/config.json @@ -0,0 +1,1816 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { 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1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/namd/fs/proc/cpuinfo b/outoforder/namd/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/namd/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/namd/fs/proc/stat b/outoforder/namd/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/namd/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/namd/fs/sys/devices/system/cpu/online b/outoforder/namd/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/namd/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/namd/fs/sys/devices/system/cpu/possible b/outoforder/namd/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/namd/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/namd/namd.stdout b/outoforder/namd/namd.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/namd/stats.txt b/outoforder/namd/stats.txt new file mode 100644 index 000000000..893f999e8 --- /dev/null +++ b/outoforder/namd/stats.txt @@ -0,0 +1,1346 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 194800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 124503 # Simulator instruction rate (inst/s) +host_mem_usage 853404 # Number of bytes of host memory used +host_op_rate 138874 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.02 # Real time elapsed on the host +host_tick_rate 48501377 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500003 # Number of instructions simulated +sim_ops 557766 # Number of ops (including micro ops) simulated +sim_seconds 0.000195 # Number of seconds simulated +sim_ticks 194800500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.769541 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 59088 # Number of BTB hits +system.cpu.branchPred.BTBLookups 60436 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 3335 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 100170 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1356 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1766 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 410 # Number of indirect misses. +system.cpu.branchPred.lookups 129707 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 51437 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 31604 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 49516 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 33525 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 221 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 78 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5830 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1661 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1095 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 302 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2686 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 466 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 750 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 829 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 616 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 401 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 810 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 379 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 645 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 576 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 406 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 237 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 184 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 257 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 344 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 390 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 243 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 826 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 156 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 599 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 61888 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 948 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1728 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 746 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2171 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1576 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1565 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 466 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2946 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1054 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 815 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 601 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 561 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 697 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 373 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 746 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 470 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 553 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 627 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 335 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 352 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 366 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 500 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 17362 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 318 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 671 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 7357 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 107 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 200223 # number of cc regfile reads +system.cpu.cc_regfile_writes 197194 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2872 # The number of times a branch was mispredicted +system.cpu.commit.branches 108156 # Number of branches committed +system.cpu.commit.bw_lim_events 26300 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 282 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 70150 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500917 # Number of instructions committed +system.cpu.commit.committedOps 558680 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 318270 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.755365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.491777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 142640 44.82% 44.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70251 22.07% 66.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 30591 9.61% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18531 5.82% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11045 3.47% 85.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4916 1.54% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5478 1.72% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8518 2.68% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 26300 8.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 318270 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 6254 # Number of function calls committed. +system.cpu.commit.int_insts 493178 # Number of committed integer instructions. +system.cpu.commit.loads 86590 # Number of loads committed +system.cpu.commit.membars 271 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 185 0.03% 0.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 402415 72.03% 72.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1715 0.31% 72.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 422 0.08% 72.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 201 0.04% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 15 0.00% 72.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21 0.00% 72.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 9 0.00% 72.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 749 0.13% 72.62% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.62% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 433 0.08% 72.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 647 0.12% 72.82% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 598 0.11% 72.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 526 0.09% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 73.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 86590 15.50% 88.52% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 64148 11.48% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 558680 # Class of committed instruction +system.cpu.commit.refs 150738 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 6484 # Number of committed Vector instructions. +system.cpu.committedInsts 500003 # Number of Instructions Simulated +system.cpu.committedOps 557766 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.779199 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.779199 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 68166 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 477 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 58583 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 651837 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 128591 # Number of cycles decode is idle +system.cpu.decode.RunCycles 124538 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2983 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1653 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 4261 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 129707 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 97874 # Number of cache lines fetched +system.cpu.fetch.Cycles 182246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1636 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 598292 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6892 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.332922 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 142784 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67801 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.535649 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 328539 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.036139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.945085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 191612 58.32% 58.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 17917 5.45% 63.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18312 5.57% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14978 4.56% 73.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12999 3.96% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 10832 3.30% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11446 3.48% 84.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8900 2.71% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 41543 12.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 328539 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 61063 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3142 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 114538 # Number of branches executed +system.cpu.iew.exec_nop 984 # number of nop insts executed +system.cpu.iew.exec_rate 1.547641 # Inst execution rate +system.cpu.iew.exec_refs 167608 # number of memory reference insts executed +system.cpu.iew.exec_stores 69031 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 10503 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 99050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 304 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2546 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 72307 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 629195 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 98577 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4526 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 602964 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 49 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 231 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2983 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 305 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 6409 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 92 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 50 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 5257 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 12454 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 8159 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 50 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2098 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1044 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 534052 # num instructions consuming a value +system.cpu.iew.wb_count 594867 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.567553 # average fanout of values written-back +system.cpu.iew.wb_producers 303103 # num instructions producing a value +system.cpu.iew.wb_rate 1.526858 # insts written-back per cycle +system.cpu.iew.wb_sent 596245 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 681567 # number of integer regfile reads +system.cpu.int_regfile_writes 429282 # number of integer regfile writes +system.cpu.ipc 1.283369 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.283369 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 205 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 432304 71.16% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1848 0.30% 71.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 423 0.07% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 204 0.03% 71.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7 0.00% 71.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 71.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 22 0.00% 71.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 9 0.00% 71.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 885 0.15% 71.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 1 0.00% 71.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 490 0.08% 71.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 729 0.12% 71.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 662 0.11% 72.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 561 0.09% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 72.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99709 16.41% 88.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 69423 11.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 607498 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 9738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016030 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3896 40.01% 40.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 124 1.27% 41.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 16 0.16% 41.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 1 0.01% 41.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 37 0.38% 41.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 41.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.03% 41.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 32 0.33% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 42.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1800 18.48% 60.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3828 39.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 608603 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1537129 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 587187 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 688964 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 627907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 607498 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 304 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 70424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 344 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 49848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 328539 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.849089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.085253 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 127505 38.81% 38.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55371 16.85% 55.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 40995 12.48% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 32990 10.04% 78.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28739 8.75% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18471 5.62% 92.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 13201 4.02% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5486 1.67% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5781 1.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328539 # Number of insts issued each cycle +system.cpu.iq.rate 1.559278 # Inst issue rate +system.cpu.iq.vec_alu_accesses 8428 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 16480 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 7680 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 9717 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 5440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4851 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 99050 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 72307 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 413197 # number of misc regfile reads +system.cpu.misc_regfile_writes 1337 # number of misc regfile writes +system.cpu.numCycles 389602 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 11519 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 593366 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2186 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 130997 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 718 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 197 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 975303 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 643921 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 685505 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 126261 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 24950 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 2983 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 29024 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 92099 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 726433 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 27755 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 1268 # count of serializing insts renamed +system.cpu.rename.skidInsts 12717 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 306 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 8775 # Number of vector rename lookups +system.cpu.rob.rob_reads 919877 # The number of ROB reads +system.cpu.rob.rob_writes 1267998 # The number of ROB writes +system.cpu.timesIdled 1366 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 8234 # number of vector regfile reads +system.cpu.vec_regfile_writes 4409 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1264 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 2 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1770 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4395 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 968 # Transaction distribution +system.membus.trans_dist::ReadExReq 284 # Transaction distribution +system.membus.trans_dist::ReadExResp 284 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 968 # Transaction distribution +system.membus.trans_dist::InvalidateReq 12 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2516 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2516 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 80128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 80128 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1264 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1264 # Request fanout histogram +system.membus.reqLayer0.occupancy 1567500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 6638250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2328 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 61 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1647 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 61 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 286 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 286 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2129 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 199 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 12 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 12 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 5905 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1116 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7021 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 241664 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 34944 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 276608 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2626 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001142 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.033787 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2623 99.89% 99.89% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.11% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2626 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 3905500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 733999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3193500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1353 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 9 # number of demand (read+write) hits +system.l2.demand_hits::total 1362 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1353 # number of overall hits +system.l2.overall_hits::.cpu.data 9 # number of overall hits +system.l2.overall_hits::total 1362 # number of overall hits +system.l2.demand_misses::.cpu.inst 776 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 476 # number of demand (read+write) misses +system.l2.demand_misses::total 1252 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 776 # number of overall misses +system.l2.overall_misses::.cpu.data 476 # number of overall misses +system.l2.overall_misses::total 1252 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61228500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 40785000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 102013500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61228500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 40785000 # number of overall miss cycles +system.l2.overall_miss_latency::total 102013500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2129 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 485 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2614 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2129 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 485 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2614 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.364490 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.981443 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.478959 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.364490 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.981443 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.478959 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85682.773109 # average overall miss latency +system.l2.demand_avg_miss_latency::total 81480.431310 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85682.773109 # average overall miss latency +system.l2.overall_avg_miss_latency::total 81480.431310 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 776 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 476 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1252 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 776 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 476 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1252 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53468500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 36025000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 89493500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53468500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 36025000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 89493500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.364490 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.981443 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.478959 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.364490 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.981443 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.478959 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75682.773109 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 71480.431310 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75682.773109 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 71480.431310 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 61 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 61 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 61 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 61 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1645 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1645 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1645 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1645 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 2 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 2 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 284 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 284 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 24621500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 24621500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 286 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 286 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.993007 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.993007 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 86695.422535 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 86695.422535 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 284 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 284 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 21781500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 21781500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.993007 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 76695.422535 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 76695.422535 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1353 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1353 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2129 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2129 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.364490 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.364490 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.364490 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.364490 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 7 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 192 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 192 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 16163500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 16163500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 199 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 199 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.964824 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.964824 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 84184.895833 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 84184.895833 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 192 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 192 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 14243500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 14243500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.964824 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.964824 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 74184.895833 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 74184.895833 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 12 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 12 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19166.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19166.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1005.066467 # Cycle average of tags in use +system.l2.tags.total_refs 4381 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1256 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.488057 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 0.435158 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 675.151065 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 329.480243 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000013 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.020604 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.010055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.030672 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1256 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1118 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.038330 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 36400 # Number of tag accesses +system.l2.tags.data_accesses 36400 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 49664 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 30464 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 80128 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 776 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 476 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1252 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 254948011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 156385636 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 411333646 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 254948011 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 254948011 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 254948011 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 156385636 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 411333646 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 776.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 476.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000595500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2511 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1252 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1252 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 50 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 29 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 185 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 171 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 62 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.22 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 14477250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6260000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 37952250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 11563.30 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 30313.30 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 958 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.52 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1252 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 771 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 309 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 119 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 272.544218 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 180.355670 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 274.253121 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 84 28.57% 28.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 107 36.39% 64.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 33 11.22% 76.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21 7.14% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 2.72% 86.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 4.08% 90.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.04% 92.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.36% 93.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 19 6.46% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 294 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 80128 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 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read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 30464 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 254948010.913729697466 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 156385635.560483664274 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 776 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 476 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21553250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 16399000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27774.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 34451.68 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 76.52 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 956760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 508530 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 3348660 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 15366000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 82538850 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 5341440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 108060240 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 554.722601 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 13202000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 6370500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 175228000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1142400 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 607200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5590620 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) 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Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 141933500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 95491 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 95491 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 95491 # number of overall hits +system.cpu.icache.overall_hits::total 95491 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2382 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2382 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2382 # number of overall misses +system.cpu.icache.overall_misses::total 2382 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 94983999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 94983999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 94983999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 94983999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 97873 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 97873 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 97873 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 97873 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.024338 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.024338 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.024338 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.024338 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 39875.734257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39875.734257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 39875.734257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39875.734257 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1198 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.052632 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1647 # number of writebacks +system.cpu.icache.writebacks::total 1647 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 253 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 253 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 253 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2129 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2129 # number of overall MSHR misses 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overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 36980.271959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36980.271959 # average overall mshr miss latency +system.cpu.icache.replacements 1647 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 95491 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 95491 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2382 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2382 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 94983999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 94983999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 97873 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 97873 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.tags.occ_percent::.cpu.inst 0.851881 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.851881 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 482 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 479 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 197875 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197875 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 148293 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148293 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 148895 # number of overall hits +system.cpu.dcache.overall_hits::total 148895 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1810 # number of demand (read+write) misses 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+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84531.360324 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 84484.893360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84484.893360 # average overall mshr miss latency +system.cpu.dcache.replacements 122 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 85686 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 85686 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 540 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 540 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 39653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 86226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.006263 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006263 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 73432.407407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73432.407407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 196 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 16309000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16309000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 83209.183673 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83209.183673 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 62600 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 62600 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1262 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1262 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 99171953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 99171953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 63862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 63862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.019761 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019761 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78583.164025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78583.164025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 972 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 972 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 290 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 25202994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25202994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.004541 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004541 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 86906.875862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86906.875862 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 602 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 602 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 605 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 605 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.004959 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004959 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.004959 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004959 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 282 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 282 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 271 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 271 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 271 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 271 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 295.653271 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 149945 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 301.700201 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 295.653271 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.577448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.577448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 303019 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 303019 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 194800500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 194800500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/omnetpp/config.ini b/outoforder/omnetpp/config.ini new file mode 100644 index 000000000..5f663d456 --- /dev/null +++ b/outoforder/omnetpp/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 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+eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//data/ref/input/omnetpp.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=omnetpp.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=outoforder/omnetpp/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=outoforder/omnetpp/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=outoforder/omnetpp/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/omnetpp/config.json b/outoforder/omnetpp/config.json new file mode 100644 index 000000000..34ab3a40a --- /dev/null +++ b/outoforder/omnetpp/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 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"system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/omnetpp/fs/proc/cpuinfo b/outoforder/omnetpp/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/omnetpp/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/omnetpp/fs/proc/stat b/outoforder/omnetpp/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/omnetpp/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/omnetpp/fs/sys/devices/system/cpu/online b/outoforder/omnetpp/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/omnetpp/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/omnetpp/fs/sys/devices/system/cpu/possible b/outoforder/omnetpp/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/omnetpp/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/omnetpp/omnetpp.log b/outoforder/omnetpp/omnetpp.log new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/omnetpp/stats.txt b/outoforder/omnetpp/stats.txt new file mode 100644 index 000000000..5b62a6287 --- /dev/null +++ b/outoforder/omnetpp/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 306680000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 111138 # Simulator instruction rate (inst/s) +host_mem_usage 872208 # Number of bytes of host memory used +host_op_rate 124012 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.50 # Real time elapsed on the host +host_tick_rate 68164391 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500002 # Number of instructions simulated +sim_ops 557944 # Number of ops (including micro ops) simulated +sim_seconds 0.000307 # Number of seconds simulated +sim_ticks 306680000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.083798 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 63929 # Number of BTB hits +system.cpu.branchPred.BTBLookups 67949 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4679 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 101374 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1051 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2102 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 1051 # Number of indirect misses. +system.cpu.branchPred.lookups 136512 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 40175 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 30959 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 38299 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 32835 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 301 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 43 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 3117 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1276 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 54 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 326 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1290 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 570 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 335 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1046 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 745 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 217 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 297 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 691 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 342 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 358 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 570 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 372 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 375 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 129 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 61 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 8 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 979 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 109 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 402 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 56035 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 760 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1096 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 307 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1569 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 536 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 604 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 378 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1856 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 876 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 589 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 256 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 776 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 543 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 481 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 270 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 556 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 586 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 546 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 422 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 207 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 81 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 10672 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 171 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 803 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 11633 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 517 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 211950 # number of cc regfile reads +system.cpu.cc_regfile_writes 200574 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3019 # The number of times a branch was mispredicted +system.cpu.commit.branches 96899 # Number of branches committed +system.cpu.commit.bw_lim_events 24399 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 540 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 104262 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 501694 # Number of instructions committed +system.cpu.commit.committedOps 559636 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 492220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.136963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.065231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 305998 62.17% 62.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 63715 12.94% 75.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 50911 10.34% 85.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15251 3.10% 88.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18779 3.82% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3795 0.77% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6541 1.33% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2831 0.58% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24399 4.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 492220 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 9450 # Number of function calls committed. +system.cpu.commit.int_insts 507183 # Number of committed integer instructions. +system.cpu.commit.loads 52957 # Number of loads committed +system.cpu.commit.membars 532 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 12 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 416438 74.41% 74.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 40054 7.16% 81.57% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 38 0.01% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 81.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 47 0.01% 81.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 49 0.01% 81.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 81.60% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 47 0.01% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 81.61% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 52957 9.46% 91.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 49971 8.93% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 559636 # Class of committed instruction +system.cpu.commit.refs 102928 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 699 # Number of committed Vector instructions. +system.cpu.committedInsts 500002 # Number of Instructions Simulated +system.cpu.committedOps 557944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.226717 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.226717 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 292852 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1670 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 62309 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 692901 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 91881 # Number of cycles decode is idle +system.cpu.decode.RunCycles 94155 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3078 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 7283 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 25124 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 136512 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 101490 # Number of cache lines fetched +system.cpu.fetch.Cycles 362370 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2599 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 661606 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9476 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.222564 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 139734 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 76613 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.078657 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 507090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.449575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.607415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 353419 69.70% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20432 4.03% 73.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20348 4.01% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17115 3.38% 81.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12870 2.54% 83.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17614 3.47% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 10813 2.13% 89.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17668 3.48% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36811 7.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 507090 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 106271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3396 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 108885 # Number of branches executed +system.cpu.iew.exec_nop 1853 # number of nop insts executed +system.cpu.iew.exec_rate 1.013579 # Inst execution rate +system.cpu.iew.exec_refs 116350 # number of memory reference insts executed +system.cpu.iew.exec_stores 53785 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 47580 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 66103 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 678 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 57053 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 664285 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 62565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4790 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 621690 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 231 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1325 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3078 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1984 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2167 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2344 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 13146 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 7081 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1827 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1569 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 682348 # num instructions consuming a value +system.cpu.iew.wb_count 613409 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.548818 # average fanout of values written-back +system.cpu.iew.wb_producers 374485 # num instructions producing a value +system.cpu.iew.wb_rate 1.000078 # insts written-back per cycle +system.cpu.iew.wb_sent 615853 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 773538 # number of integer regfile reads +system.cpu.int_regfile_writes 476460 # number of integer regfile writes +system.cpu.ipc 0.815184 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.815184 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 467278 74.59% 74.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 40062 6.39% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 26 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 54 0.01% 81.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 70 0.01% 81.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 69 0.01% 81.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.01% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64047 10.22% 91.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 54801 8.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 626482 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5759 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009193 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3386 58.79% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 58.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.03% 58.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 6 0.10% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 58.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 683 11.86% 70.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1682 29.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 631327 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1764297 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 612592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 765733 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 661841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 626482 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 591 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 104483 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 297 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 74507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 507090 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.235445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.798850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269368 53.12% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 74053 14.60% 67.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 78200 15.42% 83.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25111 4.95% 88.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22583 4.45% 92.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12325 2.43% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 13332 2.63% 97.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8197 1.62% 99.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3921 0.77% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 507090 # Number of insts issued each cycle +system.cpu.iq.rate 1.021392 # Inst issue rate +system.cpu.iq.vec_alu_accesses 897 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1811 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 817 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1221 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2201 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2145 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 66103 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 57053 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 364783 # number of misc regfile reads +system.cpu.misc_regfile_writes 2121 # number of misc regfile writes +system.cpu.numCycles 613361 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 105930 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 614891 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 78630 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 102393 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2867 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 927 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1089378 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 681139 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 744876 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 106752 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7326 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3078 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 95123 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 129971 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 840374 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 93814 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2156 # count of serializing insts renamed +system.cpu.rename.skidInsts 145405 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 593 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1144 # Number of vector rename lookups +system.cpu.rob.rob_reads 1131381 # The number of ROB reads +system.cpu.rob.rob_writes 1342691 # The number of ROB writes +system.cpu.timesIdled 1238 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 944 # number of vector regfile reads +system.cpu.vec_regfile_writes 295 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 3580 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 6835 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2548 # Transaction distribution +system.membus.trans_dist::ReadExReq 882 # Transaction distribution +system.membus.trans_dist::ReadExResp 882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2549 # Transaction distribution +system.membus.trans_dist::InvalidateReq 149 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 7010 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7010 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 219520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 219520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3580 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3580 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3580 # Request fanout histogram +system.membus.reqLayer0.occupancy 4404000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 18150500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2879 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1162 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1193 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 551 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 898 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 898 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1703 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1177 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 151 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 151 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4599 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 6164 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 10763 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 185344 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 207104 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 392448 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3929 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000255 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.015954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3928 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3929 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 5772500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 3186999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2555498 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 204 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 143 # number of demand (read+write) hits +system.l2.demand_hits::total 347 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 204 # number of overall hits +system.l2.overall_hits::.cpu.data 143 # number of overall hits +system.l2.overall_hits::total 347 # number of overall hits +system.l2.demand_misses::.cpu.inst 1499 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1932 # number of demand (read+write) misses +system.l2.demand_misses::total 3431 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1499 # number of overall misses +system.l2.overall_misses::.cpu.data 1932 # number of overall misses +system.l2.overall_misses::total 3431 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 117227000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 150614000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 267841000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 117227000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 150614000 # number of overall miss cycles +system.l2.overall_miss_latency::total 267841000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1703 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2075 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3778 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1703 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2075 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3778 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.880211 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.931084 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.908152 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.880211 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.931084 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.908152 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78203.468979 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77957.556936 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78064.995628 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78203.468979 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77957.556936 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78064.995628 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1499 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1932 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3431 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1499 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1932 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3431 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 102237000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 131304000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 233541000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 102237000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 131304000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 233541000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.880211 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.931084 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.908152 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.880211 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.931084 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.908152 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68203.468979 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67962.732919 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68067.910230 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68203.468979 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67962.732919 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68067.910230 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1162 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1162 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1162 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1162 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1193 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1193 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1193 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1193 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 16 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 16 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 882 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 882 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 70088500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 70088500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 898 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 898 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.982183 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.982183 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79465.419501 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79465.419501 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 882 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 882 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 61268500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 61268500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.982183 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.982183 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69465.419501 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69465.419501 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 204 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 204 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1499 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1499 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 117227000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 117227000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1703 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1703 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.880211 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.880211 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78203.468979 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78203.468979 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1499 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1499 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 102237000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 102237000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.880211 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.880211 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68203.468979 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68203.468979 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 127 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 127 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1050 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1050 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 80525500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 80525500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1177 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1177 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.892099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.892099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 76690.952381 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 76690.952381 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1050 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1050 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 70035500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 70035500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.892099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.892099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 66700.476190 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 66700.476190 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 149 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 149 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19114.093960 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19114.093960 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1894.653157 # Cycle average of tags in use +system.l2.tags.total_refs 6684 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 3580 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.867039 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 57.908110 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1010.843092 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 825.901955 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001767 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.030848 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.025205 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.057820 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 3578 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1152 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2305 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.109192 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 58252 # Number of tag accesses +system.l2.tags.data_accesses 58252 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 95936 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 123584 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 219520 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 95936 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 95936 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1499 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1931 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 3430 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 312821182 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 402973784 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 715794965 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 312821182 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 312821182 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 312821182 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 402973784 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 715794965 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1499.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1932.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000592250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 6872 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3431 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 3431 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 126 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 239 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 202 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 287 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 232 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 214 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 265 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 231 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 86 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 143 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 214 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 162 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.31 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 28181250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 17155000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 92512500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8213.71 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26963.71 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2836 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 82.66 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3431 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2436 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 687 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 213 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.bytesPerActivate::samples 594 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 369.346801 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 233.030404 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 340.434745 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 145 24.41% 24.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 26.43% 50.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 76 12.79% 63.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 44 7.41% 71.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 38 6.40% 77.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 20 3.37% 80.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 14 2.36% 83.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 10 1.68% 84.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 90 15.15% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 594 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 219584 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 219584 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 716.00 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 716.00 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.59 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.59 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 306651500 # Total gap between requests +system.mem_ctrls.avgGap 89376.71 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 95936 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 123648 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 312821181.687752723694 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 403182470.327377080917 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1499 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1932 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 40582000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 51930500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27072.72 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26879.14 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1927800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1024650 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10145940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 23970960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 84086970 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46955040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 168111360 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 548.165384 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 121325750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 10140000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 175214250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 2320500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1229580 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 14351400 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 23970960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 111459510 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 23904480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 177236430 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 577.919753 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 60980500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 10140000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 235559500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 99073 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 99073 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 99073 # number of overall hits +system.cpu.icache.overall_hits::total 99073 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2415 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2415 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2415 # number of overall misses +system.cpu.icache.overall_misses::total 2415 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 159037498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 159037498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 159037498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 159037498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 101488 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 101488 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 101488 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 101488 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.023796 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.023796 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.023796 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.023796 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65854.036439 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65854.036439 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65854.036439 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65854.036439 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1193 # number of writebacks +system.cpu.icache.writebacks::total 1193 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 712 # number of demand (read+write) MSHR hits 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# number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.016780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.016780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016780 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 71644.156195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71644.156195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 71644.156195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71644.156195 # average overall mshr miss latency +system.cpu.icache.replacements 1193 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 99073 # number of ReadReq hits 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+system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 457.647558 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 100776 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1703 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.175573 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 457.647558 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.893843 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893843 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 204679 # Number of tag accesses +system.cpu.icache.tags.data_accesses 204679 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 99534 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 99534 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 99544 # number of overall hits +system.cpu.dcache.overall_hits::total 99544 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 6815 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6815 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 6817 # number of overall misses +system.cpu.dcache.overall_misses::total 6817 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 453569325 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 453569325 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 453569325 # number of overall miss cycles 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159744891 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.020875 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.020875 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.020891 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.020891 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71874.050000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71874.050000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 71892.390189 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71892.390189 # average overall mshr miss latency +system.cpu.dcache.replacements 1713 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 53156 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 53156 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3739 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3739 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 242608000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 242608000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 56895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.065718 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065718 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 64885.798342 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64885.798342 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 2568 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2568 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1171 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1171 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 83246500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 83246500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.020582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 71090.093937 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71090.093937 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 46367 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 46367 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 2936 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2936 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 206472921 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 206472921 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 49303 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 49303 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.059550 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059550 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 70324.564373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70324.564373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 909 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 909 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 71965487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71965487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 79169.952695 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79169.952695 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 10 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 12 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.166667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 151 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.927152 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32060.028571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 140 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4348404 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 435.454454 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 102856 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2225 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 46.227416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 435.454454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.850497 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.850497 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 217131 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 217131 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 306680000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 306680000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/povray/SPEC-benchmark-ref.stdout b/outoforder/povray/SPEC-benchmark-ref.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/povray/config.ini b/outoforder/povray/config.ini new file mode 100644 index 000000000..460c2033a --- /dev/null +++ b/outoforder/povray/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 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+prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/453.povray//data/ref/input/SPEC-benchmark-ref.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=SPEC-benchmark-ref.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 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system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/povray/config.json b/outoforder/povray/config.json new file mode 100644 index 000000000..24756252e --- /dev/null +++ b/outoforder/povray/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + 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1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/povray/fs/proc/cpuinfo b/outoforder/povray/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/povray/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/povray/fs/proc/stat b/outoforder/povray/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/povray/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/povray/fs/sys/devices/system/cpu/online b/outoforder/povray/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/povray/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/povray/fs/sys/devices/system/cpu/possible b/outoforder/povray/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/povray/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/povray/stats.txt b/outoforder/povray/stats.txt new file mode 100644 index 000000000..d875bd5d5 --- /dev/null +++ b/outoforder/povray/stats.txt @@ -0,0 +1,1362 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 252288000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 115584 # Simulator instruction rate (inst/s) +host_mem_usage 856524 # Number of bytes of host memory used +host_op_rate 133472 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.33 # Real time elapsed on the host +host_tick_rate 58317209 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500004 # Number of instructions simulated +sim_ops 577416 # Number of ops (including micro ops) simulated +sim_seconds 0.000252 # Number of seconds simulated +sim_ticks 252288000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.120838 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 63012 # Number of BTB hits +system.cpu.branchPred.BTBLookups 64880 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 3363 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 100084 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 187 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 692 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 505 # Number of indirect misses. +system.cpu.branchPred.lookups 151612 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 56938 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 24410 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 52968 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 28380 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 323 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 84 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6025 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1358 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1546 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 797 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1473 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 279 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 651 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 425 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 874 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 329 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 467 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 441 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 462 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 724 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 900 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 310 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 492 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 835 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 612 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 218 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 915 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 757 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 87 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 236 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 58948 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 972 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1961 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 838 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2508 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1103 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2043 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 654 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1442 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1026 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 658 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 410 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 930 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 480 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 451 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 449 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 365 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 617 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 866 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 779 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 917 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 404 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 691 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 991 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 18936 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 158 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 654 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 20867 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 158 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 179490 # number of cc regfile reads +system.cpu.cc_regfile_writes 176163 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2587 # The number of times a branch was mispredicted +system.cpu.commit.branches 125971 # Number of branches committed +system.cpu.commit.bw_lim_events 37230 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 48 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 57195 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500810 # Number of instructions committed +system.cpu.commit.committedOps 578222 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 413504 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.398347 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.419959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 234270 56.65% 56.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75984 18.38% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32220 7.79% 82.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16867 4.08% 86.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5203 1.26% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4526 1.09% 89.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4513 1.09% 90.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2691 0.65% 91.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 37230 9.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 413504 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 18534 # Number of function calls committed. +system.cpu.commit.int_insts 519669 # Number of committed integer instructions. +system.cpu.commit.loads 113713 # Number of loads committed +system.cpu.commit.membars 32 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 18 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 400382 69.24% 69.25% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 43 0.01% 69.25% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 8 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 7 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 9 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 70 0.01% 69.27% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 71 0.01% 69.28% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 72 0.01% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 50 0.01% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 113713 19.67% 88.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 63777 11.03% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 578222 # Class of committed instruction +system.cpu.commit.refs 177490 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 764 # Number of committed Vector instructions. +system.cpu.committedInsts 500004 # Number of Instructions Simulated +system.cpu.committedOps 577416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.009146 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.009146 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 229385 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 795 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 61243 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 656978 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 84243 # Number of cycles decode is idle +system.cpu.decode.RunCycles 86108 # Number of cycles decode is running +system.cpu.decode.SquashCycles 2644 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2584 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 19747 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 151612 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 100858 # Number of cache lines fetched +system.cpu.fetch.Cycles 276034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1675 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 601294 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6840 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.300473 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 142603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 84066 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.191679 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 422127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.634176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.674871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 269113 63.75% 63.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 19161 4.54% 68.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28269 6.70% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 26181 6.20% 81.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8375 1.98% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13485 3.19% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5530 1.31% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14621 3.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37392 8.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 422127 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 82450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 132291 # Number of branches executed +system.cpu.iew.exec_nop 889 # number of nop insts executed +system.cpu.iew.exec_rate 1.216354 # Inst execution rate +system.cpu.iew.exec_refs 188388 # number of memory reference insts executed +system.cpu.iew.exec_stores 66763 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 6853 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124716 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 68949 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 635820 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 121625 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4160 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 613744 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 690 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2644 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 726 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2203 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1786 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11002 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5172 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 943 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 559912 # num instructions consuming a value +system.cpu.iew.wb_count 608626 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.587423 # average fanout of values written-back +system.cpu.iew.wb_producers 328905 # num instructions producing a value +system.cpu.iew.wb_rate 1.206210 # insts written-back per cycle +system.cpu.iew.wb_sent 610126 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 657828 # number of integer regfile reads +system.cpu.int_regfile_writes 445802 # number of integer regfile writes +system.cpu.ipc 0.990937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.990937 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 28 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 427303 69.15% 69.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43 0.01% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 8 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 15 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 85 0.01% 69.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 94 0.02% 69.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 107 0.02% 69.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 60 0.01% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 69.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 122792 19.87% 89.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 67353 10.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 617904 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 8564 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013860 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1886 22.02% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 4 0.05% 22.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 14 0.16% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 22.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3197 37.33% 59.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3463 40.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 625439 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1664873 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 607734 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 690982 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 634853 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 617904 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 57512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 358 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 37279 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 422127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.463787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.009594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 210117 49.78% 49.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 66762 15.82% 65.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 41285 9.78% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36909 8.74% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28617 6.78% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10583 2.51% 93.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12793 3.03% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6784 1.61% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8277 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 422127 # Number of insts issued each cycle +system.cpu.iq.rate 1.224598 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1001 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1984 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 892 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1488 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 409 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 506 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124716 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 68949 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 521324 # number of misc regfile reads +system.cpu.misc_regfile_writes 138 # number of misc regfile writes +system.cpu.numCycles 504577 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 9889 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 588900 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3317 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 93057 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 934960 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 646018 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 659379 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 96946 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 2482 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 2644 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 21904 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 70468 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 692929 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 197687 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 11495 # count of serializing insts renamed +system.cpu.rename.skidInsts 89412 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1640 # Number of vector rename lookups +system.cpu.rob.rob_reads 1011249 # The number of ROB reads +system.cpu.rob.rob_writes 1279486 # The number of ROB writes +system.cpu.timesIdled 1374 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1084 # number of vector regfile reads +system.cpu.vec_regfile_writes 450 # number of vector regfile writes +system.cpu.workload.numSyscalls 15 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1562 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1915 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4763 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1200 # Transaction distribution +system.membus.trans_dist::ReadExReq 352 # Transaction distribution +system.membus.trans_dist::ReadExResp 352 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1200 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 99328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 99328 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1562 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1562 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1562 # Request fanout histogram +system.membus.reqLayer0.occupancy 1941500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 8244000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2484 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 110 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1685 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 120 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 354 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 354 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2181 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 303 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 10 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 10 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 6047 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7611 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 247424 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 49088 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 296512 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2848 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000351 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.018738 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2847 99.96% 99.96% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.04% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2848 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 4176500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 990500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3271500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1190 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 96 # number of demand (read+write) hits +system.l2.demand_hits::total 1286 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1190 # number of overall hits +system.l2.overall_hits::.cpu.data 96 # number of overall hits +system.l2.overall_hits::total 1286 # number of overall hits +system.l2.demand_misses::.cpu.inst 991 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 561 # number of demand (read+write) misses +system.l2.demand_misses::total 1552 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 991 # number of overall misses +system.l2.overall_misses::.cpu.data 561 # number of overall misses +system.l2.overall_misses::total 1552 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 78134500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 45156000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 123290500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 78134500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 45156000 # number of overall miss cycles +system.l2.overall_miss_latency::total 123290500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2181 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 657 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2838 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2181 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 657 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2838 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.454379 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.853881 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.546864 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.454379 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.853881 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.546864 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78844.096872 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80491.978610 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79439.755155 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78844.096872 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80491.978610 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79439.755155 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 991 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 561 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1552 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 991 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 561 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1552 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 68224500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 39546000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 107770500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 68224500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 39546000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 107770500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.454379 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.853881 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.546864 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.454379 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.853881 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.546864 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68844.096872 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70491.978610 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69439.755155 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68844.096872 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70491.978610 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69439.755155 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 110 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 110 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 110 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 110 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1685 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1685 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1685 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1685 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 2 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 2 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 352 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 352 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 27716000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 27716000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 354 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 354 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.994350 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.994350 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78738.636364 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78738.636364 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 352 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 352 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 24196000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 24196000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.994350 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68738.636364 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68738.636364 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1190 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1190 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 991 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 991 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 78134500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 78134500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2181 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2181 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.454379 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.454379 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78844.096872 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78844.096872 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 991 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 991 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 68224500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 68224500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.454379 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.454379 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68844.096872 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68844.096872 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 94 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 94 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 209 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 209 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 17440000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 17440000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 303 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 303 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.689769 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.689769 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83444.976077 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83444.976077 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 209 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 209 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 15350000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 15350000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.689769 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.689769 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73444.976077 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73444.976077 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 10 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18800 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18800 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1267.110551 # Cycle average of tags in use +system.l2.tags.total_refs 4752 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1559 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.048108 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 4.635189 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 820.363557 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 442.111805 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000141 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.025036 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.013492 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.038669 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1559 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1500 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.047577 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 39655 # Number of tag accesses +system.l2.tags.data_accesses 39655 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 63424 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 35904 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99328 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 63424 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 63424 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 991 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 561 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1552 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 251395231 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 142313546 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 393708777 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 251395231 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 251395231 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 251395231 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 142313546 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 393708777 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 991.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 561.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000573500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3115 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1552 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1552 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 115 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 7 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 113 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 141 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 152 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 133 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.22 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 14798500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 7760000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 43898500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9535.12 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28285.12 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1179 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 75.97 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1552 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 966 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 397 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 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3.23% 87.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 1.08% 88.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.42% 91.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 2.15% 93.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 24 6.45% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 372 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 99328 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 99328 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 393.71 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 393.71 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.08 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.08 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 250990000 # Total gap between requests +system.mem_ctrls.avgGap 161720.36 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 63424 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 35904 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 251395230.847285658121 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 142313546.423135489225 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 991 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 561 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 27447000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 16451500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27696.27 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 29325.31 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 75.97 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1470840 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 777975 # Energy for precharge commands per rank (pJ) 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in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8320000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 162339000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1192380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 633765 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 4848060 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 19668480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 74861520 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 33837600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 135041805 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 535.268443 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 87352750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 8320000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 156615250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 98368 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98368 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 98368 # number of overall hits +system.cpu.icache.overall_hits::total 98368 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2489 # number of overall misses +system.cpu.icache.overall_misses::total 2489 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 112047499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112047499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 112047499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112047499 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 100857 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 100857 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 100857 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 100857 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.024679 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.024679 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.024679 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.024679 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 45017.074729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45017.074729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 45017.074729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45017.074729 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.947368 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1685 # number of writebacks +system.cpu.icache.writebacks::total 1685 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 308 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 308 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 308 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2181 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2181 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2181 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2181 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 93987499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 93987499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 93987499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 93987499 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.021625 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.021625 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.021625 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.021625 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 43093.763870 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43093.763870 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 43093.763870 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43093.763870 # average overall mshr miss latency +system.cpu.icache.replacements 1685 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 98368 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98368 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2489 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 112047499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112047499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 100857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 100857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.024679 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.024679 # miss rate for ReadReq accesses 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43093.763870 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 450.179569 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 100549 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2181 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 46.102247 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 450.179569 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.879257 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.879257 # Average percentage of cache occupancy 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(read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 158318455 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 158318455 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 158318455 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 181078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 181078 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 181245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 181245 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.013254 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013254 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.013258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013258 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 65966.022917 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65966.022917 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 65883.668331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65883.668331 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3040 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 404 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 77 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.480519 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.800000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1737 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1737 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1737 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1737 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 666 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 666 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 46866494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46866494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 47356994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47356994 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.003661 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003661 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.003675 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003675 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 70688.527903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70688.527903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 71106.597598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71106.597598 # average overall mshr miss latency +system.cpu.dcache.replacements 230 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 116667 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 116667 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 532 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 532 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 33350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 117199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 117199 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.004539 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004539 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 62688.909774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62688.909774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 233 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 18287500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18287500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002551 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 61162.207358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61162.207358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 62011 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 62011 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1861 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1861 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 124745458 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124745458 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 63872 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 63872 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.029136 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029136 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67031.412144 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67031.412144 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 357 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 357 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 28363497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 28363497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.005589 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005589 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 79449.571429 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79449.571429 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 164 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 164 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.017964 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.017964 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 490500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 490500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.017964 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.017964 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 163500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 163500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 39 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 39 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 41 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 41 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.048780 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048780 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.024390 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.024390 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 32 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 32 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 32 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 32 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 366.100594 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 179580 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 667 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 269.235382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 366.100594 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.715040 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.715040 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 437 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 376 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.853516 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 363303 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 363303 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 252288000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 252288000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/sjeng/config.ini b/outoforder/sjeng/config.ini new file mode 100644 index 000000000..06195bd94 --- /dev/null +++ b/outoforder/sjeng/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true 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+clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//data/ref/input/ref.txt +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state 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"True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/sjeng/fs/proc/cpuinfo b/outoforder/sjeng/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/sjeng/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/sjeng/fs/proc/stat b/outoforder/sjeng/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/sjeng/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/sjeng/fs/sys/devices/system/cpu/online b/outoforder/sjeng/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/sjeng/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/sjeng/fs/sys/devices/system/cpu/possible b/outoforder/sjeng/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/sjeng/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/sjeng/ref.out b/outoforder/sjeng/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/sjeng/stats.txt b/outoforder/sjeng/stats.txt new file mode 100644 index 000000000..5c1ca9e22 --- /dev/null +++ b/outoforder/sjeng/stats.txt @@ -0,0 +1,1352 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 145319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 113471 # Simulator instruction rate (inst/s) +host_mem_usage 850528 # Number of bytes of host memory used +host_op_rate 113711 # Simulator op (including micro ops) rate (op/s) +host_seconds 4.41 # Real time elapsed on the host +host_tick_rate 32977594 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500001 # Number of instructions simulated +sim_ops 501077 # Number of ops (including micro ops) simulated +sim_seconds 0.000145 # Number of seconds simulated +sim_ticks 145319500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.496121 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 24757 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25135 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 26003 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 110 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 110 # Number of indirect misses. +system.cpu.branchPred.lookups 27247 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 816 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 23921 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 807 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 23930 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 13 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 4 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 624 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1208 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 408 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 938 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 209 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2076 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3126 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3813 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 9614 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 153 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 7 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 64 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 67 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 2011 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 220 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 506 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 116 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1208 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 410 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1147 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2076 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3126 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 3813 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 9614 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 153 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 32 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 34 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 22360 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 5 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 14 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 34 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 287028 # number of cc regfile reads +system.cpu.cc_regfile_writes 287061 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 315 # The number of times a branch was mispredicted +system.cpu.commit.branches 25457 # Number of branches committed +system.cpu.commit.bw_lim_events 41912 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 11 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4603 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 500015 # Number of instructions committed +system.cpu.commit.committedOps 501091 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 260273 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.925252 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.021016 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156465 60.12% 60.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28840 11.08% 71.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7765 2.98% 74.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2917 1.12% 75.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 974 0.37% 75.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20345 7.82% 83.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 332 0.13% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 723 0.28% 83.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 41912 16.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 260273 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 111 # Number of function calls committed. +system.cpu.commit.int_insts 476120 # Number of committed integer instructions. +system.cpu.commit.loads 141821 # Number of loads committed +system.cpu.commit.membars 4 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 252025 50.30% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 20 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 50.30% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 19 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 17 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 50.31% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 141821 28.30% 78.62% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 107155 21.38% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 501091 # Class of committed instruction +system.cpu.commit.refs 248976 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 151 # Number of committed Vector instructions. +system.cpu.committedInsts 500001 # Number of Instructions Simulated +system.cpu.committedOps 501077 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.581279 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.581279 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 124185 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 172 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 24839 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 507536 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 47923 # Number of cycles decode is idle +system.cpu.decode.RunCycles 85514 # Number of cycles decode is running +system.cpu.decode.SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3088 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 27247 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 49528 # Number of cache lines fetched +system.cpu.fetch.Cycles 203009 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 508446 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 996 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.093748 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 57458 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 24982 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.749401 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 261041 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.954873 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.019970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 166649 63.84% 63.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 488 0.19% 64.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23542 9.02% 73.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 658 0.25% 73.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20216 7.74% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3849 1.47% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2069 0.79% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 327 0.13% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 43243 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 261041 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 29599 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 365 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 25856 # Number of branches executed +system.cpu.iew.exec_nop 32 # number of nop insts executed +system.cpu.iew.exec_rate 1.738498 # Inst execution rate +system.cpu.iew.exec_refs 251098 # number of memory reference insts executed +system.cpu.iew.exec_stores 107384 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1900 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 142551 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 118 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 107696 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 505740 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 143714 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 445 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 505277 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 546 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 587 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 399 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 716 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 792770 # num instructions consuming a value +system.cpu.iew.wb_count 503440 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.454211 # average fanout of values written-back +system.cpu.iew.wb_producers 360085 # num instructions producing a value +system.cpu.iew.wb_rate 1.732177 # insts written-back per cycle +system.cpu.iew.wb_sent 503680 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 986019 # number of integer regfile reads +system.cpu.int_regfile_writes 370542 # number of integer regfile writes +system.cpu.ipc 1.720345 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.720345 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 254320 50.29% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.01% 50.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 50.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.01% 50.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 28 0.01% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 50.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 143821 28.44% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 107468 21.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 505728 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 21960 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.043423 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 532 2.42% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 2.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20729 94.39% 96.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 694 3.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 527463 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1294067 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 503249 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 509911 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 505693 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 505728 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4582 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3423 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 261041 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.937351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.185193 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 117289 44.93% 44.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 27385 10.49% 55.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23656 9.06% 64.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10471 4.01% 68.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 36413 13.95% 82.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24572 9.41% 91.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18395 7.05% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2144 0.82% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 716 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261041 # Number of insts issued each cycle +system.cpu.iq.rate 1.740050 # Inst issue rate +system.cpu.iq.vec_alu_accesses 218 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 450 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 191 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 387 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 142551 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 107696 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 349748 # number of misc regfile reads +system.cpu.misc_regfile_writes 17 # number of misc regfile writes +system.cpu.numCycles 290640 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 2790 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 655066 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 95 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 49714 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 180 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1276228 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 506805 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 660961 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 86776 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 117663 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 331 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 118639 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 5830 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 986753 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2791 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 53 # count of serializing insts renamed +system.cpu.rename.skidInsts 14365 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 18 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 373 # Number of vector rename lookups +system.cpu.rob.rob_reads 723925 # The number of ROB reads +system.cpu.rob.rob_writes 1012210 # The number of ROB writes +system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 252 # number of vector regfile reads +system.cpu.vec_regfile_writes 120 # number of vector regfile writes +system.cpu.workload.numSyscalls 6 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2901 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2065 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4967 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 478 # Transaction distribution +system.membus.trans_dist::ReadExReq 2412 # Transaction distribution +system.membus.trans_dist::ReadExResp 2412 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 478 # Transaction distribution +system.membus.trans_dist::InvalidateReq 11 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5791 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5791 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 184960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 184960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2901 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2901 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2901 # Request fanout histogram +system.membus.reqLayer0.occupancy 3141000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 15388250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 479 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1951 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 45 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 69 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2412 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2412 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 370 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 109 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 11 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 11 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 785 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 7084 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7869 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 26560 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 286208 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 312768 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2902 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000345 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.018563 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2901 99.97% 99.97% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.03% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2902 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 4479500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 3787000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 555000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1 # number of demand (read+write) hits +system.l2.demand_hits::total 1 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1 # number of overall hits +system.l2.overall_hits::total 1 # number of overall hits +system.l2.demand_misses::.cpu.inst 369 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2521 # number of demand (read+write) misses +system.l2.demand_misses::total 2890 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 369 # number of overall misses +system.l2.overall_misses::.cpu.data 2521 # number of overall misses +system.l2.overall_misses::total 2890 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 29101000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 202364500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 231465500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 29101000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 202364500 # number of overall miss cycles +system.l2.overall_miss_latency::total 231465500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 370 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2521 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2891 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 370 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2521 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2891 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.997297 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 1 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.999654 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.997297 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 1 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.999654 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78864.498645 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80271.519238 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80091.868512 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78864.498645 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80271.519238 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80091.868512 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 369 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2521 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2890 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 369 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2521 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2890 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 25411000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 177154500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 202565500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 25411000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 177154500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 202565500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.997297 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 1 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.999654 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.997297 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 1 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.999654 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68864.498645 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70271.519238 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70091.868512 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68864.498645 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70271.519238 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70091.868512 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1951 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1951 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1951 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1951 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 45 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 45 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 45 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 45 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 2412 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2412 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 192917500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 192917500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2412 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2412 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79982.379768 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79982.379768 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2412 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2412 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 168797500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 168797500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69982.379768 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69982.379768 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 369 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 369 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 29101000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 29101000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 370 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 370 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.997297 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.997297 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78864.498645 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78864.498645 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 369 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 369 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 25411000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 25411000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.997297 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.997297 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68864.498645 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68864.498645 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_misses::.cpu.data 109 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 109 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 9447000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 9447000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 109 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 109 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86669.724771 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86669.724771 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 109 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 109 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 8357000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 8357000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76669.724771 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76669.724771 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 11 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 11 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 11 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 11 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 11 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 11 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 208000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 208000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18909.090909 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18909.090909 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1694.175649 # Cycle average of tags in use +system.l2.tags.total_refs 4955 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2901 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.708032 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 8.694208 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 338.781764 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1346.699677 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000265 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.010339 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.041098 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.051702 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2901 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1327 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1424 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.088531 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 42629 # Number of tag accesses +system.l2.tags.data_accesses 42629 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 23616 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 161344 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 184960 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 23616 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 23616 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 369 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2521 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2890 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 162510881 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1110270817 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1272781698 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 162510881 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 162510881 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 162510881 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1110270817 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1272781698 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 369.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2521.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000594000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5761 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2890 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2890 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 271 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 168 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 188 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 206 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 206 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 152 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 153 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 215 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 231 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 28877500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 14450000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 83065000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9992.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28742.21 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2559 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.55 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2890 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1211 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1166 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 458 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 40 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 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activation +system.mem_ctrls.bytesPerActivate::256-383 25 7.67% 37.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 62 19.02% 56.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 2.45% 58.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 2.45% 61.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 13 3.99% 65.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 9 2.76% 68.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 104 31.90% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 326 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 184960 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 184960 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1272.78 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1272.78 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 9.94 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 9.94 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 145123500 # Total gap between requests +system.mem_ctrls.avgGap 50215.74 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 23616 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 161344 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 162510881.196260660887 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1110270817.061715841293 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 369 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2521 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 10230500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 72834500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27724.93 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28891.11 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 88.55 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1156680 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 603405 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10845660 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 11063520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 63837150 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 2045280 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 89551695 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 616.240043 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 4639250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 4680000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 136000250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1206660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 633765 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 9788940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 11063520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 64905330 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 1145760 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 88743975 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 610.681808 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 2362750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 4680000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 138276750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 49041 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49041 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 49041 # number of overall hits +system.cpu.icache.overall_hits::total 49041 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 487 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 487 # number of overall misses +system.cpu.icache.overall_misses::total 487 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 37139496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37139496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 37139496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37139496 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 49528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 49528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49528 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.009833 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009833 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.009833 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009833 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76261.798768 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76261.798768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76261.798768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76261.798768 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 750 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 45 # number of writebacks +system.cpu.icache.writebacks::total 45 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 117 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 117 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 117 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 370 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 370 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 370 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 29672996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29672996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 29672996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29672996 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.007471 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007471 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.007471 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007471 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 80197.286486 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80197.286486 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 80197.286486 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80197.286486 # average overall mshr miss latency +system.cpu.icache.replacements 45 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 49041 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49041 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 487 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 487 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 37139496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37139496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 49528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49528 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007471 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 80197.286486 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80197.286486 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 300.818700 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49411 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 370 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 133.543243 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 300.818700 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.587537 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.587537 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 325 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.634766 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 99426 # Number of tag accesses +system.cpu.icache.tags.data_accesses 99426 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 230082 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 230082 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 230086 # number of overall hits +system.cpu.dcache.overall_hits::total 230086 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 19350 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 19350 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 19352 # number of overall misses +system.cpu.dcache.overall_misses::total 19352 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 1214694124 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1214694124 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 1214694124 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1214694124 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 249432 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 249432 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 249438 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 249438 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.077576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.077576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.077582 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.077582 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 62774.890129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62774.890129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62768.402439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62768.402439 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23836 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.432558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1951 # number of writebacks +system.cpu.dcache.writebacks::total 1951 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 16821 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16821 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 16821 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16821 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 2529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 2531 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2531 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 206293991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206293991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 206470491 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 206470491 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.010139 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010139 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.010147 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.010147 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 81571.368525 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81571.368525 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 81576.645990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81576.645990 # average overall mshr miss latency +system.cpu.dcache.replacements 2020 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 141961 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 141961 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 321 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 22909000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22909000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 142282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 142282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.002256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 71367.601246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71367.601246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 106 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 9099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000745 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000745 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 85844.339623 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85844.339623 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 88121 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 88121 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 19022 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19022 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 1191562626 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1191562626 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 107143 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 107143 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.177538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.177538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 62641.290401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62641.290401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 16606 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16606 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 2416 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2416 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 196978993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 196978993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.022549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.022549 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 81531.040149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81531.040149 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 435.219066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 232625 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2532 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 91.874013 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 435.219066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.850037 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.850037 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 501424 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 501424 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 145319500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 145319500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/outoforder/xalancbmk/config.ini b/outoforder/xalancbmk/config.ini new file mode 100644 index 000000000..0a994d6c5 --- /dev/null +++ b/outoforder/xalancbmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState 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+clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross -v /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/t5.xml /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/xalanc.xsl +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 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+eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/outoforder/xalancbmk/config.json b/outoforder/xalancbmk/config.json new file mode 100644 index 000000000..4cac62ad9 --- /dev/null +++ b/outoforder/xalancbmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 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"True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/outoforder/xalancbmk/fs/proc/cpuinfo b/outoforder/xalancbmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/outoforder/xalancbmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/outoforder/xalancbmk/fs/proc/stat b/outoforder/xalancbmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/outoforder/xalancbmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/outoforder/xalancbmk/fs/sys/devices/system/cpu/online b/outoforder/xalancbmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/xalancbmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/xalancbmk/fs/sys/devices/system/cpu/possible b/outoforder/xalancbmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/outoforder/xalancbmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/outoforder/xalancbmk/ref.out b/outoforder/xalancbmk/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/outoforder/xalancbmk/stats.txt b/outoforder/xalancbmk/stats.txt new file mode 100644 index 000000000..bee147d4d --- /dev/null +++ b/outoforder/xalancbmk/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 263409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 98014 # Simulator instruction rate (inst/s) +host_mem_usage 882600 # Number of bytes of host memory used +host_op_rate 119688 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.10 # Real time elapsed on the host +host_tick_rate 51633000 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500002 # Number of instructions simulated +sim_ops 610592 # Number of ops (including micro ops) simulated +sim_seconds 0.000263 # Number of seconds simulated +sim_ticks 263409000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 89.757962 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 56368 # Number of BTB hits +system.cpu.branchPred.BTBLookups 62800 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 54 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6581 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 90401 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1568 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3642 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 2074 # Number of indirect misses. +system.cpu.branchPred.lookups 133808 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 47597 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 25540 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 44476 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 28661 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 592 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 123 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 4397 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1787 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 819 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 601 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1595 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 644 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1417 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1690 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 426 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 982 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 841 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 872 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 911 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 814 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 252 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 201 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 125 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 21 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1411 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 225 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 534 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 51383 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1269 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1571 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1313 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1528 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1185 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1213 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1608 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1732 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 505 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1018 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1075 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 862 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1189 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1085 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 514 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 694 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 733 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 298 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 85 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 28 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 10 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 15989 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 209 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 919 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 14803 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 480 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 151842 # number of cc regfile reads +system.cpu.cc_regfile_writes 149626 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4026 # The number of times a branch was mispredicted +system.cpu.commit.branches 104469 # Number of branches committed +system.cpu.commit.bw_lim_events 31435 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 525 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 79924 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 501201 # Number of instructions committed +system.cpu.commit.committedOps 611791 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 392447 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.558914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.486059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 224815 57.29% 57.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 49433 12.60% 69.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 27130 6.91% 76.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 22746 5.80% 82.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 15552 3.96% 86.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5887 1.50% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11406 2.91% 90.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4043 1.03% 91.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 31435 8.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 392447 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 11731 # Number of function calls committed. +system.cpu.commit.int_insts 564079 # Number of committed integer instructions. +system.cpu.commit.loads 91205 # Number of loads committed +system.cpu.commit.membars 524 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 3 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 422523 69.06% 69.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 392 0.06% 69.13% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 46 0.01% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 2 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 15 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 10 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 12 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 21 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 91205 14.91% 84.05% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 97561 15.95% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 611791 # Class of committed instruction +system.cpu.commit.refs 188766 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 466 # Number of committed Vector instructions. +system.cpu.committedInsts 500002 # Number of Instructions Simulated +system.cpu.committedOps 610592 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.053636 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.053636 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 138155 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 2612 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 56962 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 722242 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 129176 # Number of cycles decode is idle +system.cpu.decode.RunCycles 124683 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4086 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 10474 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 8575 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 133808 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 100611 # Number of cache lines fetched +system.cpu.fetch.Cycles 234272 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3473 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 633981 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 135 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 13324 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.253992 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 163537 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 72739 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.203411 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 404675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.896776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.911040 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 253860 62.73% 62.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 12949 3.20% 65.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21905 5.41% 71.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16572 4.10% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 14584 3.60% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15044 3.72% 82.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 9722 2.40% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11097 2.74% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 48942 12.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 404675 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 122145 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4903 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 112391 # Number of branches executed +system.cpu.iew.exec_nop 1275 # number of nop insts executed +system.cpu.iew.exec_rate 1.273889 # Inst execution rate +system.cpu.iew.exec_refs 213078 # number of memory reference insts executed +system.cpu.iew.exec_stores 102494 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 11767 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 104642 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2718 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 107374 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 691884 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 110584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6963 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 671110 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1800 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4086 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1859 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 198 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3186 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 10010 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 13432 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 9811 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 61 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3022 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1881 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 594943 # num instructions consuming a value +system.cpu.iew.wb_count 655034 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.556073 # average fanout of values written-back +system.cpu.iew.wb_producers 330832 # num instructions producing a value +system.cpu.iew.wb_rate 1.243373 # insts written-back per cycle +system.cpu.iew.wb_sent 657761 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 812257 # number of integer regfile reads +system.cpu.int_regfile_writes 486904 # number of integer regfile writes +system.cpu.ipc 0.949095 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.949095 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 461875 68.12% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 394 0.06% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 47 0.01% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 2 0.00% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 17 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 12 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 12 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 23 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 112060 16.53% 84.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 103610 15.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 678078 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 8583 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012658 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2553 29.74% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 29.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3680 42.88% 72.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2350 27.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 686033 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1768889 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 654515 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 769843 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 690039 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 678078 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 80000 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 703 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 50074 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 404675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.675611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.160405 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 204396 50.51% 50.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37521 9.27% 59.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 39470 9.75% 69.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 38527 9.52% 79.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31935 7.89% 86.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20159 4.98% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17354 4.29% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9127 2.26% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6186 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404675 # Number of insts issued each cycle +system.cpu.iq.rate 1.287115 # Inst issue rate +system.cpu.iq.vec_alu_accesses 603 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1223 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 519 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 826 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 7862 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9346 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 104642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 107374 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 467599 # number of misc regfile reads +system.cpu.misc_regfile_writes 2076 # number of misc regfile writes +system.cpu.numCycles 526820 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 16931 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 592966 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3629 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 135453 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 3334 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1046806 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 711285 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 689300 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 126590 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 10645 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4086 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 22463 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 96304 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 864495 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 99152 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3533 # count of serializing insts renamed +system.cpu.rename.skidInsts 36058 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 578 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 696 # Number of vector rename lookups +system.cpu.rob.rob_reads 1052493 # The number of ROB reads +system.cpu.rob.rob_writes 1395785 # The number of ROB writes +system.cpu.timesIdled 1784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 538 # number of vector regfile reads +system.cpu.vec_regfile_writes 71 # number of vector regfile writes +system.cpu.workload.numSyscalls 6 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2964 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 5 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 3456 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 7934 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2083 # Transaction distribution +system.membus.trans_dist::ReadExReq 753 # Transaction distribution +system.membus.trans_dist::ReadExResp 753 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2083 # Transaction distribution +system.membus.trans_dist::InvalidateReq 128 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5800 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 181504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 181504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2964 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2964 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2964 # Request fanout histogram +system.membus.reqLayer0.occupancy 3667000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 15109250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3544 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 649 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2497 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 309 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 807 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 807 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3009 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 535 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 128 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 128 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 8514 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 3898 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 12412 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 352320 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 127424 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 479744 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 4479 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001340 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.036580 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 4473 99.87% 99.87% # Request fanout histogram +system.tol2bus.snoop_fanout::1 6 0.13% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 4479 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 7113000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2077000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 4513500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1330 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 184 # number of demand (read+write) hits +system.l2.demand_hits::total 1514 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1330 # number of overall hits +system.l2.overall_hits::.cpu.data 184 # number of overall hits +system.l2.overall_hits::total 1514 # number of overall hits +system.l2.demand_misses::.cpu.inst 1678 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1158 # number of demand (read+write) misses +system.l2.demand_misses::total 2836 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1678 # number of overall misses +system.l2.overall_misses::.cpu.data 1158 # number of overall misses +system.l2.overall_misses::total 2836 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 135202500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 95779000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 230981500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 135202500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 95779000 # number of overall miss cycles +system.l2.overall_miss_latency::total 230981500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3008 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1342 # number of demand (read+write) accesses +system.l2.demand_accesses::total 4350 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3008 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1342 # number of overall (read+write) accesses +system.l2.overall_accesses::total 4350 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.557846 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.862891 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.651954 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.557846 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.862891 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.651954 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 80573.599523 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82710.708117 # average overall miss latency +system.l2.demand_avg_miss_latency::total 81446.227080 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 80573.599523 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82710.708117 # average overall miss latency +system.l2.overall_avg_miss_latency::total 81446.227080 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1678 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1158 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2836 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1678 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1158 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2836 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 118422500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 84199000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 202621500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 118422500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 84199000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 202621500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.557846 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.862891 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.651954 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.557846 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.862891 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.651954 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 70573.599523 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 72710.708117 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 71446.227080 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 70573.599523 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 72710.708117 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 71446.227080 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 649 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 649 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 649 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2494 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2494 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2494 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2494 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 54 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 54 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 753 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 753 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 60630000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 60630000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 807 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 807 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.933086 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.933086 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 80517.928287 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 80517.928287 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 753 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 753 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 53100000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 53100000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.933086 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.933086 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 70517.928287 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 70517.928287 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1330 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1330 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1678 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1678 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 135202500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 135202500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3008 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3008 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.557846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.557846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 80573.599523 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 80573.599523 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1678 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1678 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 118422500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 118422500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.557846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.557846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 70573.599523 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 70573.599523 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 130 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 130 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 405 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 405 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 35149000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 35149000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 535 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 535 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.757009 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.757009 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86787.654321 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86787.654321 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 405 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 405 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 31099000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 31099000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.757009 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.757009 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76787.654321 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76787.654321 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 128 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 128 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 128 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 128 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 128 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 128 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2454000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2454000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19171.875000 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19171.875000 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1885.587828 # Cycle average of tags in use +system.l2.tags.total_refs 7800 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2955 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.639594 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 58.250121 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1090.851632 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 736.486075 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001778 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.033290 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.022476 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.057544 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2955 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 503 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2389 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.090179 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 66379 # Number of tag accesses +system.l2.tags.data_accesses 66379 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 107392 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 74112 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 181504 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 107392 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 107392 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1678 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1158 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2836 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 407700572 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 281357129 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 689057701 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 407700572 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 407700572 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 407700572 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 281357129 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 689057701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1678.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1158.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000574500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5632 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2836 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2836 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 191 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 154 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 341 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 399 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 193 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 134 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 176 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 202 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 205 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 32664000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 14180000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 85839000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 11517.63 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 30267.63 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2083 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.45 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2836 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1893 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 656 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 206 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming 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write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 751 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 241.427430 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 152.286367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 264.416978 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 305 40.61% 40.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 211 28.10% 68.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 75 9.99% 78.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 46 6.13% 84.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 25 3.33% 88.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 28 3.73% 91.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 14 1.86% 93.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 9 1.20% 94.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 38 5.06% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 751 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 181504 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 181504 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 689.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 689.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.38 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.38 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 263252000 # Total gap between requests +system.mem_ctrls.avgGap 92825.11 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 107392 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 74112 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 407700572.114088773727 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 281357129.027481973171 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1678 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1158 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 49371250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 36467750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 29422.68 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31492.01 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 73.45 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1756440 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 933570 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 8339520 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 88357410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 26743200 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 146413260 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 555.840005 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 68727500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 8580000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 186101500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3619980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1916475 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 11909520 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 117157230 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 2490720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 157377045 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 597.462672 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 4493750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 8580000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 250335250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 96734 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96734 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 96734 # number of overall hits +system.cpu.icache.overall_hits::total 96734 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3876 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3876 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3876 # number of overall misses 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accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.038525 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038525 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 51076.754386 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51076.754386 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 51076.754386 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51076.754386 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 929 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2497 # number of writebacks +system.cpu.icache.writebacks::total 2497 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 867 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 867 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 867 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 867 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 3009 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3009 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 3009 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3009 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 153813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 153813500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 153813500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 153813500 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.029908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.029908 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.029908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.029908 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 51117.813227 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51117.813227 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 51117.813227 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51117.813227 # average overall mshr miss latency +system.cpu.icache.replacements 2497 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 96734 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96734 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 3876 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3876 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 197973500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 197973500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 100610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 100610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.038525 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038525 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 51076.754386 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51076.754386 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 867 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 867 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 3009 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3009 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 153813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 153813500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.029908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.029908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 51117.813227 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51117.813227 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 455.374672 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 99743 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3009 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.148222 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 455.374672 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.889404 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.889404 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 204229 # Number of tag accesses +system.cpu.icache.tags.data_accesses 204229 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 187863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 188370 # number of overall hits +system.cpu.dcache.overall_hits::total 188370 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 4813 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4813 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 4815 # number of overall misses +system.cpu.dcache.overall_misses::total 4815 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 328210839 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328210839 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 328210839 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328210839 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 192676 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192676 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 193185 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193185 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.024980 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024980 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.024924 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024924 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 68192.569915 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68192.569915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 68164.244860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68164.244860 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7001 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2377 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 17 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.830846 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 139.823529 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3346 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3346 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3346 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 1467 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1467 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 1469 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1469 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 103516413 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 103516413 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 103700913 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 103700913 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.007614 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007614 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.007604 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007604 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 70563.335378 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70563.335378 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 70592.861130 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70592.861130 # average overall mshr miss latency +system.cpu.dcache.replacements 958 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 94097 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94097 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1483 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1483 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 103705500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 103705500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 95580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 95580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.015516 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015516 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 69929.534727 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69929.534727 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 951 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 951 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 532 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 532 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 37085500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37085500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.005566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 69709.586466 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69709.586466 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 93765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 93765 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3216 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3216 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 220813916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 220813916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 96981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 96981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033161 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033161 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 68661.043532 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68661.043532 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2395 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2395 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 821 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 821 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 62853490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62853490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.008466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 76557.235079 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76557.235079 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 509 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 509 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.003929 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003929 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.003929 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003929 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 114 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 114 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3691423 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3691423 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 115 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 115 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.991304 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.991304 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32380.903509 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32380.903509 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 114 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 114 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3577423 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3577423 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.991304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.991304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31380.903509 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31380.903509 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 538 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 538 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 250000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 250000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.005545 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.005545 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 83333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 83333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 85500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.001848 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001848 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 85500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 518 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 518 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 518 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 518 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 432.934203 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1470 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 129.861224 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 432.934203 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.845575 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.845575 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 389958 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 389958 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 263409000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 263409000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/report.txt b/report.txt new file mode 100644 index 000000000..e69de29bb diff --git a/run_spec2006_benchmarks.sh b/run_spec2006_benchmarks.sh new file mode 100644 index 000000000..45b6ba749 --- /dev/null +++ b/run_spec2006_benchmarks.sh @@ -0,0 +1,17 @@ +#!/bin/sh + +scons-3 -j 4 ./build/ARM/gem5.opt + +echo "Out of Order execution with TAGE-L-S branch predictor" +count=0 +for bench in astar bwaves bzip2 cactusADM calculix GemsFDTD gobmk gromacs h264ref hmmer lbm leslie3d libquantum mcf milc namd omnetpp povray sjeng sphinx3 xalancbmk; +do + echo -e "Executing bench $bench\n" + ./build/ARM/gem5.opt -d TAGE_SC_L_benchmarks/$bench configs/spec2k6/run.py -b $bench\ + --maxinsts=1000000 --cpu-type=DerivO3CPU --caches --l2cache --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=8\ + --l1d_size=32kB --l1i_size=32kB --l2_size=2MB + count=$(( $count+1 )) + +done + +echo -e "Successfully executed $count total benchmarks" \ No newline at end of file diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 51d912147..1c955aac4 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -171,7 +171,7 @@ def support_take_over(cls): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy") - branchPred = Param.BranchPredictor(TournamentBP(numThreads = + branchPred = Param.BranchPredictor(TAGE_SC_L_8KB(numThreads = Parent.numThreads), "Branch Predictor") needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', diff --git a/src/cpu/pred/BranchPredictor.py b/src/cpu/pred/BranchPredictor.py index 117d40d9a..67871d67e 100644 --- a/src/cpu/pred/BranchPredictor.py +++ b/src/cpu/pred/BranchPredictor.py @@ -309,7 +309,7 @@ class TAGE_SC_L_LoopPredictor(LoopPredictor): cxx_class = 'TAGE_SC_L_LoopPredictor' cxx_header = "cpu/pred/tage_sc_l.hh" loopTableAgeBits = 4 - loopTableConfidenceBits = 4 + loopTableConfidenceBits = 3 loopTableTagBits = 10 loopTableIterBits = 10 useSpeculation = False diff --git a/test.c b/test.c new file mode 100644 index 000000000..eff48e1af --- /dev/null +++ b/test.c @@ -0,0 +1,43 @@ +int main() +{ + int i,j,k,a=1000,b=50; + int sum=0; + for(i=0;i1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1306 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 648 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 2137 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1064 # Transaction distribution +system.membus.trans_dist::ReadExReq 178 # Transaction distribution +system.membus.trans_dist::ReadExResp 178 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1065 # Transaction distribution +system.membus.trans_dist::InvalidateReq 63 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2548 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 79488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1306 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1306 # Request fanout histogram +system.membus.reqLayer0.occupancy 1614000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 6586250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1243 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 50 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 543 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 54 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 182 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 182 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1029 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 216 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 63 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 63 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2599 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1026 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3625 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 100480 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 129152 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1490 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001342 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.036625 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1488 99.87% 99.87% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1490 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1661500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 628500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1540500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 144 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 183 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 144 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 183 # number of overall hits +system.l2.demand_misses::.cpu.inst 885 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 359 # number of demand (read+write) misses +system.l2.demand_misses::total 1244 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 885 # number of overall misses +system.l2.overall_misses::.cpu.data 359 # number of overall misses +system.l2.overall_misses::total 1244 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69107000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 30532500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 99639500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69107000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 30532500 # number of overall miss cycles +system.l2.overall_miss_latency::total 99639500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1029 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 398 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1427 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1029 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 398 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1427 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.860058 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.902010 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.871759 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.860058 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.902010 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.871759 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.demand_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78087.005650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 85048.746518 # average overall miss latency +system.l2.overall_avg_miss_latency::total 80096.061093 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 885 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 359 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1244 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 885 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 359 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1244 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60277000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 26942001 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 87219001 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60277000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 26942001 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 87219001 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.871759 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.902010 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.871759 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 75047.356546 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 70111.737138 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 50 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 50 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 50 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 543 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 543 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 543 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 543 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 4 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 4 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 178 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 178 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 14769000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 182 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.978022 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82971.910112 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 178 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 12988501 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.978022 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72969.106742 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 144 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 885 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69107000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1029 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.860058 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78087.005650 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 885 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60277000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.860058 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68109.604520 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 181 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 15763500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 216 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.837963 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 87091.160221 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 181 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 13953500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.837963 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 77091.160221 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 63 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 63 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 63 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 63 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1198000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19015.873016 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19015.873016 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 674.522414 # Cycle average of tags in use +system.l2.tags.total_refs 2071 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1248 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.659455 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.805164 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 455.337647 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 217.379603 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000055 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013896 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006634 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.020585 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1248 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.038086 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 18336 # Number of tag accesses +system.l2.tags.data_accesses 18336 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56576 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 22976 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 79552 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56576 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 884 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 359 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1243 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 913068388 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 370804922 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1283873310 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 913068388 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 913068388 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 370804922 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1283873310 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 884.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 359.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000554500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2436 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1243 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1243 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 151 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 25 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 12775500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6215000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 36081750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 10277.96 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29027.96 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 971 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.12 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1243 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 698 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 361 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 260 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 297.107692 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.423498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.377322 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 30.00% 30.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 65 25.00% 55.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45 17.31% 72.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 19 7.31% 79.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 6.15% 85.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 3.46% 89.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 1.92% 91.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 2.31% 93.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 6.54% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 260 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 79552 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 79552 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1283.87 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1283.87 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.03 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 61929000 # Total gap between requests +system.mem_ctrls.avgGap 49822.20 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56576 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 22976 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 913068388.137986779213 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 370804922.332055687904 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 884 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 359 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23954000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 12127750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27097.29 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33782.03 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1185240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 607200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4976580 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 27790920 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 390720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 39253140 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 633.498326 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 824000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 59318500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 756840 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3898440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 27598260 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 552960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 37488480 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 605.018842 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1232500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 58910000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6542 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6542 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6542 # number of overall hits +system.cpu.icache.overall_hits::total 6542 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1319 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1319 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1319 # number of overall misses +system.cpu.icache.overall_misses::total 1319 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 91010500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 91010500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 91010500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7861 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.167790 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.167790 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.167790 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.167790 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 68999.620925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68999.620925 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 543 # number of writebacks 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+system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 72191000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72191000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.130899 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.130899 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70156.462585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70156.462585 # average overall mshr miss latency +system.cpu.icache.replacements 543 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 6542 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6542 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1319 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1319 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 91010500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 91010500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 7861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.167790 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.167790 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 68999.620925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68999.620925 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 290 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 72191000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72191000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.130899 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.130899 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 70156.462585 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70156.462585 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 324.833684 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7569 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1027 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.370010 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 324.833684 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.634441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.634441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 16749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 16749 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 11600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 11622 # number of overall hits +system.cpu.dcache.overall_hits::total 11622 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1511 # number of overall misses +system.cpu.dcache.overall_misses::total 1511 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98038926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 98038926 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98038926 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 13105 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 13105 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 13133 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 13133 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.114842 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.114842 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.115054 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115054 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 65142.143522 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65142.143522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 64883.471873 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64883.471873 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 109 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.155963 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 50 # number of writebacks +system.cpu.dcache.writebacks::total 50 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1052 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1052 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1052 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1052 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 453 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 458 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 32772961 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32772961 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 33131461 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33131461 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034874 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 72346.492274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72346.492274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72339.434498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72339.434498 # average overall mshr miss latency +system.cpu.dcache.replacements 104 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 6518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 6518 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 504 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 504 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 33163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33163500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 7022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.071774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.071774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 65800.595238 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65800.595238 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15738000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75663.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5082 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 941 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62963958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6023 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.156234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66911.751328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 756 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15183493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.030716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82072.935135 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 28 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.214286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 358500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.178571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71700 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 60 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1911468 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 60 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31857.800000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 60 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1851468 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30857.800000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 34 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 37 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.081081 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 122166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 3 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 363500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.081081 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 121166.666667 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 231.645691 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12141 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 461 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.336226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 231.645691 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.452433 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 26849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 26849 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 61962500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 61962500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/astar/config.ini b/test_run/astar/config.ini new file mode 100644 index 000000000..1e4d71b2f --- /dev/null +++ b/test_run/astar/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true 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+clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/473.astar/data/ref/input/rivers.cfg +cwd=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=lake.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/astar/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/astar/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/astar/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/astar/config.json b/test_run/astar/config.json new file mode 100644 index 000000000..530d07145 --- /dev/null +++ b/test_run/astar/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/astar/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/astar/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/astar/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.itb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.itb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "itb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[2]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.itb", + "type": "ArmTLB", + "size": 64 + }, + "fetchWidth": 8, + "cpu_id": 0, + "fetchToDecodeDelay": 1, + "renameToDecodeDelay": 1, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [ + "ON", + "CLK_GATED", + "OFF" + ], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.power_state", + "type": "PowerState", + "leaders": [] + }, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": [], + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "Process", + "executable": "/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", + "cwd": "/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run", + "pgid": 100, + "simpoint": 0, + "euid": 100, + "input": "cin", + "path": "system.cpu.workload", + "name": "workload", + "cmd": [ + "/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/run/astar_base.amd64-armcross", + "/home/min/a/ece565/benchspec-2020/CPU2006/473.astar/data/ref/input/rivers.cfg" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "release": "5.1.0", + "output": "lake.out" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + 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"addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + 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"clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + 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"cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/astar/fs/proc/cpuinfo b/test_run/astar/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/astar/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/astar/fs/proc/stat b/test_run/astar/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/astar/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/astar/fs/sys/devices/system/cpu/online b/test_run/astar/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/astar/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/astar/fs/sys/devices/system/cpu/possible b/test_run/astar/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/astar/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/astar/lake.out b/test_run/astar/lake.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/astar/stats.txt b/test_run/astar/stats.txt new file mode 100644 index 000000000..42099d434 --- /dev/null +++ b/test_run/astar/stats.txt @@ -0,0 +1,1343 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 442981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 153235 # Simulator instruction rate (inst/s) +host_mem_usage 855468 # Number of bytes of host memory used +host_op_rate 153841 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.53 # Real time elapsed on the host +host_tick_rate 67878103 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1003978 # Number of ops (including micro ops) simulated +sim_seconds 0.000443 # Number of seconds simulated +sim_ticks 442981000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.317962 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 134261 # Number of BTB hits +system.cpu.branchPred.BTBLookups 135183 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1145 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 138678 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 6 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 205 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 199 # Number of indirect misses. +system.cpu.branchPred.lookups 140939 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 79284 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 37376 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2331 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 114329 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 63 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 10 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 380 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 17819 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 50 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1562 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1678 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3130 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3913 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 5853 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 20479 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 18538 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 26408 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 222 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 5 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 82 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 14960 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 460 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 346 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 17819 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 20 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 22 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 811 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1560 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 173 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1672 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 9 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3130 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 3918 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 5853 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 5 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 20477 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 18538 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 26408 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 128 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 100569 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 73 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 24 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 551 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 66 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 387693 # number of cc regfile reads +system.cpu.cc_regfile_writes 387595 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 800 # The number of times a branch was mispredicted +system.cpu.commit.branches 117621 # Number of branches committed +system.cpu.commit.bw_lim_events 92202 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 84 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 64674 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000203 # Number of instructions committed +system.cpu.commit.committedOps 1004181 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 819030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.226061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.598946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 613257 74.88% 74.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47765 5.83% 80.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19692 2.40% 83.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15401 1.88% 84.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25173 3.07% 88.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2202 0.27% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1855 0.23% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1483 0.18% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 92202 11.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 819030 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 280 # Number of function calls committed. +system.cpu.commit.int_insts 888121 # Number of committed integer instructions. +system.cpu.commit.loads 355397 # Number of loads committed +system.cpu.commit.membars 58 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 531746 52.95% 52.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 11 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 6 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 16 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 8 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 11 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.96% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 18 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 18 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 2 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 15 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 52.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 355397 35.39% 88.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 116855 11.64% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1004181 # Class of committed instruction +system.cpu.commit.refs 472252 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 465 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1003978 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.885963 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.885963 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 625945 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 360 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 130316 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1082831 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 33701 # Number of cycles decode is idle +system.cpu.decode.RunCycles 131525 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1250 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1261 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 35198 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 140939 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7771 # Number of cache lines fetched +system.cpu.fetch.Cycles 802963 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 650 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1100160 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3190 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.159080 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22986 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 134818 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.241767 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 827619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.336913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590994 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 599084 72.39% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 747 0.09% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 88472 10.69% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 713 0.09% 83.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44145 5.33% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 569 0.07% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1714 0.21% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 484 0.06% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 91691 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 827619 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 58344 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 978 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 131695 # Number of branches executed +system.cpu.iew.exec_nop 325 # number of nop insts executed +system.cpu.iew.exec_rate 1.217345 # Inst execution rate +system.cpu.iew.exec_refs 502146 # number of memory reference insts executed +system.cpu.iew.exec_stores 130059 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 13495 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 359106 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 111 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 131145 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1070563 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 372087 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1078523 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 32025 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 32094 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 20859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 129 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 154 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3691 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 14285 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 701 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 277 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1229053 # num instructions consuming a value +system.cpu.iew.wb_count 1051267 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.619020 # average fanout of values written-back +system.cpu.iew.wb_producers 760808 # num instructions producing a value +system.cpu.iew.wb_rate 1.186581 # insts written-back per cycle +system.cpu.iew.wb_sent 1063740 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1483049 # number of integer regfile reads +system.cpu.int_regfile_writes 803389 # number of integer regfile writes +system.cpu.ipc 1.128715 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.128715 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 6 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 576727 53.42% 53.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 12 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 11 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 6 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 16 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 8 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 11 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 22 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 23 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 2 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 53.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 372388 34.49% 87.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 130245 12.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1079565 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 17838 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016523 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205 1.15% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 14 0.08% 1.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 21 0.12% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 16007 89.74% 91.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1587 8.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1096789 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3003537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1050764 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1135810 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1070127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1079565 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 111 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 66214 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 70706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 827619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.304423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.251098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 572164 69.13% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35200 4.25% 73.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11291 1.36% 74.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 50931 6.15% 80.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47784 5.77% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 42357 5.12% 91.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25411 3.07% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 26245 3.17% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 16236 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 827619 # Number of insts issued each cycle +system.cpu.iq.rate 1.218522 # Inst issue rate +system.cpu.iq.vec_alu_accesses 608 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1152 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 503 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 675 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 137 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 638 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 359106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 131145 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1016138 # number of misc regfile reads +system.cpu.misc_regfile_writes 288 # number of misc regfile writes +system.cpu.numCycles 885963 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 45738 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1118217 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 598 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 50400 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 207676 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2022680 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1073704 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1201363 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 149539 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 355124 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1250 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 571580 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 83084 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1480169 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9112 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 248 # count of serializing insts renamed +system.cpu.rename.skidInsts 143419 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 112 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 677 # Number of vector rename lookups +system.cpu.rob.rob_reads 1790197 # The number of ROB reads +system.cpu.rob.rob_writes 2146359 # The number of ROB writes +system.cpu.timesIdled 548 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 583 # number of vector regfile reads +system.cpu.vec_regfile_writes 187 # number of vector regfile writes +system.cpu.workload.numSyscalls 25 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 26907 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 29802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 2 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 60582 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 2 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2178 # Transaction distribution +system.membus.trans_dist::CleanEvict 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 147 # Transaction distribution +system.membus.trans_dist::ReadExResp 147 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2178 # Transaction distribution +system.membus.trans_dist::InvalidateReq 24580 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 29232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 29232 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 148800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 148800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 26905 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 26905 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 26905 # Request fanout histogram +system.membus.reqLayer0.occupancy 28748000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 12279750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2277 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 28182 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 315 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1309 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3923 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3922 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 780 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1497 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 24580 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 24580 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1875 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 89486 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 91361 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 70080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 2150464 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2220544 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 4 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 30784 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000097 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.009872 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 30781 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 30784 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 58788000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 13.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 20418500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 4.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1170000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 75 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 3800 # number of demand (read+write) hits +system.l2.demand_hits::total 3875 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 75 # number of overall hits +system.l2.overall_hits::.cpu.data 3800 # number of overall hits +system.l2.overall_hits::total 3875 # number of overall hits +system.l2.demand_misses::.cpu.inst 705 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1620 # number of demand (read+write) misses +system.l2.demand_misses::total 2325 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 705 # number of overall misses +system.l2.overall_misses::.cpu.data 1620 # number of overall misses +system.l2.overall_misses::total 2325 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 55807000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 122184500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 177991500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 55807000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 122184500 # number of overall miss cycles +system.l2.overall_miss_latency::total 177991500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 780 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5420 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6200 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 780 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5420 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6200 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.903846 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.298893 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.375000 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.903846 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.298893 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.375000 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79158.865248 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75422.530864 # average overall miss latency +system.l2.demand_avg_miss_latency::total 76555.483871 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79158.865248 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75422.530864 # average overall miss latency +system.l2.overall_avg_miss_latency::total 76555.483871 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 705 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1620 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2325 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 705 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1620 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2325 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 48757000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 105984500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 154741500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 48757000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 105984500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 154741500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.298893 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.375000 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.298893 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.375000 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65422.530864 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 66555.483871 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65422.530864 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 66555.483871 # average overall mshr miss latency +system.l2.replacements 4 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 28182 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 28182 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 28182 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 28182 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 315 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 315 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 315 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 315 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3776 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3776 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 147 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 147 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 12044500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 12044500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3923 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3923 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.037471 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.037471 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 81935.374150 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 81935.374150 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 147 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 147 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 10574500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 10574500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.037471 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.037471 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 71935.374150 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 71935.374150 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 75 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 75 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 705 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 705 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 55807000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 55807000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 780 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 780 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.903846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.903846 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79158.865248 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79158.865248 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 705 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 705 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 48757000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 48757000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.903846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.903846 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69158.865248 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69158.865248 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 24 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 24 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1473 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1473 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 110140000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 110140000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1497 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1497 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.983968 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.983968 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 74772.572980 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 74772.572980 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1473 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1473 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 95410000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 95410000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.983968 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.983968 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 64772.572980 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 64772.572980 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 24580 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 24580 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 24580 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 24580 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 24580 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 24580 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 476098500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 476098500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19369.344996 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19369.344996 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 17279.685171 # Cycle average of tags in use +system.l2.tags.total_refs 36001 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 26905 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.338078 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 16079.129966 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 666.131927 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 534.423278 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.490696 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.020329 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.016309 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.527334 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 26901 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 657 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 26170 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.820953 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 511553 # Number of tag accesses +system.l2.tags.data_accesses 511553 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 45120 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 103680 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 148800 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 45120 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 45120 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 705 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1620 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2325 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 101855384 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 234050670 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 335906055 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 101855384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 101855384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 101855384 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 234050670 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 335906055 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 705.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1620.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000577000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4716 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2325 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2325 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 214 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 209 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 83 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 83 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 163 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 167 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 226 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 287 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.08 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15889750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 11625000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 59483500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6834.30 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 25584.30 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2005 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.24 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2325 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1884 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 289 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 108 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 318 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 464.301887 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 281.376593 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 394.299199 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 75 23.58% 23.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 69 21.70% 45.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 27 8.49% 53.77% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 12 3.77% 57.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 27 8.49% 66.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 3.46% 69.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 1.89% 71.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.57% 72.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 86 27.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 318 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 148800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 148800 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 335.91 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 335.91 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.62 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.62 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 442858500 # Total gap between requests +system.mem_ctrls.avgGap 190476.77 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 45120 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 103680 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 101855384.316708847880 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 234050670.344777762890 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 705 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1620 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 19741000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 39742500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28001.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24532.41 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.24 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1285200 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10217340 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 82309140 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 100791840 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 229706460 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 518.546981 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 260843000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 167578000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 999600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 523710 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6383160 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 57325470 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 121830720 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 221482500 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 499.981941 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 316042750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 112378250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 6788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 6788 # number of overall hits +system.cpu.icache.overall_hits::total 6788 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 982 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 982 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 982 # number of overall misses +system.cpu.icache.overall_misses::total 982 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 69824999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69824999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 69824999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69824999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 7770 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7770 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 7770 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7770 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.126384 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.126384 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 71104.886965 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71104.886965 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 71104.886965 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71104.886965 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 939 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 315 # number of writebacks +system.cpu.icache.writebacks::total 315 # number of writebacks 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average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 202 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 202 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 780 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 780 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 57838499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57838499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.100386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.100386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 74151.921795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74151.921795 # average ReadReq mshr miss latency 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task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.908203 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 16320 # Number of tag accesses +system.cpu.icache.tags.data_accesses 16320 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 403810 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 403810 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 403818 # number of overall hits +system.cpu.dcache.overall_hits::total 403818 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 70976 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 70976 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 70978 # number of overall misses +system.cpu.dcache.overall_misses::total 70978 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 2032079271 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2032079271 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 2032079271 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2032079271 # number of overall miss cycles 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miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28629.705979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378769 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 24316 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.576945 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.066667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 28182 # number of writebacks +system.cpu.dcache.writebacks::total 28182 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 40978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 40978 # number of demand (read+write) MSHR hits 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number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 12485 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12485 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 908367000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 908367000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 357989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 357989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.034875 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034875 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 72756.668002 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72756.668002 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 10990 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10990 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1495 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1495 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 112473000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 112473000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.004176 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004176 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 75232.775920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75232.775920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 58306 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 58306 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 33914 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 33914 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 314729727 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 314729727 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 92220 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 92220 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.367751 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.367751 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 9280.230200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9280.230200 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 29988 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 29988 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 59258770 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59258770 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.042572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.042572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 15093.930209 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15093.930209 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 8 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 10 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.200000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 24577 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 24577 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 808982544 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 808982544 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 24577 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 24577 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32916.244619 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32916.244619 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 24577 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 24577 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 784405544 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 784405544 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31916.244619 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31916.244619 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 475.104284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 433945 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 29999 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.465316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 475.104284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.927938 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.927938 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 979847 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 979847 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 442981000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 442981000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/benchs.txt b/test_run/benchs.txt new file mode 100644 index 000000000..93b586cb2 --- /dev/null +++ b/test_run/benchs.txt @@ -0,0 +1 @@ +astar benchs.txt bwaves bzip2 cactusADM calculix dealII gamess GemsFDTD gobmk gromacs h264ref hmmer lbm leslie3d libquantum mcf milc namd omnetpp perlbench povray sjeng soplex specrand_f specrand_i sphinx3 tonto xalancbmk zeusmp \ No newline at end of file diff --git a/test_run/bwaves/config.ini b/test_run/bwaves/config.ini new file mode 100644 index 000000000..276c85d7a --- /dev/null +++ b/test_run/bwaves/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc 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+pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 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system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true 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+power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 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+replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false 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+possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/bwaves/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/bwaves/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/bwaves/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/bwaves/config.json b/test_run/bwaves/config.json new file mode 100644 index 000000000..735dc6d2a --- /dev/null +++ b/test_run/bwaves/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/bwaves/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/bwaves/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/bwaves/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + 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1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/bwaves/fs/proc/cpuinfo b/test_run/bwaves/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/bwaves/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/bwaves/fs/proc/stat b/test_run/bwaves/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/bwaves/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/bwaves/fs/sys/devices/system/cpu/online b/test_run/bwaves/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/bwaves/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/bwaves/fs/sys/devices/system/cpu/possible b/test_run/bwaves/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/bwaves/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/bwaves/stats.txt b/test_run/bwaves/stats.txt new file mode 100644 index 000000000..6a8c26763 --- /dev/null +++ b/test_run/bwaves/stats.txt @@ -0,0 +1,1397 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2378369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 70342 # Simulator instruction rate (inst/s) +host_mem_usage 858120 # Number of bytes of host memory used +host_op_rate 72727 # Simulator op (including micro ops) rate (op/s) +host_seconds 14.22 # Real time elapsed on the host +host_tick_rate 167296326 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1033929 # Number of ops (including micro ops) simulated +sim_seconds 0.002378 # Number of seconds simulated +sim_ticks 2378369000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.771953 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 136892 # Number of BTB hits +system.cpu.branchPred.BTBLookups 138594 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 7 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 18533 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 177123 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 588 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1472 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 884 # Number of indirect misses. +system.cpu.branchPred.lookups 185561 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 75581 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 21590 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 22365 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 74806 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 196 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 679 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 359 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 100 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 51 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 354 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 127 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 104 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 72 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 165 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 54 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 164 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 112 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 153 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 344 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 266 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 286 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 401 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 613 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 854 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2699 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 9454 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 24079 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1815 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1553 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1204 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 27614 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 844 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 192 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 384 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 157 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 184 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 109 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 443 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 148 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 60 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 63 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 139 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 108 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 164 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 300 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 141 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 256 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 343 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 397 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 922 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1456 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 5601 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 29809 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 30659 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 775 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 7812 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2833 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 205 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 328677 # number of cc regfile reads +system.cpu.cc_regfile_writes 340566 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 17987 # The number of times a branch was mispredicted +system.cpu.commit.branches 102118 # Number of branches committed +system.cpu.commit.bw_lim_events 26782 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 162 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 353315 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000217 # Number of instructions committed +system.cpu.commit.committedOps 1034146 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 4632570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.223234 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.967467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 4299727 92.82% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103235 2.23% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 28445 0.61% 95.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72389 1.56% 97.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 82558 1.78% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9442 0.20% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4788 0.10% 99.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5204 0.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 26782 0.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4632570 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 1944 # Number of function calls committed. +system.cpu.commit.int_insts 938116 # Number of committed integer instructions. +system.cpu.commit.loads 14759 # Number of loads committed +system.cpu.commit.membars 100 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 396501 38.34% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 174 0.02% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 4 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 38.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2813 0.27% 38.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 2810 0.27% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3 0.00% 38.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 15 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 38.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 52 0.01% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 38.92% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14759 1.43% 40.34% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 616942 59.66% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1034146 # Class of committed instruction +system.cpu.commit.refs 631701 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 28978 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1033929 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.756740 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.756740 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 4241372 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 563 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117396 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1586891 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 180067 # Number of cycles decode is idle +system.cpu.decode.RunCycles 197238 # Number of cycles decode is running +system.cpu.decode.SquashCycles 19249 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1992 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 49495 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 185561 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 287663 # Number of cache lines fetched +system.cpu.fetch.Cycles 4350270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7143 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1826015 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 39590 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.039010 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 317304 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 140313 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.383880 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 4687421 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.402776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.590550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 4348825 92.78% 92.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16824 0.36% 93.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 8205 0.18% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100126 2.14% 95.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9726 0.21% 95.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 28561 0.61% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8618 0.18% 96.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11338 0.24% 96.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 155198 3.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4687421 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 69319 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 19707 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 119498 # Number of branches executed +system.cpu.iew.exec_nop 293 # number of nop insts executed +system.cpu.iew.exec_rate 0.266983 # Inst execution rate +system.cpu.iew.exec_refs 764673 # number of memory reference insts executed +system.cpu.iew.exec_stores 745527 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 36303 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 19462 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 195 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2418 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 822533 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1387610 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 19146 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 61691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1269971 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2119830 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 19249 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2117384 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 47215 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 497 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 4703 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 205591 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 9167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 10540 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 834910 # num instructions consuming a value +system.cpu.iew.wb_count 1244931 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.370368 # average fanout of values written-back +system.cpu.iew.wb_producers 309224 # num instructions producing a value +system.cpu.iew.wb_rate 0.261719 # insts written-back per cycle +system.cpu.iew.wb_sent 1267715 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2693361 # number of integer regfile reads +system.cpu.int_regfile_writes 401477 # number of integer regfile writes +system.cpu.ipc 0.210228 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210228 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 514474 38.63% 38.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 181 0.01% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 32 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 38.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3498 0.26% 38.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 3007 0.23% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 23 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 23 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 39.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 39.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 19807 1.49% 40.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 790514 59.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1331662 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 90929 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.068282 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 987 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 12 0.01% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 355 0.39% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 89574 98.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1383514 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 7384267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1207905 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1689028 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1387122 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1331662 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 195 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 353388 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 359181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 4687421 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.284093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.096581 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4289827 91.52% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107593 2.30% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 58099 1.24% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 45950 0.98% 96.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43828 0.94% 96.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 87848 1.87% 98.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35663 0.76% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7413 0.16% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11200 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4687421 # Number of insts issued each cycle +system.cpu.iq.rate 0.279953 # Inst issue rate +system.cpu.iq.vec_alu_accesses 39073 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 78578 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 37026 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 51706 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 70 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 286 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 19462 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 822533 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1324545 # number of misc regfile reads +system.cpu.misc_regfile_writes 6031 # number of misc regfile writes +system.cpu.numCycles 4756740 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 2153805 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 605959 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 59 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 202563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 12 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 3686396 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1479083 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 871657 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 220703 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 2069360 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 19249 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 2070152 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 265698 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 3143972 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20949 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 667 # count of serializing insts renamed +system.cpu.rename.skidInsts 372322 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 197 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 45801 # Number of vector rename lookups +system.cpu.rob.rob_reads 5977064 # The number of ROB reads +system.cpu.rob.rob_writes 2829843 # The number of ROB writes +system.cpu.timesIdled 878 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 37736 # number of vector regfile reads +system.cpu.vec_regfile_writes 6435 # number of vector regfile writes +system.cpu.workload.numSyscalls 61 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 41715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 116674 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 75274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 151539 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 475 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 991 # Transaction distribution +system.membus.trans_dist::WritebackDirty 41216 # Transaction distribution +system.membus.trans_dist::CleanEvict 499 # Transaction distribution +system.membus.trans_dist::ReadExReq 73861 # Transaction distribution +system.membus.trans_dist::ReadExResp 73860 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 991 # Transaction distribution +system.membus.trans_dist::InvalidateReq 107 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 191525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 191525 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 7428288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 7428288 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 74959 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 74959 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 74959 # Request fanout histogram +system.membus.reqLayer0.occupancy 300234000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 12.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 389480500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1611 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 115521 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 865 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1078 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 74547 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 74543 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1340 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 271 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 107 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 107 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3545 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 224255 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 227800 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 141120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 9543616 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 9684736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 42190 # Total snoops (count) +system.tol2bus.snoopTraffic 2637824 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 118455 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.004018 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.063264 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 117979 99.60% 99.60% # Request fanout histogram +system.tol2bus.snoop_fanout::1 476 0.40% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 118455 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 150939500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 112274500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2010000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 467 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 836 # number of demand (read+write) hits +system.l2.demand_hits::total 1303 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 467 # number of overall hits +system.l2.overall_hits::.cpu.data 836 # number of overall hits +system.l2.overall_hits::total 1303 # number of overall hits +system.l2.demand_misses::.cpu.inst 873 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 73982 # number of demand (read+write) misses +system.l2.demand_misses::total 74855 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 873 # number of overall misses +system.l2.overall_misses::.cpu.data 73982 # number of overall misses +system.l2.overall_misses::total 74855 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 69165000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 6999555500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 7068720500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 69165000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 6999555500 # number of overall miss cycles +system.l2.overall_miss_latency::total 7068720500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1340 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 74818 # number of demand (read+write) accesses +system.l2.demand_accesses::total 76158 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1340 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 74818 # number of overall (read+write) accesses +system.l2.overall_accesses::total 76158 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.651493 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.988826 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.982891 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.651493 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.988826 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.982891 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79226.804124 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 94611.601471 # average overall miss latency +system.l2.demand_avg_miss_latency::total 94432.175539 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79226.804124 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 94611.601471 # average overall miss latency +system.l2.overall_avg_miss_latency::total 94432.175539 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 41216 # number of writebacks +system.l2.writebacks::total 41216 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 873 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 73982 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 74855 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 873 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 73982 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 74855 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 60435000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 6259775500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 6320210500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 60435000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 6259775500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 6320210500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.988826 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.982891 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.988826 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.982891 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 84612.142143 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 84432.709906 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 84612.142143 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 84432.709906 # average overall mshr miss latency +system.l2.replacements 42190 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 74305 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 74305 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 74305 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 74305 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 865 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 865 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 865 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 865 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 683 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 683 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 73864 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 73864 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 6989304500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 6989304500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 74547 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 74547 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990838 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990838 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 94623.964313 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 94623.964313 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 73864 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 73864 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 6250704500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 6250704500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990838 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990838 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 84624.505849 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 84624.505849 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 467 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 467 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 873 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 873 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 69165000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 69165000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1340 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1340 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.651493 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.651493 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79226.804124 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79226.804124 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 873 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 873 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 60435000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 60435000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.651493 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.651493 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69226.804124 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69226.804124 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 153 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 153 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 118 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 118 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10251000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10251000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 271 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 271 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.435424 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.435424 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86872.881356 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86872.881356 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 118 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 118 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9071000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9071000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.435424 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.435424 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76872.881356 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76872.881356 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 107 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 107 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 107 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 107 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 107 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 107 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2034500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2034500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19014.018692 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19014.018692 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 26084.782711 # Cycle average of tags in use +system.l2.tags.total_refs 151427 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 74958 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.020158 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 38.053228 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 310.191124 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 25736.538359 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001161 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.009466 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.785417 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.796044 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 2582 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 25922 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::3 3978 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1287262 # Number of tag accesses +system.l2.tags.data_accesses 1287262 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 55872 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 4734592 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 4790464 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 55872 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 55872 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 2637824 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 2637824 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 873 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 73978 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 74851 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 41216 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 41216 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 23491729 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1990688577 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2014180306 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 23491729 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 23491729 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1109089464 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1109089464 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1109089464 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 23491729 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1990688577 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3123269770 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 41216.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 873.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 73979.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000174410500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 2554 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 2554 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 172973 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 38701 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 74852 # Number of read requests accepted +system.mem_ctrls.writeReqs 41216 # Number of write requests accepted +system.mem_ctrls.readBursts 74852 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 41216 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 4674 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 4665 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 4710 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 4726 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 4740 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4803 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 4820 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 4712 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 4566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 4635 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 4584 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 4570 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 4719 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 4585 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 4706 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 4637 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 2595 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 2603 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 2624 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 2562 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 2634 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 2683 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 2682 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 2560 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 2499 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 2499 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2472 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 2469 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 2557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 2507 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 2661 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 2580 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 17.09 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 1781946000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 374260000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 3185421000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 23806.26 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 42556.26 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 63077 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 34486 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 84.27 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 83.67 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 74852 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 41216 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 23533 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 18550 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 17494 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 15264 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 84 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 532 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1427 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 1986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2588 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2900 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2596 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2585 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2581 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2643 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2590 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2603 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2738 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2796 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 5008 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2816 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 18465 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 402.082210 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 283.705525 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 301.849556 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3011 16.31% 16.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3435 18.60% 34.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3612 19.56% 54.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1735 9.40% 63.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1357 7.35% 71.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1709 9.26% 80.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1843 9.98% 90.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 201 1.09% 91.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1562 8.46% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 18465 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2554 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 29.302662 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.457594 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 634.033065 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 2553 99.96% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2554 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2554 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.126468 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.116603 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.601001 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2419 94.71% 94.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 34 1.33% 96.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 37 1.45% 97.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 53 2.08% 99.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.23% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.04% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.04% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 3 0.12% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2554 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 4790528 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2635968 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 4790528 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 2637824 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2014.21 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1108.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2014.21 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1109.09 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 24.39 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 15.74 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 8.66 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 2378355500 # Total gap between requests +system.mem_ctrls.avgGap 20491.05 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 55872 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 4734656 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 2635968 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 23491728.995795018971 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1990715486.116746425629 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1108309097.537009716034 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 873 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 73979 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 41216 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 24503500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 3160917500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 38198167750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28068.16 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 42727.23 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 926780.08 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 84.06 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 69143760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 36728010 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 264194280 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 105673680 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 187465200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 1035260220 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 41496000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 1739961150 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 731.577459 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 96474000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 79300000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 2202595000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 62774880 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 33346665 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 270249000 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 109322460 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 187465200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 974878410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 92343840 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 1730380455 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 727.549197 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 229260750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 79300000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states 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50442.748092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50442.748092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 259 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 11620500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11620500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.015470 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015470 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 43850.943396 # average ReadReq mshr miss latency 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number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3218954 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3218954 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 121 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 121 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.834711 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.834711 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31870.831683 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31870.831683 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 101 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 101 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3117954 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3117954 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.834711 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.834711 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30870.831683 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30870.831683 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 127 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 312500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 128 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 128 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.007812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.007812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 312500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 311500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007812 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007812 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 311500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 100 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 100 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 502.584179 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 548170 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 74921 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.316640 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 502.584179 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.981610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.981610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1343429 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1343429 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2378369000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 2378369000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/bzip2/config.ini b/test_run/bzip2/config.ini new file mode 100644 index 000000000..c640ffa65 --- /dev/null +++ b/test_run/bzip2/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 system.cpu.fuPool.FUList5.opList20 system.cpu.fuPool.FUList5.opList21 system.cpu.fuPool.FUList5.opList22 system.cpu.fuPool.FUList5.opList23 system.cpu.fuPool.FUList5.opList24 system.cpu.fuPool.FUList5.opList25 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2/data/ref/input/input.source 1 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/401.bzip2//exe/bzip2_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=input.source.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/bzip2/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/bzip2/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/bzip2/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/bzip2/config.json b/test_run/bzip2/config.json new file mode 100644 index 000000000..8ae29dd3b --- /dev/null +++ b/test_run/bzip2/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/bzip2/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/bzip2/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/bzip2/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": 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0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/bzip2/fs/proc/cpuinfo b/test_run/bzip2/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/bzip2/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/bzip2/fs/proc/stat b/test_run/bzip2/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/bzip2/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/bzip2/fs/sys/devices/system/cpu/online b/test_run/bzip2/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/bzip2/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/bzip2/fs/sys/devices/system/cpu/possible b/test_run/bzip2/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/bzip2/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/bzip2/input.source.out b/test_run/bzip2/input.source.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/bzip2/stats.txt b/test_run/bzip2/stats.txt new file mode 100644 index 000000000..6115ea195 --- /dev/null +++ b/test_run/bzip2/stats.txt @@ -0,0 +1,1385 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 378669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 129383 # Simulator instruction rate (inst/s) +host_mem_usage 850904 # Number of bytes of host memory used +host_op_rate 136282 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.73 # Real time elapsed on the host +host_tick_rate 48992342 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1053339 # Number of ops (including micro ops) simulated +sim_seconds 0.000379 # Number of seconds simulated +sim_ticks 378669000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.503404 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115614 # Number of BTB hits +system.cpu.branchPred.BTBLookups 116191 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 2464 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 165497 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 7 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 226 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 219 # Number of indirect misses. +system.cpu.branchPred.lookups 215070 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95597 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 25234 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89459 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 31372 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 77 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 17 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1398 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3995 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1548 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2699 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 4225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 691 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1062 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1543 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1073 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1096 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1741 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2997 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1489 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 3809 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2871 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1179 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1383 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 91 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 510 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 72520 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 390 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1150 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 613 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3333 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 828 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5300 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1929 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4449 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 886 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1064 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 936 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 872 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1487 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1877 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1646 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 4123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 2434 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2290 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1615 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 44496 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 359 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1004 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 1255 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 58 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 313770 # number of cc regfile reads +system.cpu.cc_regfile_writes 314274 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 2236 # The number of times a branch was mispredicted +system.cpu.commit.branches 166034 # Number of branches committed +system.cpu.commit.bw_lim_events 89784 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 60 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 186372 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000753 # Number of instructions committed +system.cpu.commit.committedOps 1054092 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 689773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.528172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.731295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417532 60.53% 60.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116341 16.87% 77.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 28634 4.15% 81.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 17254 2.50% 84.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4031 0.58% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6864 1.00% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5326 0.77% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4007 0.58% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89784 13.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 689773 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 949 # Number of function calls committed. +system.cpu.commit.int_insts 932693 # Number of committed integer instructions. +system.cpu.commit.loads 381890 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 9 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 499972 47.43% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 23 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 47.43% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 29 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 34 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 36 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 47.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 26 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 47.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 381890 36.23% 83.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 172070 16.32% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1054092 # Class of committed instruction +system.cpu.commit.refs 553960 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 224 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1053339 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.757339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.757339 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 360461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 238 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 107076 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1267054 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 119405 # Number of cycles decode is idle +system.cpu.decode.RunCycles 192717 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3090 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 38933 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 215070 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157254 # Number of cache lines fetched +system.cpu.fetch.Cycles 542149 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1264248 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6636 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.283981 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 169064 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 116876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.669329 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 714606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.851436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.916258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 423481 59.26% 59.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 93221 13.05% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14864 2.08% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3790 0.53% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24832 3.47% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40621 5.68% 84.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2761 0.39% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18559 2.60% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 92477 12.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 714606 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2409 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 196664 # Number of branches executed +system.cpu.iew.exec_nop 1021 # number of nop insts executed +system.cpu.iew.exec_rate 1.740594 # Inst execution rate +system.cpu.iew.exec_refs 722788 # number of memory reference insts executed +system.cpu.iew.exec_stores 202589 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 32308 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 426666 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 208592 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1244237 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 520199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1318220 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 23397 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3090 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 22831 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2201 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 114 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 72 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 57119 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 44776 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 36521 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 72 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1520 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 889 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1296071 # num instructions consuming a value +system.cpu.iew.wb_count 1190532 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.595900 # average fanout of values written-back +system.cpu.iew.wb_producers 772329 # num instructions producing a value +system.cpu.iew.wb_rate 1.571994 # insts written-back per cycle +system.cpu.iew.wb_sent 1216310 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1585569 # number of integer regfile reads +system.cpu.int_regfile_writes 864051 # number of integer regfile writes +system.cpu.ipc 1.320413 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.320413 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 596296 45.14% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 26 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 35 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 38 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 40 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 28 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 45.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 521557 39.48% 84.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 203026 15.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1321063 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 25708 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019460 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1956 7.61% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22214 86.41% 94.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1533 5.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1346476 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3382155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1190281 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1432674 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1243135 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1321063 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 189873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 300 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 119405 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 714606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.848659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.064894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 293888 41.13% 41.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78022 10.92% 52.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 110896 15.52% 67.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 75702 10.59% 78.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 71454 10.00% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35453 4.96% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22686 3.17% 96.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17094 2.39% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9411 1.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 714606 # Number of insts issued each cycle +system.cpu.iq.rate 1.744348 # Inst issue rate +system.cpu.iq.vec_alu_accesses 285 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 585 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 251 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 478 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 106597 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65049 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 426666 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 208592 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1050401 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 757339 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 82529 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 994060 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 9884 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 138535 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 71021 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1546 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1838328 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1257405 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1218260 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 211199 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 176346 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3090 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 269320 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 224182 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1510334 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 9933 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 206 # count of serializing insts renamed +system.cpu.rename.skidInsts 227667 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 486 # Number of vector rename lookups +system.cpu.rob.rob_reads 1830001 # The number of ROB reads +system.cpu.rob.rob_writes 2505786 # The number of ROB writes +system.cpu.timesIdled 374 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 333 # number of vector regfile reads +system.cpu.vec_regfile_writes 167 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1159 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6744 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4866 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 16 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10619 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 16 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2017 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1151 # Transaction distribution +system.membus.trans_dist::CleanEvict 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 3561 # Transaction distribution +system.membus.trans_dist::ReadExResp 3561 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2017 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 12322 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 5585 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5585 # Request fanout histogram +system.membus.reqLayer0.occupancy 12181000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 28800250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.6 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2150 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4546 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 142 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1353 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3595 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 517 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1633 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 8 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 8 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1176 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15196 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16372 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42176 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 551872 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 594048 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1175 # Total snoops (count) +system.tol2bus.snoopTraffic 73664 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6928 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002454 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.049479 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6911 99.75% 99.75% # Request fanout histogram +system.tol2bus.snoop_fanout::1 17 0.25% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6928 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 8846500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 7846000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 775500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 9 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 158 # number of demand (read+write) hits +system.l2.demand_hits::total 167 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 9 # number of overall hits +system.l2.overall_hits::.cpu.data 158 # number of overall hits +system.l2.overall_hits::total 167 # number of overall hits +system.l2.demand_misses::.cpu.inst 508 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5070 # number of demand (read+write) misses +system.l2.demand_misses::total 5578 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 508 # number of overall misses +system.l2.overall_misses::.cpu.data 5070 # number of overall misses +system.l2.overall_misses::total 5578 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40426500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 445531000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 485957500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40426500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 445531000 # number of overall miss cycles +system.l2.overall_miss_latency::total 485957500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 517 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5228 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5745 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 517 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5228 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5745 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.982592 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.969778 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.970931 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.982592 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.969778 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.970931 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.demand_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79579.724409 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87875.936884 # average overall miss latency +system.l2.overall_avg_miss_latency::total 87120.383650 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1151 # number of writebacks +system.l2.writebacks::total 1151 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 508 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5070 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 5578 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 508 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5070 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 5578 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35346500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 394831000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 430177500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35346500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 394831000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 430177500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.970931 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.969778 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.970931 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77875.936884 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 77120.383650 # average overall mshr miss latency +system.l2.replacements 1175 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3395 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3395 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 142 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 142 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 142 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 142 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 34 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 34 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3561 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3561 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 325566000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3595 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.990542 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 91425.442291 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3561 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 289956000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.990542 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 81425.442291 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 9 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40426500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 517 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.982592 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79579.724409 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 508 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35346500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.982592 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69579.724409 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 124 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1509 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 119965000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1633 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.924066 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 79499.668655 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1509 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 104875000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.924066 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 69499.668655 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.875000 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.875000 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3219.497523 # Cycle average of tags in use +system.l2.tags.total_refs 10611 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 5590 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.898211 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 7.025790 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 423.809713 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2788.662020 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000214 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.012934 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.085103 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.098251 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 4119 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.134705 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 90534 # Number of tag accesses +system.l2.tags.data_accesses 90534 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32512 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 324480 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 356992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32512 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 73664 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 73664 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 508 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5070 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 5578 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1151 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1151 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 85858626 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 856896128 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 942754754 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 85858626 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 194534013 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 194534013 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 85858626 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 856896128 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1137288767 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1151.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 508.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5070.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000326398500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 70 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 70 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 11431 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 1054 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 5578 # Number of read requests accepted +system.mem_ctrls.writeReqs 1151 # Number of write requests accepted +system.mem_ctrls.readBursts 5578 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1151 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 353 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 445 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 432 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 309 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 267 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 285 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 270 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 67 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 70 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 71 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 65 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 20.52 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 94535750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 27890000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 199123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16947.97 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 35697.97 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4807 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 945 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.18 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.10 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 5578 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1151 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1928 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1431 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1215 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 984 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 70 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 129 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 138 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 74 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 945 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 453.079365 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 384.495920 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 199.503629 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 78 8.25% 8.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 87 9.21% 17.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48 5.08% 22.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 4.02% 26.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 630 66.67% 93.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.95% 94.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 20 2.12% 96.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.21% 96.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 33 3.49% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 945 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 70 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 76.500000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 21.987624 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.513517 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 64 91.43% 91.43% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-255 1 1.43% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::256-383 4 5.71% 98.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2560-2687 1 1.43% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 70 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 70 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 70 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 70 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 356992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 71680 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 356992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 73664 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 942.75 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 189.29 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 942.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 194.53 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.84 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 7.37 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 378545500 # Total gap between requests +system.mem_ctrls.avgGap 56255.83 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 324480 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 71680 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 85858625.871143400669 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 856896128.280899643898 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 189294608.219843715429 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 508 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5070 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1151 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14431750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 184691500 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 3158337250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28408.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 36428.30 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 2743994.14 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 85.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3127320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1658415 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 20149080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 2949300 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 165006450 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 6456480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 228849765 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 604.353050 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 15482250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 350706750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 3627120 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1927860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 19677840 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 2897100 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 77622600 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 80042880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 215298120 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 568.565475 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 207448500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 158740500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 156559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 156559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 156559 # number of overall hits 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 142 # number of writebacks +system.cpu.icache.writebacks::total 142 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 177 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 517 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 517 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 517 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 517 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41303999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41303999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41303999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.003288 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003288 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.003288 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003288 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79891.680851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79891.680851 # average overall mshr miss latency +system.cpu.icache.replacements 142 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 156559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 156559 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 694 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 52763999 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 303.822050 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 345.595783 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.674992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.674992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 375 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 315023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 315023 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 464703 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 464703 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 464720 # number of overall hits +system.cpu.dcache.overall_hits::total 464720 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 8891 # number of demand (read+write) misses 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+system.cpu.dcache.WriteReq_accesses::.cpu.data 172029 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172029 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 79486.179232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.179232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3595 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3595 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 331352977 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 331352977 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.020898 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92170.508206 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 17 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 20 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.150000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.150000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 107333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 44 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 84000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 46 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 399.938493 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 89.770053 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 399.938493 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.781130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 174 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 952628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 952628 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 378669000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 378669000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/cactusADM/benchADM.out b/test_run/cactusADM/benchADM.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/cactusADM/config.ini b/test_run/cactusADM/config.ini new file mode 100644 index 000000000..32d875906 --- /dev/null +++ b/test_run/cactusADM/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] 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+type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//data/ref/input/benchADM.par +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/436.cactusADM//exe/cactusADM_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=benchADM.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/cactusADM/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/cactusADM/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/cactusADM/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/cactusADM/config.json b/test_run/cactusADM/config.json new file mode 100644 index 000000000..411255c1c --- /dev/null +++ b/test_run/cactusADM/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + 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"static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/cactusADM/fs/proc/cpuinfo b/test_run/cactusADM/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/cactusADM/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/cactusADM/fs/proc/stat b/test_run/cactusADM/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/cactusADM/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/cactusADM/fs/sys/devices/system/cpu/online b/test_run/cactusADM/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/cactusADM/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/cactusADM/fs/sys/devices/system/cpu/possible b/test_run/cactusADM/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/cactusADM/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/cactusADM/stats.txt b/test_run/cactusADM/stats.txt new file mode 100644 index 000000000..734909a18 --- /dev/null +++ b/test_run/cactusADM/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 468934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 141425 # Simulator instruction rate (inst/s) +host_mem_usage 857932 # Number of bytes of host memory used +host_op_rate 157746 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.07 # Real time elapsed on the host +host_tick_rate 66317091 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1115434 # Number of ops (including micro ops) simulated +sim_seconds 0.000469 # Number of seconds simulated +sim_ticks 468934500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.262346 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 141471 # Number of BTB hits +system.cpu.branchPred.BTBLookups 145453 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 9391 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 220443 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3812 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 4741 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 929 # Number of indirect misses. +system.cpu.branchPred.lookups 302124 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95777 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 77037 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 92105 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80709 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 741 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 220 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 20202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1973 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 864 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1733 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3428 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1457 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 3210 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3917 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 4292 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 4162 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 2969 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1781 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 638 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1316 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 3060 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 386 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 476 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 314 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 142 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1900 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 617 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 883 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 108110 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2099 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3520 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4793 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1956 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1090 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4841 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 4720 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2582 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 3607 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 3667 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 4716 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4073 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1191 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 2928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 887 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 4328 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 515 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 637 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 510 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 348 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 54309 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 445 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1757 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 30296 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 519 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 359643 # number of cc regfile reads +system.cpu.cc_regfile_writes 343424 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 8332 # The number of times a branch was mispredicted +system.cpu.commit.branches 231894 # Number of branches committed +system.cpu.commit.bw_lim_events 61305 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 150260 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001506 # Number of instructions committed +system.cpu.commit.committedOps 1116940 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 825652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.352798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.277638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 431090 52.21% 52.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 199057 24.11% 76.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 65640 7.95% 84.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25941 3.14% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18585 2.25% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7816 0.95% 90.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8606 1.04% 91.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7612 0.92% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61305 7.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825652 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 22009 # Number of function calls committed. +system.cpu.commit.int_insts 1003889 # Number of committed integer instructions. +system.cpu.commit.loads 188126 # Number of loads committed +system.cpu.commit.membars 234 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 8 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 793381 71.03% 71.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 444 0.04% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 14 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 20 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 54 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 61 0.01% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 188126 16.84% 87.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 134785 12.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1116940 # Class of committed instruction +system.cpu.commit.refs 322911 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1515 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1115434 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.937870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.937870 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 351151 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1084 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131130 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1328223 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 235007 # Number of cycles decode is idle +system.cpu.decode.RunCycles 224796 # Number of cycles decode is running +system.cpu.decode.SquashCycles 8407 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4080 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 29047 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 302124 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 222644 # Number of cache lines fetched +system.cpu.fetch.Cycles 535575 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1285656 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18932 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.322138 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 303270 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 175579 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.370825 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 848408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696105 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.699079 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 525019 61.88% 61.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42918 5.06% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 73846 8.70% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28765 3.39% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26350 3.11% 82.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30088 3.55% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28164 3.32% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8804 1.04% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 84454 9.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 848408 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 89462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9865 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 251794 # Number of branches executed +system.cpu.iew.exec_nop 1869 # number of nop insts executed +system.cpu.iew.exec_rate 1.303190 # Inst execution rate +system.cpu.iew.exec_refs 355366 # number of memory reference insts executed +system.cpu.iew.exec_stores 146931 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 16550 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 213838 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 154189 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1267807 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 208435 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1222223 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 4213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8407 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4294 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2777 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 50 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 62 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25707 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 19402 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 62 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 6197 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3668 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1106565 # num instructions consuming a value +system.cpu.iew.wb_count 1213951 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.582876 # average fanout of values written-back +system.cpu.iew.wb_producers 644990 # num instructions producing a value +system.cpu.iew.wb_rate 1.294370 # insts written-back per cycle +system.cpu.iew.wb_sent 1218084 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1420776 # number of integer regfile reads +system.cpu.int_regfile_writes 874576 # number of integer regfile writes +system.cpu.ipc 1.066246 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.066246 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 9 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 871958 70.78% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480 0.04% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 14 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 58 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 18 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 68 0.01% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 210407 17.08% 87.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 148868 12.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1231948 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14526 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011791 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4852 33.40% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 33.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4991 34.36% 67.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4678 32.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1244743 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3323953 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1212381 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1414639 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1265632 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1231948 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150480 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 495 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 78863 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 848408 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 393727 46.41% 46.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150412 17.73% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 105051 12.38% 76.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72755 8.58% 85.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52873 6.23% 91.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32913 3.88% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 19751 2.33% 97.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8802 1.04% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12124 1.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 848408 # Number of insts issued each cycle +system.cpu.iq.rate 1.313559 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1722 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3369 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1570 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1837 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 5612 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9134 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 213838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 154189 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1000136 # number of misc regfile reads +system.cpu.misc_regfile_writes 957 # number of misc regfile writes +system.cpu.numCycles 937870 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 21506 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1121395 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 249451 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 444 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1970254 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1295032 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1298125 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239899 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5945 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 8407 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 30468 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 176678 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1507674 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 298677 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 18843 # count of serializing insts renamed +system.cpu.rename.skidInsts 135698 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 311 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1703 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031157 # The number of ROB reads +system.cpu.rob.rob_writes 2557380 # The number of ROB writes +system.cpu.timesIdled 2383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1549 # number of vector regfile reads +system.cpu.vec_regfile_writes 238 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2163 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4766 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10513 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1294 # Transaction distribution +system.membus.trans_dist::ReadExReq 793 # Transaction distribution +system.membus.trans_dist::ReadExResp 793 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1294 # Transaction distribution +system.membus.trans_dist::InvalidateReq 76 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4250 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 133568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2163 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2163 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2163 # Request fanout histogram +system.membus.reqLayer0.occupancy 2694500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 11077500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4801 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 781 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 3742 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 243 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 868 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 868 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 4213 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 588 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 78 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 78 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 12168 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4092 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16260 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 509120 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 143168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 652288 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5747 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000174 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013191 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5746 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5747 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9779500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2223499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 6319500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 3199 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 383 # number of demand (read+write) hits +system.l2.demand_hits::total 3582 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 3199 # number of overall hits +system.l2.overall_hits::.cpu.data 383 # number of overall hits +system.l2.overall_hits::total 3582 # number of overall hits +system.l2.demand_misses::.cpu.inst 1014 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1073 # number of demand (read+write) misses +system.l2.demand_misses::total 2087 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1014 # number of overall misses +system.l2.overall_misses::.cpu.data 1073 # number of overall misses +system.l2.overall_misses::total 2087 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 79654500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 85698500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 165353000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 79654500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 85698500 # number of overall miss cycles +system.l2.overall_miss_latency::total 165353000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 4213 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1456 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5669 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 4213 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1456 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5669 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.240684 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.736951 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.368143 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.240684 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.736951 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.368143 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78554.733728 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 79868.126747 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79229.995208 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1014 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1073 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2087 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1014 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1073 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2087 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 69514500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 74968500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 144483000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 69514500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 74968500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 144483000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.368143 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.736951 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.368143 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 69868.126747 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69229.995208 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 781 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 781 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 781 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 3742 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 3742 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 3742 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 3742 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 75 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 75 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 793 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 793 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 62454000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 868 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.913594 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78756.620429 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 793 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 54524000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.913594 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68756.620429 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 3199 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1014 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 79654500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 4213 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.240684 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78554.733728 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 69514500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.240684 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68554.733728 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 308 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 280 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 23244500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 588 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.476190 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83016.071429 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 280 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 20444500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.476190 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73016.071429 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 76 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 76 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 78 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.974359 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 76 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1437000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.974359 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18907.894737 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18907.894737 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1545.070072 # Cycle average of tags in use +system.l2.tags.total_refs 10436 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2145 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 4.865268 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 34.455603 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 823.783092 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 686.831377 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001052 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.025140 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.020960 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047152 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2143 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1854 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.065399 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 86241 # Number of tag accesses +system.l2.tags.data_accesses 86241 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 64896 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 68672 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 133568 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1014 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1073 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2087 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 138390330 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 146442627 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 284832956 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 138390330 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 138390330 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 146442627 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 284832956 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1014.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1073.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 4241 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2087 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2087 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 116 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 98 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 135 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 121 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 89 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 19480500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 10435000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 58611750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9334.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28084.21 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1636 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.39 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2087 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1462 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 439 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 295.537778 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 184.185643 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 301.373367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 148 32.89% 32.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 130 28.89% 61.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 47 10.44% 72.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 6.67% 78.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 20 4.44% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 16 3.56% 86.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 18 4.00% 90.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.11% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 36 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 133568 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 133568 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 284.83 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 284.83 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.23 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 468792000 # Total gap between requests +system.mem_ctrls.avgGap 224624.82 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 64896 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 68672 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 138390329.566282719374 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 146442626.848738998175 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1014 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1073 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 27791000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 30820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27407.30 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28723.90 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.39 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1570800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 834900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6418860 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 127052430 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 73079520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 245834910 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 524.241467 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 188810000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 264524500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1649340 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 872850 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 8482320 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 36878400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 181366590 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 27341280 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 256590780 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 547.178295 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 69488250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 383846250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 217852 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217852 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 217852 # number of overall hits +system.cpu.icache.overall_hits::total 217852 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 4790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 4790 # number of overall misses +system.cpu.icache.overall_misses::total 4790 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 141209999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 141209999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 141209999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 141209999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 222642 # number of demand (read+write) accesses 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miss latency +system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 3742 # number of writebacks +system.cpu.icache.writebacks::total 3742 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 577 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 577 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 577 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 577 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 4213 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4213 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 4213 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4213 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 119761000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 119761000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 119761000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 119761000 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.018923 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018923 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.018923 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 28426.536910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28426.536910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 28426.536910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28426.536910 # average overall mshr miss latency +system.cpu.icache.replacements 3742 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 217852 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217852 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 4790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4790 # number of ReadReq misses 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+system.cpu.icache.tags.sampled_refs 4213 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 52.709471 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 432.493594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.844714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.844714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 471 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.919922 # Percentage of cache occupancy per task id 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(read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 334586 # number of overall hits +system.cpu.dcache.overall_hits::total 334586 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 4594 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4594 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 4596 # number of overall misses +system.cpu.dcache.overall_misses::total 4596 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 288853920 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 288853920 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 288853920 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 288853920 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 338662 # number of demand (read+write) accesses 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miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.339286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 781 # number of writebacks +system.cpu.dcache.writebacks::total 781 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3078 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3078 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3078 # number of overall MSHR hits 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+system.cpu.dcache.ReadReq_misses::total 1153 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 57372500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57372500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 204045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 204045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.005651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 49759.323504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49759.323504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 570 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 26961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.002794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 47300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47300 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 131149 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3386 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229769447 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 134535 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.025168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 67858.667159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67858.667159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 65281995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65281995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.006623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006623 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 73268.232323 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73268.232323 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 518 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 518 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 520 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 520 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.003846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 176500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.003846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 88250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 27 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 27 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 55 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 55 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1711973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 82 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.670732 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31126.781818 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 55 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1656973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.670732 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30126.781818 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 252 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 278000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.059701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 262000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059701 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 454.875030 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 336606 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 219.430248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 454.875030 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.888428 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 680902 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 680902 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 468934500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 468934500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/calculix/beampic.log b/test_run/calculix/beampic.log new file mode 100644 index 000000000..f2915065d --- /dev/null +++ b/test_run/calculix/beampic.log @@ -0,0 +1,2 @@ + *ERROR in openfile: input file /data/ref/input/hyperviscoplastic.inp.inp + does not exist diff --git a/test_run/calculix/config.ini b/test_run/calculix/config.ini new file mode 100644 index 000000000..506cf2d0f --- /dev/null +++ b/test_run/calculix/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross -i /data/ref/input/hyperviscoplastic.inp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/454.calculix//exe/calculix_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=beampic.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/calculix/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys 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+type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/calculix/config.json b/test_run/calculix/config.json new file mode 100644 index 000000000..c154a9fe2 --- /dev/null +++ b/test_run/calculix/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + 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"IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/calculix/fs/proc/cpuinfo b/test_run/calculix/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/calculix/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/calculix/fs/proc/stat b/test_run/calculix/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/calculix/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/calculix/fs/sys/devices/system/cpu/online b/test_run/calculix/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/calculix/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/calculix/fs/sys/devices/system/cpu/possible b/test_run/calculix/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/calculix/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/calculix/stats.txt b/test_run/calculix/stats.txt new file mode 100644 index 000000000..415159023 --- /dev/null +++ b/test_run/calculix/stats.txt @@ -0,0 +1,1359 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 56861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 80766 # Simulator instruction rate (inst/s) +host_mem_usage 856900 # Number of bytes of host memory used +host_op_rate 97588 # Simulator op (including micro ops) rate (op/s) +host_seconds 0.29 # Real time elapsed on the host +host_tick_rate 195027731 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 23532 # Number of instructions simulated +sim_ops 28450 # Number of ops (including micro ops) simulated +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56861000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.498652 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 3688 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4821 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1286 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8019 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 34 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 465 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 431 # Number of indirect misses. +system.cpu.branchPred.lookups 11185 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 2360 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 1810 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 2273 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 1897 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 21 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 124 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 31 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 14 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 6 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 15 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 112 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 1 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 37 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 2916 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 558 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 93 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 66 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 3 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 15 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 347 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 15 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 17 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 859 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 8625 # number of cc regfile reads +system.cpu.cc_regfile_writes 8679 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 834 # The number of times a branch was mispredicted +system.cpu.commit.branches 5605 # Number of branches committed +system.cpu.commit.bw_lim_events 1239 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 54 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 13539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 23588 # Number of instructions committed +system.cpu.commit.committedOps 28506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 39891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.714597 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.779156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30973 77.64% 77.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3276 8.21% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1731 4.34% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 879 2.20% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 598 1.50% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 551 1.38% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 436 1.09% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208 0.52% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1239 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39891 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 490 # Number of function calls committed. +system.cpu.commit.int_insts 25886 # Number of committed integer instructions. +system.cpu.commit.loads 4020 # Number of loads committed +system.cpu.commit.membars 36 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 7 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 19666 68.99% 69.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 42 0.15% 69.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.01% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 26 0.09% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.26% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 26 0.09% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 28 0.10% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 30 0.11% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 4020 14.10% 83.66% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4658 16.34% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 28506 # Class of committed instruction +system.cpu.commit.refs 8678 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 413 # Number of committed Vector instructions. +system.cpu.committedInsts 23532 # Number of Instructions Simulated +system.cpu.committedOps 28450 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 4.832696 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.832696 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 13004 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 460 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 3802 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 47302 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 19734 # Number of cycles decode is idle +system.cpu.decode.RunCycles 7777 # Number of cycles decode is running +system.cpu.decode.SquashCycles 869 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1546 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 710 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 11185 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6474 # Number of cache lines fetched +system.cpu.fetch.Cycles 17733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 47366 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2642 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.098353 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22801 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4581 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.416503 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 42094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.317646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.646455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 31882 75.74% 75.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1052 2.50% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1015 2.41% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 717 1.70% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1034 2.46% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 731 1.74% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1010 2.40% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 843 2.00% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3810 9.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 42094 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 71629 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 997 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 6864 # Number of branches executed +system.cpu.iew.exec_nop 122 # number of nop insts executed +system.cpu.iew.exec_rate 0.326908 # Inst execution rate +system.cpu.iew.exec_refs 11357 # number of memory reference insts executed +system.cpu.iew.exec_stores 5453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2304 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 6339 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 89 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6321 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 42090 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 5904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1114 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 37177 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 869 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1371 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 86 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1663 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 188 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 31510 # num instructions consuming a value +system.cpu.iew.wb_count 35773 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.563504 # average fanout of values written-back +system.cpu.iew.wb_producers 17756 # num instructions producing a value +system.cpu.iew.wb_rate 0.314563 # insts written-back per cycle +system.cpu.iew.wb_sent 36351 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 41177 # number of integer regfile reads +system.cpu.int_regfile_writes 25395 # number of integer regfile writes +system.cpu.ipc 0.206924 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.206924 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 8 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 26234 68.51% 68.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.11% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.01% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 28 0.07% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.07% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 32 0.08% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.09% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 6191 16.17% 85.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5691 14.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 38291 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 555 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189 34.05% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.18% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.36% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 34.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 118 21.26% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 245 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 38309 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 118302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 35311 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 54736 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 41879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 38291 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13517 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 42094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.909655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29929 71.10% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2997 7.12% 78.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2546 6.05% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2071 4.92% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1657 3.94% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1133 2.69% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 951 2.26% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 490 1.16% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 320 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42094 # Number of insts issued each cycle +system.cpu.iq.rate 0.336704 # Inst issue rate +system.cpu.iq.vec_alu_accesses 529 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1074 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 462 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 769 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 6339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6321 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 28736 # number of misc regfile reads +system.cpu.misc_regfile_writes 145 # number of misc regfile writes +system.cpu.numCycles 113723 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3701 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 26781 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 202 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 20563 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 64176 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 44669 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 42396 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 7626 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 751 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 869 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1430 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 15615 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 49589 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 7905 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 302 # count of serializing insts renamed +system.cpu.rename.skidInsts 3721 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 688 # Number of vector rename lookups +system.cpu.rob.rob_reads 80411 # The number of ROB reads +system.cpu.rob.rob_writes 86307 # The number of ROB writes +system.cpu.timesIdled 663 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 512 # number of vector regfile reads +system.cpu.vec_regfile_writes 137 # number of vector regfile writes +system.cpu.workload.numSyscalls 17 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1251 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 502 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 1817 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1026 # Transaction distribution +system.membus.trans_dist::ReadExReq 168 # Transaction distribution +system.membus.trans_dist::ReadExResp 168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1027 # Transaction distribution +system.membus.trans_dist::InvalidateReq 56 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2445 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1251 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1251 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1251 # Request fanout histogram +system.membus.reqLayer0.occupancy 1533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 6321500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1089 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 27 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 440 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 33 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 171 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 171 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 925 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 165 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 56 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 56 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2289 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 844 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 3133 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 87296 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 23232 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 110528 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001519 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.038954 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1315 99.85% 99.85% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.15% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 1375500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 532000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1386000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 42 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 66 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 42 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 66 # number of overall hits +system.l2.demand_misses::.cpu.inst 883 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 312 # number of demand (read+write) misses +system.l2.demand_misses::total 1195 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 883 # number of overall misses +system.l2.overall_misses::.cpu.data 312 # number of overall misses +system.l2.overall_misses::total 1195 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 68520500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 25782500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 94303000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 68520500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 25782500 # number of overall miss cycles +system.l2.overall_miss_latency::total 94303000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 925 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 336 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1261 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 925 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 336 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1261 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.954595 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.928571 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.947661 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.954595 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.928571 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.947661 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77599.660249 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 82636.217949 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78914.644351 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 883 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 312 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1195 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 883 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 312 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1195 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 59700500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 22662500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 82363000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 59700500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 22662500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 82363000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.947661 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.928571 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.947661 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 72636.217949 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68923.012552 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 27 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 27 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 27 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 440 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 440 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 440 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 440 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 3 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 3 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 168 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 168 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 13366000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 171 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.982456 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79559.523810 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 168 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 11686000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.982456 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69559.523810 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 42 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 883 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 68520500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 925 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.954595 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77599.660249 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 59700500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.954595 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67610.985277 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 144 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12416500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 165 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.872727 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86225.694444 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 144 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10976500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.872727 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76225.694444 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 56 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 56 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 56 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 56 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1064000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19000 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19000 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 638.816237 # Cycle average of tags in use +system.l2.tags.total_refs 1760 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1196 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.471572 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 0.787737 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 434.030626 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 203.997874 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000024 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013246 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.006226 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.019495 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1196 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1019 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.036499 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 15732 # Number of tag accesses +system.l2.tags.data_accesses 15732 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 56448 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 19968 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 76416 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 56448 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 882 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 312 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1194 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 992736674 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 351172157 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1343908830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 992736674 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 992736674 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 351172157 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1343908830 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 883.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 312.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000542000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2358 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1195 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1195 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 126 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 95 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 91 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 75 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.77 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10859000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 5975000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 33265250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9087.03 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27837.03 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 963 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.59 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1195 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 132 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 225 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 336.213333 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 219.600202 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.995257 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 57 25.33% 25.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 62 27.56% 52.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 32 14.22% 67.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 7.56% 74.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 4.44% 79.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 15 6.67% 85.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.67% 88.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 3.56% 92.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 18 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 225 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 76480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 76480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1345.03 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1345.03 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 10.51 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.51 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 56833500 # Total gap between requests +system.mem_ctrls.avgGap 47559.41 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 56512 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 19968 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 993862225.426918268204 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 351172156.662738919258 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 883 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 312 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 23476250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 9789000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26586.92 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 31375.00 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 849660 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4448220 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 24871380 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 890400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 35806155 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 629.713776 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 2123000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 52918000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 806820 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 4076940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 25828980 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 84000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 35509080 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 624.489193 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 11500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 55029500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 5295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 5295 # number of overall hits +system.cpu.icache.overall_hits::total 5295 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1177 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1177 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1177 # number of overall misses +system.cpu.icache.overall_misses::total 1177 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 86127996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86127996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 86127996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86127996 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 6472 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6472 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 6472 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6472 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.181860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.181860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.181860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.181860 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 73175.867460 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73175.867460 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1005 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 440 # number of writebacks +system.cpu.icache.writebacks::total 440 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 252 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 252 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 925 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 925 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 70369497 # number of demand (read+write) MSHR miss cycles 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mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76075.131892 # average overall mshr miss latency +system.cpu.icache.replacements 440 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5295 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1177 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86127996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 6472 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6472 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.181860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.181860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 73175.867460 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73175.867460 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 252 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 70369497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70369497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.142923 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142923 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 76075.131892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76075.131892 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 317.135421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6219 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 924 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.730519 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 317.135421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.619405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13868 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13868 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 8767 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 8767 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 8789 # number of overall hits +system.cpu.dcache.overall_hits::total 8789 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1306 # number of overall misses +system.cpu.dcache.overall_misses::total 1306 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 85332929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85332929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 85332929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85332929 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 10069 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 10069 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 10095 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 10095 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.129308 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129308 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.129371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129371 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 65539.884025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65539.884025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 65339.149311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65339.149311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3235 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.010204 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 27 # number of writebacks +system.cpu.dcache.writebacks::total 27 # number of writebacks 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overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28171467 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038435 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038732 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71753.144703 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71753.144703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 72049.787724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72049.787724 # average overall mshr miss latency +system.cpu.dcache.replacements 60 # number of replacements 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average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12382500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029417 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77390.625000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3725 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 854 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56857956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4579 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66578.402810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13812994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.038436 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78482.920455 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 22 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.153846 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 403000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 100750 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 51 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1623973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 51 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31842.607843 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 51 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1572973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30842.607843 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 47 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040816 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 103000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 103000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 36 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 36 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 223.007274 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 9264 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.632653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 223.007274 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.435561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 332 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.648438 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 20752 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 20752 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 56861000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 56861000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/dealII/config.ini b/test_run/dealII/config.ini new file mode 100644 index 000000000..31f47a569 --- /dev/null +++ b/test_run/dealII/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=65536 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=65536 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=65536 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc 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+children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross 8 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/447.dealII//exe/dealII_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=4194304 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=4194304 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=4194304 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/dealII/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/dealII/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/dealII/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/dealII/config.json b/test_run/dealII/config.json new file mode 100644 index 000000000..3c4246bf7 --- /dev/null +++ b/test_run/dealII/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/dealII/fs/proc/cpuinfo b/test_run/dealII/fs/proc/cpuinfo new file mode 100644 index 000000000..e0e43ef09 --- /dev/null +++ b/test_run/dealII/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 4096K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/dealII/fs/proc/stat b/test_run/dealII/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/dealII/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/dealII/fs/sys/devices/system/cpu/online b/test_run/dealII/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/dealII/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/dealII/fs/sys/devices/system/cpu/possible b/test_run/dealII/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/dealII/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/dealII/stats.txt b/test_run/dealII/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/games/stats.txt b/test_run/games/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/gamess/config.ini b/test_run/gamess/config.ini new file mode 100644 index 000000000..59ad0a6fe --- /dev/null +++ b/test_run/gamess/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] 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+clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/416.gamess//exe/gamess_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/416.gamess//exe/gamess_base.amd64-armcross +gid=100 +input=exam29.config +kvmInSE=false +maxStackSize=67108864 +output=exam29.output +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/gamess/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/gamess/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/gamess/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/gamess/config.json b/test_run/gamess/config.json new file mode 100644 index 000000000..02fe38417 --- /dev/null +++ b/test_run/gamess/config.json @@ -0,0 +1,1685 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/gamess/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/gamess/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/gamess/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 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13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/gamess/fs/proc/cpuinfo b/test_run/gamess/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/gamess/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/gamess/fs/proc/stat b/test_run/gamess/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/gamess/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/gamess/fs/sys/devices/system/cpu/online b/test_run/gamess/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gamess/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gamess/fs/sys/devices/system/cpu/possible b/test_run/gamess/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gamess/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gamess/stats.txt b/test_run/gamess/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/gobmk/capture.out b/test_run/gobmk/capture.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/gobmk/config.ini b/test_run/gobmk/config.ini new file mode 100644 index 000000000..b82a67a90 --- /dev/null +++ b/test_run/gobmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 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+children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross --quiet --mode gtp +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//data/ref/input/13x13.tst +kvmInSE=false +maxStackSize=67108864 +output=capture.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/gobmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/gobmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/gobmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/gobmk/config.json b/test_run/gobmk/config.json new file mode 100644 index 000000000..42ee9ff54 --- /dev/null +++ b/test_run/gobmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/gobmk/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/gobmk/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/gobmk/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.itb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.itb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "itb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, 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+ "name": "workload", + "cmd": [ + "/home/min/a/ece565/benchspec-2020/CPU2006/445.gobmk//exe/gobmk_base.amd64-armcross", + "--quiet", + "--mode", + "gtp" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "release": "5.1.0", + "output": "capture.out" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "decodeToFetchDelay": 1, + "renameWidth": 8, + "numThreads": 1, + "syscallRetryLatency": 10000, + "squashWidth": 8, + "function_trace": false, + "backComSize": 5, + "decodeToRenameDelay": 1, + "store_set_clear_period": 250000, + "numPhysIntRegs": 256, + "fuPool": { + "name": "fuPool", + "FUList": [ + { + "count": 6, + "opList": [ + { + "opClass": "IntAlu", + "opLat": 1, + "name": "opList", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList0.opList", + "type": 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"system.cpu.dcache.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 32768 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/gobmk/fs/proc/cpuinfo b/test_run/gobmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/gobmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/gobmk/fs/proc/stat b/test_run/gobmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/gobmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/gobmk/fs/sys/devices/system/cpu/online b/test_run/gobmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gobmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gobmk/fs/sys/devices/system/cpu/possible b/test_run/gobmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gobmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gobmk/stats.txt b/test_run/gobmk/stats.txt new file mode 100644 index 000000000..61588d7c3 --- /dev/null +++ b/test_run/gobmk/stats.txt @@ -0,0 +1,1342 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 463966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 146415 # Simulator instruction rate (inst/s) +host_mem_usage 859120 # Number of bytes of host memory used +host_op_rate 146961 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.83 # Real time elapsed on the host +host_tick_rate 67929727 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1003756 # Number of ops (including micro ops) simulated +sim_seconds 0.000464 # Number of seconds simulated +sim_ticks 463966500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.726161 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 173713 # Number of BTB hits +system.cpu.branchPred.BTBLookups 174190 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 844 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 175218 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 134 # Number of indirect misses. +system.cpu.branchPred.lookups 183670 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 9619 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 154197 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 4842 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 158974 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 65 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 763 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 46 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 40 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 275 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 136 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 60 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 145 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 215 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 206 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 128 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 263 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 108 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 116 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 36 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 61 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 62 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 79 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 269 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 10 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 159067 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 285 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 650 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 40 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 64 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 301 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 52 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 248 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 125 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 68 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 212 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 308 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 183 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 270 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 165 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 329 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 36 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 82 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 95 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 3403 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 40 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 100 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2727 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 507132 # number of cc regfile reads +system.cpu.cc_regfile_writes 507438 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 649 # The number of times a branch was mispredicted +system.cpu.commit.branches 171144 # Number of branches committed +system.cpu.commit.bw_lim_events 19230 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 40539 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000213 # Number of instructions committed +system.cpu.commit.committedOps 1003967 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 891530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.126117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.219871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 650701 72.99% 72.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 52797 5.92% 78.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32204 3.61% 82.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21703 2.43% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7692 0.86% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7047 0.79% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99282 11.14% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 874 0.10% 97.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 19230 2.16% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 891530 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2417 # Number of function calls committed. +system.cpu.commit.int_insts 840106 # Number of committed integer instructions. +system.cpu.commit.loads 310680 # Number of loads committed +system.cpu.commit.membars 16 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 4 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 533766 53.17% 53.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 449 0.04% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 19 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 12 0.00% 53.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 16 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 53.22% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 310680 30.95% 84.16% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 159002 15.84% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1003967 # Class of committed instruction +system.cpu.commit.refs 469682 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 248 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1003756 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927932 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927932 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 713461 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 170925 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1055068 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 40149 # Number of cycles decode is idle +system.cpu.decode.RunCycles 102411 # Number of cycles decode is running +system.cpu.decode.SquashCycles 990 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 670 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 40070 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 183670 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 15255 # Number of cache lines fetched +system.cpu.fetch.Cycles 872161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 392 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1072586 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 2370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.197934 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 23707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 176441 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.155886 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 897081 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.201933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.336465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692458 77.19% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4126 0.46% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23115 2.58% 80.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1334 0.15% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25122 2.80% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 897 0.10% 83.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139169 15.51% 98.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2994 0.33% 99.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7866 0.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 897081 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 30853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 729 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 177146 # Number of branches executed +system.cpu.iew.exec_nop 257 # number of nop insts executed +system.cpu.iew.exec_rate 1.156592 # Inst execution rate +system.cpu.iew.exec_refs 519344 # number of memory reference insts executed +system.cpu.iew.exec_stores 164447 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 5056 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 321924 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 164988 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1044518 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 354897 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1073241 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 17069 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 990 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 17094 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8383 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11235 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5981 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 446 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1269546 # num instructions consuming a value +system.cpu.iew.wb_count 1033965 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.530245 # average fanout of values written-back +system.cpu.iew.wb_producers 673170 # num instructions producing a value +system.cpu.iew.wb_rate 1.114266 # insts written-back per cycle +system.cpu.iew.wb_sent 1039294 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1392509 # number of integer regfile reads +system.cpu.int_regfile_writes 700174 # number of integer regfile writes +system.cpu.ipc 1.077665 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077665 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 553864 51.57% 51.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 501 0.05% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 51.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 25 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 16 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 51.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 355062 33.06% 84.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 164583 15.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1074097 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 18272 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017011 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 123 0.67% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18071 98.90% 99.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 75 0.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1092056 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3062983 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1033689 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1084351 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1044228 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1074097 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 40478 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 23290 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 897081 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.197324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 639583 71.30% 71.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 33403 3.72% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24407 2.72% 77.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 35269 3.93% 81.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 51684 5.76% 87.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56013 6.24% 93.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5377 0.60% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43750 4.88% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7595 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 897081 # Number of insts issued each cycle +system.cpu.iq.rate 1.157514 # Inst issue rate +system.cpu.iq.vec_alu_accesses 308 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 619 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 276 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 424 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2492 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2394 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 321924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 164988 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 865847 # number of misc regfile reads +system.cpu.misc_regfile_writes 65 # number of misc regfile writes +system.cpu.numCycles 927934 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23218 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1166751 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 3317 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 60184 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 8163 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1892164 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1047728 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1217345 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 122048 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 674293 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 990 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 686442 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 50538 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1368066 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4199 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.skidInsts 219619 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 409 # Number of vector rename lookups +system.cpu.rob.rob_reads 1912854 # The number of ROB reads +system.cpu.rob.rob_writes 2094604 # The number of ROB writes +system.cpu.timesIdled 311 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 318 # number of vector regfile reads +system.cpu.vec_regfile_writes 92 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 22125 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 21334 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 43517 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 464 # Transaction distribution +system.membus.trans_dist::ReadExReq 18836 # Transaction distribution +system.membus.trans_dist::ReadExResp 18835 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 464 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 41424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 22125 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 22125 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 22125 # Request fanout histogram +system.membus.reqLayer0.occupancy 31087500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 98420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 504 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 21206 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 51 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 77 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 18854 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 18851 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 385 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 119 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2825 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2825 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 821 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 64876 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 65697 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 2571264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2599168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 22183 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000045 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.006714 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 22182 100.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 22183 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 43015500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 9.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 29867500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 577500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 8 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 48 # number of demand (read+write) hits +system.l2.demand_hits::total 56 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 8 # number of overall hits +system.l2.overall_hits::.cpu.data 48 # number of overall hits +system.l2.overall_hits::total 56 # number of overall hits +system.l2.demand_misses::.cpu.inst 377 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 18925 # number of demand (read+write) misses +system.l2.demand_misses::total 19302 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 377 # number of overall misses +system.l2.overall_misses::.cpu.data 18925 # number of overall misses +system.l2.overall_misses::total 19302 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 30084500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1436692500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1466777000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 30084500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1436692500 # number of overall miss cycles +system.l2.overall_miss_latency::total 1466777000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 385 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 18973 # number of demand (read+write) accesses +system.l2.demand_accesses::total 19358 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 385 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 18973 # number of overall (read+write) accesses +system.l2.overall_accesses::total 19358 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.979221 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.997470 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.997107 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.979221 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.997470 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.997107 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79799.734748 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75915.059445 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75990.933582 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 377 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 18925 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 19302 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 377 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 18925 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 19302 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 26314500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1247472500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1273787000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 26314500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1247472500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1273787000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.997107 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.997470 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.997107 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65916.644650 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65992.487825 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 21206 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 21206 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 51 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 51 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 51 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 51 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 16 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 16 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 18838 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 18838 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1428903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 18854 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999151 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75852.160527 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 18838 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1240553000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999151 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65853.753052 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 377 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 30084500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 385 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.979221 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79799.734748 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 377 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 26314500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.979221 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69799.734748 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 7789500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 119 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.731092 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 89534.482759 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 6919500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.731092 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 79534.482759 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2825 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2825 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2825 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 54259000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19206.725664 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19206.725664 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 11222.269262 # Cycle average of tags in use +system.l2.tags.total_refs 40688 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 22124 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.839089 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 2583.087120 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 362.014998 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 8277.167144 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.078830 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.011048 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.252599 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.342476 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 22124 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 472 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4203 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 17449 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.675171 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 370252 # Number of tag accesses +system.l2.tags.data_accesses 370252 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 24128 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1211008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1235136 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 24128 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 377 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 18922 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 19299 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 52003755 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2610119481 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2662123235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 52003755 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 52003755 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2610119481 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2662123235 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 377.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 18923.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000585000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 38666 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 19300 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 19300 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1250 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1163 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1166 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1206 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1234 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.19 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 115628000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 96500000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 477503000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5991.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24741.09 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 17926 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 19300 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5032 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 4929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 5539 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 3792 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an 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does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 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+system.mem_ctrls.bytesPerActivate::512-639 33 2.40% 14.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 0.44% 15.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 25 1.82% 16.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 0.44% 17.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1134 82.59% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1373 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1235200 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1235200 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2662.26 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2662.26 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 20.80 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 20.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 463952000 # Total gap between requests +system.mem_ctrls.avgGap 24038.96 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 24128 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1211072 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 52003754.581419132650 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2610257421.602637290955 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 377 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 18923 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 10808750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 466694250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28670.42 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24662.80 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 92.88 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 5069400 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2690655 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 70093380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 117849210 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 78922080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 310888485 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 670.066664 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 200539250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 248087250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 4740960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 2519880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 67701480 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 110516730 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 85096800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 306839610 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 661.340011 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 216684000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 231942500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 14752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 14752 # number of overall hits +system.cpu.icache.overall_hits::total 14752 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 503 # number of overall misses +system.cpu.icache.overall_misses::total 503 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 38236998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38236998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 38236998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38236998 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 15255 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15255 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 15255 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15255 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.032973 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032973 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.032973 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032973 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76017.888668 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76017.888668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76017.888668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76017.888668 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 51 # number of writebacks +system.cpu.icache.writebacks::total 51 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 118 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 385 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 385 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 385 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 385 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30755499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 30755499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30755499 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.025238 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.025238 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79884.412987 # average overall mshr miss latency +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14752 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38236998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15255 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032973 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76017.888668 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 385 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30755499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.025238 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79884.412987 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 322.204782 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15137 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 385 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39.316883 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 322.204782 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.629306 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.629306 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30895 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 326918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 326918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 326923 # number of overall hits +system.cpu.dcache.overall_hits::total 326923 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 152895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 152895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 152897 # number of overall misses +system.cpu.dcache.overall_misses::total 152897 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 9649773141 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9649773141 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 9649773141 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9649773141 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 479813 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 479813 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 479820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 479820 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.318655 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.318655 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.318655 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.318655 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 63113.726028 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63113.726028 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 63112.900456 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63112.900456 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 622929 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8721 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.428621 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 21206 # number of writebacks +system.cpu.dcache.writebacks::total 21206 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 131099 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 131099 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 131099 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 131099 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 21796 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 21796 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 21798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 21798 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 1557818510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1557818510 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 1558017510 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1558017510 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.045426 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.045426 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.045430 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.045430 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 71472.678932 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71472.678932 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 71475.250482 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71475.250482 # average overall mshr miss latency +system.cpu.dcache.replacements 21283 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 320485 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 320827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51133.040936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 117 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000365 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69376.068376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6433 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 149730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 149730 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 9539526625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9539526625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 156163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.958806 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.958806 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63711.524912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 130874 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18856 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1459765494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77416.498409 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 7 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.285714 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 199000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 99500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2823 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 92759016 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2823 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32858.312434 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2823 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 89936016 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31858.312434 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 16 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 16 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 492.463211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 21795 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.001468 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 492.463211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.961842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 981503 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 981503 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 463966500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 463966500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/gromacs/config.ini b/test_run/gromacs/config.ini new file mode 100644 index 000000000..3217bb58b --- /dev/null +++ b/test_run/gromacs/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] 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CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/435.gromacs/435.gromacs//exe/gromacs_base.amd64-armcross -silent -deffnm /home/min/a/ece565/benchspec-2020/CPU2006/435.gromacs//data/ref/input/gromacs.tpr -nice 0 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/435.gromacs/435.gromacs//exe/gromacs_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=cout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false 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+[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 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+system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/gromacs/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/gromacs/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/gromacs/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 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+ "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/gromacs/fs/proc/cpuinfo b/test_run/gromacs/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/gromacs/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/gromacs/fs/proc/stat b/test_run/gromacs/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/gromacs/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/gromacs/fs/sys/devices/system/cpu/online b/test_run/gromacs/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gromacs/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gromacs/fs/sys/devices/system/cpu/possible b/test_run/gromacs/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/gromacs/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/gromacs/stats.txt b/test_run/gromacs/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/h264ref/config.ini b/test_run/h264ref/config.ini new file mode 100644 index 000000000..fc1c952fe --- /dev/null +++ b/test_run/h264ref/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] 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+clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 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+power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run/h264ref_base.amd64-armcross -d /home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//data/ref/input/foreman_ref_encoder_baseline.cfg +cwd=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/464.h264ref//run/h264ref_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=foreman_ref_encoder_baseline.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/h264ref/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/h264ref/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/h264ref/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/h264ref/config.json b/test_run/h264ref/config.json new file mode 100644 index 000000000..308782e92 --- /dev/null +++ b/test_run/h264ref/config.json @@ -0,0 +1,1812 @@ +{ + "name": null, + "sim_quantum": 0, + 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"write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/h264ref/foreman_ref_encoder_baseline.out b/test_run/h264ref/foreman_ref_encoder_baseline.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/h264ref/fs/proc/cpuinfo b/test_run/h264ref/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/h264ref/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/h264ref/fs/proc/stat b/test_run/h264ref/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/h264ref/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/h264ref/fs/sys/devices/system/cpu/online b/test_run/h264ref/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/h264ref/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/h264ref/fs/sys/devices/system/cpu/possible b/test_run/h264ref/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/h264ref/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/h264ref/stats.txt b/test_run/h264ref/stats.txt new file mode 100644 index 000000000..856e8e82f --- /dev/null +++ b/test_run/h264ref/stats.txt @@ -0,0 +1,1366 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 427446500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 161665 # Simulator instruction rate (inst/s) +host_mem_usage 854568 # Number of bytes of host memory used +host_op_rate 184640 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.19 # Real time elapsed on the host +host_tick_rate 69101033 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1142145 # Number of ops (including micro ops) simulated +sim_seconds 0.000427 # Number of seconds simulated +sim_ticks 427446500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.575075 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 121359 # Number of BTB hits +system.cpu.branchPred.BTBLookups 124375 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4313 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 198147 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 655 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1283 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 628 # Number of indirect misses. +system.cpu.branchPred.lookups 250887 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 125414 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 53109 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 101135 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 77388 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 271 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 59 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 13501 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2840 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3207 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1792 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2768 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 748 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 2375 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 3991 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 7442 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1519 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 2239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 914 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 2020 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1730 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1065 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1307 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1097 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1285 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1233 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1910 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1197 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 167 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 370 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 120104 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 828 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 553 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3993 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8056 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 4579 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 824 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3601 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3076 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1884 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2406 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 7039 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 2146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1665 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 2144 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 951 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1108 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1599 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1503 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1304 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1331 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 2041 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 54083 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 181 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1074 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 13605 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 105 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 379872 # number of cc regfile reads +system.cpu.cc_regfile_writes 372672 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3271 # The number of times a branch was mispredicted +system.cpu.commit.branches 224913 # Number of branches committed +system.cpu.commit.bw_lim_events 50758 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 252 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 56194 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1003095 # Number of instructions committed +system.cpu.commit.committedOps 1145240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 770738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.485901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.369664 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 426603 55.35% 55.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116834 15.16% 70.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 67596 8.77% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 39515 5.13% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22580 2.93% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13536 1.76% 89.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22607 2.93% 92.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10709 1.39% 93.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50758 6.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770738 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 12624 # Number of function calls committed. +system.cpu.commit.int_insts 1024481 # Number of committed integer instructions. +system.cpu.commit.loads 150860 # Number of loads committed +system.cpu.commit.membars 232 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 6 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 863752 75.42% 75.42% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5029 0.44% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 5 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 9 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 9 0.00% 75.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 376 0.03% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 22 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 22 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 24 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 245 0.02% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 75.92% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 150860 13.17% 89.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 124880 10.90% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1145240 # Class of committed instruction +system.cpu.commit.refs 275740 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 8879 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1142145 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.854894 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.854894 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 368509 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1137 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 119986 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1224547 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 178045 # Number of cycles decode is idle +system.cpu.decode.RunCycles 216792 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3386 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3609 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 12829 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 250887 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 171510 # Number of cache lines fetched +system.cpu.fetch.Cycles 561356 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1099130 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 489 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 9018 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.293471 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 212929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 135619 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.285692 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 779561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.607915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.731971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 528636 67.81% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27113 3.48% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36295 4.66% 75.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 12254 1.57% 77.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30279 3.88% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 37573 4.82% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11082 1.42% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29102 3.73% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 67227 8.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 779561 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 75333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3610 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 232462 # Number of branches executed +system.cpu.iew.exec_nop 3256 # number of nop insts executed +system.cpu.iew.exec_rate 1.385596 # Inst execution rate +system.cpu.iew.exec_refs 290276 # number of memory reference insts executed +system.cpu.iew.exec_stores 128324 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 16400 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 159345 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 373 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 825 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 130179 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1202599 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 161952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5071 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1184538 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 11293 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3386 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11568 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 2527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 6347 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1197 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 8480 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5299 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1314 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1108752 # num instructions consuming a value +system.cpu.iew.wb_count 1175456 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.594385 # average fanout of values written-back +system.cpu.iew.wb_producers 659026 # num instructions producing a value +system.cpu.iew.wb_rate 1.374973 # insts written-back per cycle +system.cpu.iew.wb_sent 1177494 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1320787 # number of integer regfile reads +system.cpu.int_regfile_writes 841620 # number of integer regfile writes +system.cpu.ipc 1.169736 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169736 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 87 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 891253 74.92% 74.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5132 0.43% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 15 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 9 0.00% 75.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 505 0.04% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 24 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 75.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 280 0.02% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 75.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163357 13.73% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 128886 10.83% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1189612 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 14157 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5654 39.94% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.01% 39.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 39.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1451 10.25% 50.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7049 49.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1192014 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3151220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1165962 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1244261 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1198970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1189612 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 373 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 57189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 671 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 43243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 779561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.526002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.034822 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 391506 50.22% 50.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101942 13.08% 63.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 84279 10.81% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59290 7.61% 81.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54793 7.03% 88.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35615 4.57% 93.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31539 4.05% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10015 1.28% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10582 1.36% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 779561 # Number of insts issued each cycle +system.cpu.iq.rate 1.391532 # Inst issue rate +system.cpu.iq.vec_alu_accesses 11668 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 22390 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 9494 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 12293 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 3440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3163 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 159345 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 130179 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 800526 # number of misc regfile reads +system.cpu.misc_regfile_writes 1323 # number of misc regfile writes +system.cpu.numCycles 854894 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 28940 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1176670 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1971 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 184460 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2889 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1821783 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1215369 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1258811 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 222802 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 53928 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3386 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 65271 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 82118 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1347675 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 274702 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5780 # count of serializing insts renamed +system.cpu.rename.skidInsts 55715 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 370 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 9913 # Number of vector rename lookups +system.cpu.rob.rob_reads 1920192 # The number of ROB reads +system.cpu.rob.rob_writes 2411737 # The number of ROB writes +system.cpu.timesIdled 1270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 8786 # number of vector regfile reads +system.cpu.vec_regfile_writes 924 # number of vector regfile writes +system.cpu.workload.numSyscalls 19 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6119 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 7306 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 15623 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1472 # Transaction distribution +system.membus.trans_dist::ReadExReq 2056 # Transaction distribution +system.membus.trans_dist::ReadExResp 2056 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1472 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2591 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 9647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9647 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 225792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 225792 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 6119 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6119 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6119 # Request fanout histogram +system.membus.reqLayer0.occupancy 7296500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 18591250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.3 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3350 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4967 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1538 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 801 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2132 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2131 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2036 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1314 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2835 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2835 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 5610 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 18329 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 23939 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 228736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 538368 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 767104 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 8317 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000120 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.010965 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 8316 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 8317 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 14316500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 6585499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3054499 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1095 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 858 # number of demand (read+write) hits +system.l2.demand_hits::total 1953 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1095 # number of overall hits +system.l2.overall_hits::.cpu.data 858 # number of overall hits +system.l2.overall_hits::total 1953 # number of overall hits +system.l2.demand_misses::.cpu.inst 941 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2588 # number of demand (read+write) misses +system.l2.demand_misses::total 3529 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 941 # number of overall misses +system.l2.overall_misses::.cpu.data 2588 # number of overall misses +system.l2.overall_misses::total 3529 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 73969000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 198318000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 272287000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 73969000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 198318000 # number of overall miss cycles +system.l2.overall_miss_latency::total 272287000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2036 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 3446 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5482 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2036 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 3446 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5482 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.462181 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.751016 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.643743 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.462181 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.751016 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.643743 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78606.801275 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 76629.829985 # average overall miss latency +system.l2.demand_avg_miss_latency::total 77156.984982 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78606.801275 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 76629.829985 # average overall miss latency +system.l2.overall_avg_miss_latency::total 77156.984982 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 941 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2588 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3529 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 941 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2588 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3529 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 64559000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 172447501 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 237006501 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 64559000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 172447501 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 237006501 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.751016 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.643743 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.751016 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.643743 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 66633.501159 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 67159.677246 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 66633.501159 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 67159.677246 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 4967 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 4967 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 4967 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 4967 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1538 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1538 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1538 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1538 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 75 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 75 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 2057 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2057 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 155434500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 155434500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2132 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2132 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.964822 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.964822 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75563.684978 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75563.684978 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2057 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2057 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 134874001 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 134874001 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.964822 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.964822 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65568.303841 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65568.303841 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1095 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1095 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 941 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 941 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 73969000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 73969000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2036 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2036 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.462181 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.462181 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78606.801275 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78606.801275 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 941 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 941 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 64559000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 64559000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.462181 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.462181 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68606.801275 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68606.801275 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 783 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 783 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 42883500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 42883500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1314 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1314 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.404110 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.404110 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80759.887006 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80759.887006 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37573500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37573500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.404110 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.404110 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70759.887006 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70759.887006 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 244 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 244 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 2591 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2591 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2835 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2835 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.913933 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.913933 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2591 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2591 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 49882500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 49882500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.913933 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.913933 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19252.219220 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19252.219220 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3445.376602 # Cycle average of tags in use +system.l2.tags.total_refs 13030 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 6363 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.047776 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1510.581900 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 802.458021 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1132.336680 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.046099 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.024489 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.034556 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.105145 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 6119 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 612 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 5439 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.186737 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 131339 # Number of tag accesses +system.l2.tags.data_accesses 131339 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts 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bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 140892486 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 140892486 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 140892486 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 387342042 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 528234528 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 941.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2587.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000580000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 7098 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3528 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 3528 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 235 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 318 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 169 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 236 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 284 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 142 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 146 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 259 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 208 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 252 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 25715500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 17640000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 91865500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 7288.97 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26038.97 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 3062 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.79 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3528 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2460 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 714 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 245 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 91 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 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+system.mem_ctrls.bytesPerActivate::512-639 18 3.87% 62.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 18 3.87% 66.02% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 14 3.01% 69.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 1.51% 70.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 137 29.46% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 465 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 225792 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 225792 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 528.23 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 528.23 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.13 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 427332000 # Total gap between requests +system.mem_ctrls.avgGap 121125.85 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 60224 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 165568 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 140892485.960231274366 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 387342041.635619878769 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 941 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2587 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 25845750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 66019750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27466.26 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 25519.81 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 86.79 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1449420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 770385 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 12109440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 126533160 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 57585600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 231638565 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 541.912415 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 148059250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 265347250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1877820 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 994290 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 13080480 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 81271740 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 95700480 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 226115370 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 528.991043 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 247772000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 165634500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 169215 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 169215 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 169215 # number of overall hits +system.cpu.icache.overall_hits::total 169215 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2293 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2293 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2293 # number of overall misses +system.cpu.icache.overall_misses::total 2293 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 104755998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 104755998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 104755998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 104755998 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 171508 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 171508 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 171508 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 171508 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.013370 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013370 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.013370 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013370 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 45685.127780 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45685.127780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 45685.127780 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45685.127780 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1607 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.958333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1538 # number of writebacks +system.cpu.icache.writebacks::total 1538 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 257 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 257 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 257 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 257 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 2036 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2036 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 2036 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2036 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88649498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88649498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88649498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88649498 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.011871 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.011871 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.011871 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.011871 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 43541.010806 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43541.010806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 43541.010806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43541.010806 # average overall mshr miss latency +system.cpu.icache.replacements 1538 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 169215 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 169215 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 2293 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2293 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 104755998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 104755998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 171508 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 171508 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.013370 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013370 # miss rate for ReadReq accesses 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43541.010806 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 465.809207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 171251 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2036 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 84.111493 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 465.809207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.909784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909784 # Average percentage of cache occupancy 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Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 257906 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 257906 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 257925 # number of overall hits +system.cpu.dcache.overall_hits::total 257925 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 17545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 17547 # number of overall misses +system.cpu.dcache.overall_misses::total 17547 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 954383136 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 954383136 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 954383136 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 954383136 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 275451 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 275451 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 275472 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 275472 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.063696 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.063696 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.063698 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.063698 # miss rate for overall accesses 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writebacks +system.cpu.dcache.writebacks::total 4967 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 11268 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 11268 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 11268 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 11268 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6277 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6277 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 6279 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 6279 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 297627965 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297627965 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 297812965 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297812965 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.022788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.022788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.022794 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.022794 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 47415.638840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47415.638840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 47429.999204 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47429.999204 # average overall mshr miss latency +system.cpu.dcache.replacements 5768 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 147681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147681 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3117 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 129376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 129376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 150798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 150798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.020670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020670 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 41506.737247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.737247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 1806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1311 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1311 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 52921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.008694 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008694 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 40367.276888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40367.276888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 110145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 110145 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 11747 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11747 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 741676646 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 741676646 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 121892 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 121892 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.096372 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.096372 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63137.536903 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63137.536903 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 9462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 2285 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2285 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 164057475 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 164057475 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 71797.582057 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71797.582057 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 19 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 19 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 21 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 21 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.095238 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.095238 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.095238 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.095238 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 80 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 80 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 2681 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 2681 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 83329990 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 83329990 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 2761 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 2761 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.971025 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.971025 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31081.682208 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31081.682208 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 2681 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 2681 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 80648990 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 80648990 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.971025 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.971025 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30081.682208 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30081.682208 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 200000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 200000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 244 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 244 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 50000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 50000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.008197 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008197 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 55750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 478.577533 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 264677 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6280 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 42.146019 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 478.577533 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.934722 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.934722 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 558176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 558176 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 427446500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 427446500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/hmmer/bombesin.out b/test_run/hmmer/bombesin.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/hmmer/config.ini b/test_run/hmmer/config.ini new file mode 100644 index 000000000..e74a701f1 --- /dev/null +++ b/test_run/hmmer/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + 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+clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross --fixed 0 --mean 325 --num 5000 --sd 200 --seed 0 /home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//data/ref/input/nph3.hmm +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=bombesin.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/hmmer/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/hmmer/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/hmmer/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/hmmer/config.json b/test_run/hmmer/config.json new file mode 100644 index 000000000..de4a881c1 --- /dev/null +++ b/test_run/hmmer/config.json @@ -0,0 +1,1821 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + 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"cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/hmmer/fs/proc/cpuinfo b/test_run/hmmer/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/hmmer/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/hmmer/fs/proc/stat b/test_run/hmmer/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/hmmer/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/hmmer/fs/sys/devices/system/cpu/online b/test_run/hmmer/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/hmmer/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/hmmer/fs/sys/devices/system/cpu/possible b/test_run/hmmer/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/hmmer/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/hmmer/stats.txt b/test_run/hmmer/stats.txt new file mode 100644 index 000000000..dd55eb4c0 --- /dev/null +++ b/test_run/hmmer/stats.txt @@ -0,0 +1,1345 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 371151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 132778 # Simulator instruction rate (inst/s) +host_mem_usage 855436 # Number of bytes of host memory used +host_op_rate 169297 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.53 # Real time elapsed on the host +host_tick_rate 49279451 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1275067 # Number of ops (including micro ops) simulated +sim_seconds 0.000371 # Number of seconds simulated +sim_ticks 371151000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.606810 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 134690 # Number of BTB hits +system.cpu.branchPred.BTBLookups 136593 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7055 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 204306 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 469 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1143 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 674 # Number of indirect misses. +system.cpu.branchPred.lookups 261150 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 95555 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 56119 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 89830 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61844 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 277 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 66 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 11001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2901 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 666 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 346 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 6942 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1667 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1558 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 892 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1613 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 838 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1380 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1120 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 769 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1940 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2365 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1862 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 1343 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2169 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 355 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1232 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 102898 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1036 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1952 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 472 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 6800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 7412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1147 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1856 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1332 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1037 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1444 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1142 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1280 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1072 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1398 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1571 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1970 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1994 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 2018 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 3065 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39731 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 649 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 2829 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 19178 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 172 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 299295 # number of cc regfile reads +system.cpu.cc_regfile_writes 276253 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6404 # The number of times a branch was mispredicted +system.cpu.commit.branches 199789 # Number of branches committed +system.cpu.commit.bw_lim_events 86134 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 405 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 214441 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002214 # Number of instructions committed +system.cpu.commit.committedOps 1277279 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 626626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038343 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.814350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301756 48.16% 48.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 90275 14.41% 62.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51837 8.27% 70.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 43017 6.86% 77.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25180 4.02% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 11065 1.77% 83.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 12372 1.97% 85.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4990 0.80% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 86134 13.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 626626 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 15547 # Number of function calls committed. +system.cpu.commit.int_insts 1131445 # Number of committed integer instructions. +system.cpu.commit.loads 187072 # Number of loads committed +system.cpu.commit.membars 384 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 861 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756222 59.21% 59.27% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7535 0.59% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 23 0.00% 59.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2196 0.17% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 10982 0.86% 60.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 10950 0.86% 61.75% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 15330 1.20% 62.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 2212 0.17% 63.13% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 16014 1.25% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.38% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1597 0.13% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 2100 0.16% 64.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 2000 0.16% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.83% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 3853 0.30% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 65.13% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 187072 14.65% 79.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 258328 20.22% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1277279 # Class of committed instruction +system.cpu.commit.refs 445400 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 96081 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1275067 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.742302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.742302 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 239022 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 662 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 131096 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1597574 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 141803 # Number of cycles decode is idle +system.cpu.decode.RunCycles 249035 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6496 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2505 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 20755 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 261150 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 157977 # Number of cache lines fetched +system.cpu.fetch.Cycles 467292 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2017 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1344580 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14294 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.351811 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 182557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 154337 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.811363 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 657111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.521428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.140176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 348325 53.01% 53.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23632 3.60% 56.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27656 4.21% 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30837 4.69% 65.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 31384 4.78% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30870 4.70% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 47784 7.27% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 14171 2.16% 84.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102452 15.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 657111 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 85192 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 11895 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 212923 # Number of branches executed +system.cpu.iew.exec_nop 2687 # number of nop insts executed +system.cpu.iew.exec_rate 1.861834 # Inst execution rate +system.cpu.iew.exec_refs 480552 # number of memory reference insts executed +system.cpu.iew.exec_stores 266534 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 30022 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 229901 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 453 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 644 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 292791 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1492153 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 214018 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1382045 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 127 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 240 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6496 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 396 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 161 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 297 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 83 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 42824 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 34431 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2505 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 9390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1186513 # num instructions consuming a value +system.cpu.iew.wb_count 1367463 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.568161 # average fanout of values written-back +system.cpu.iew.wb_producers 674131 # num instructions producing a value +system.cpu.iew.wb_rate 1.842190 # insts written-back per cycle +system.cpu.iew.wb_sent 1374742 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1621778 # number of integer regfile reads +system.cpu.int_regfile_writes 838864 # number of integer regfile writes +system.cpu.ipc 1.347161 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.347161 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 998 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829308 59.28% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7609 0.54% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 28 0.00% 59.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2197 0.16% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 4 0.00% 60.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 10983 0.79% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 10950 0.78% 61.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 15330 1.10% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 2212 0.16% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 16097 1.15% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1811 0.13% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 2359 0.17% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2282 0.16% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 4283 0.31% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 219731 15.71% 80.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 272755 19.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1398937 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 43962 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031425 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7219 16.42% 16.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 13 0.03% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 2190 4.98% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 52 0.12% 21.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 62 0.14% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7316 16.64% 38.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 27110 61.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1342253 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3302227 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1269728 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1600011 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1489013 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1398937 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 453 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 214328 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 193555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 657111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.128920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.441391 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278120 42.32% 42.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 72738 11.07% 53.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 50307 7.66% 61.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 80997 12.33% 73.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 55228 8.40% 81.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 38544 5.87% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28076 4.27% 91.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 24302 3.70% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28799 4.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 657111 # Number of insts issued each cycle +system.cpu.iq.rate 1.884590 # Inst issue rate +system.cpu.iq.vec_alu_accesses 99648 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 198960 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 97735 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 103851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1873 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21229 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 229901 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 292791 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1127954 # number of misc regfile reads +system.cpu.misc_regfile_writes 45403 # number of misc regfile writes +system.cpu.numCycles 742303 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 31082 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1164220 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 541 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 153081 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2573258 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1560444 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1380122 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 256102 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 146174 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6496 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 153264 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 215859 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1883723 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 57086 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3503 # count of serializing insts renamed +system.cpu.rename.skidInsts 60035 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 123940 # Number of vector rename lookups +system.cpu.rob.rob_reads 2031718 # The number of ROB reads +system.cpu.rob.rob_writes 3014020 # The number of ROB writes +system.cpu.timesIdled 847 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 120536 # number of vector regfile reads +system.cpu.vec_regfile_writes 92784 # number of vector regfile writes +system.cpu.workload.numSyscalls 20 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1880 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1721 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 4415 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1411 # Transaction distribution +system.membus.trans_dist::ReadExReq 456 # Transaction distribution +system.membus.trans_dist::ReadExResp 456 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1411 # Transaction distribution +system.membus.trans_dist::InvalidateReq 13 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3747 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 119488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1880 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1880 # Request fanout histogram +system.membus.reqLayer0.occupancy 2346500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 9886750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2054 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 580 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 821 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 320 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 467 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 467 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1313 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 741 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 173 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 173 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3447 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 3662 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 7109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 136576 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 114432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 251008 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 2694 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000371 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.019266 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 2693 99.96% 99.96% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.04% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 2694 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 3608500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1898999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1969999 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 245 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 409 # number of demand (read+write) hits +system.l2.demand_hits::total 654 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 245 # number of overall hits +system.l2.overall_hits::.cpu.data 409 # number of overall hits +system.l2.overall_hits::total 654 # number of overall hits +system.l2.demand_misses::.cpu.inst 1068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 799 # number of demand (read+write) misses +system.l2.demand_misses::total 1867 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1068 # number of overall misses +system.l2.overall_misses::.cpu.data 799 # number of overall misses +system.l2.overall_misses::total 1867 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 83627500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 64742000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 148369500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 83627500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 64742000 # number of overall miss cycles +system.l2.overall_miss_latency::total 148369500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1313 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1208 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2521 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1313 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1208 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2521 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.813404 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.661424 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.740579 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.813404 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.661424 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.740579 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78302.902622 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81028.785982 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79469.469738 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 799 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1867 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 799 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1867 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 72947500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 56752000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 129699500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 72947500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 56752000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 129699500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.740579 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.661424 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.740579 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71028.785982 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69469.469738 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 580 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 580 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 580 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 820 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 820 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 820 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 820 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 11 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 11 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 456 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 456 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 36653000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 467 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.976445 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 80379.385965 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 456 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 32093000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.976445 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 70379.385965 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 245 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1068 # number of ReadCleanReq misses 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ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 72947500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.813404 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68302.902622 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 398 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 343 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 28089000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 741 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.462888 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81892.128280 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 343 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 24659000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.462888 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71892.128280 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 160 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 160 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 13 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 13 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 173 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.075145 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 13 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 246500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.075145 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18961.538462 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18961.538462 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1571.392330 # Cycle average of tags in use +system.l2.tags.total_refs 4401 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2036 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.161591 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.498537 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 965.191752 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 599.702041 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000198 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.029455 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.018301 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.047955 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1876 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.057251 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 37348 # Number of tag accesses +system.l2.tags.data_accesses 37348 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 68352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 119488 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 799 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1867 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 184162241 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 137776808 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 321939049 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 184162241 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 184162241 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 137776808 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 321939049 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 799.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000577500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3767 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1867 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1867 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 37 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 28 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 177 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 212 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 180 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 80 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.26 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 17820750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 9335000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 52827000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9545.13 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28295.13 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1446 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 77.45 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1867 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1121 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 532 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 149 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.bytesPerActivate::samples 420 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 284.190476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 185.885137 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 276.585457 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 132 31.43% 31.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 114 27.14% 58.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 62 14.76% 73.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 33 7.86% 81.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 26 6.19% 87.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 3.33% 90.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 0.95% 91.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 1.90% 93.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 27 6.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 420 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 119488 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 119488 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 321.94 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 321.94 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.52 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 369996500 # Total gap between requests +system.mem_ctrls.avgGap 198177.02 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 68352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51136 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 184162241.244129747152 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 137776807.822153240442 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 799 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 28999750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 23827250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27153.32 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 29821.34 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1692180 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 895620 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6525960 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 151671300 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14798880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 204472020 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 550.913294 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 37200500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 321730500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1313760 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 698280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 6804420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 90643680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 66190560 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 194538780 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 524.149955 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 171329000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 187602000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 156317 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 156317 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 156317 # number of overall hits +system.cpu.icache.overall_hits::total 156317 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1660 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1660 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1660 # number of overall misses +system.cpu.icache.overall_misses::total 1660 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108308496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 108308496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108308496 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 157977 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 157977 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 157977 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 157977 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.010508 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.010508 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.010508 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.010508 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65246.081928 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65246.081928 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65246.081928 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65246.081928 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 922 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.086957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 821 # number of writebacks +system.cpu.icache.writebacks::total 821 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 347 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 347 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 347 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 88219497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 88219497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 88219497 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008311 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008311 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67189.258949 # average overall mshr miss latency +system.cpu.icache.replacements 821 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 156317 # number of ReadReq hits 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+system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 347 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 88219497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 88219497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.008311 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008311 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 67189.258949 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67189.258949 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 461.614751 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 157630 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1313 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 120.053313 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 461.614751 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.901591 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 492 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.960938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 317267 # Number of tag accesses +system.cpu.icache.tags.data_accesses 317267 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 468504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 468504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 468777 # number of overall hits +system.cpu.dcache.overall_hits::total 468777 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 4699 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4699 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 4709 # number of overall misses +system.cpu.dcache.overall_misses::total 4709 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212942364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 212942364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212942364 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 473203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 473203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 473486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 473486 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.009930 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009930 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.009945 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009945 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 45316.527772 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45316.527772 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 45220.293905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45220.293905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7524 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.258824 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 580 # number of writebacks +system.cpu.dcache.writebacks::total 580 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 3323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3323 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 1376 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 1381 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1381 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 72791495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 72791495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 73193495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 73193495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.002908 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002908 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.002917 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002917 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 52900.795785 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52900.795785 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 53000.358436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000.358436 # average overall mshr miss latency +system.cpu.dcache.replacements 900 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 213698 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1443 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79131000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 215141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54837.837838 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32993000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44827.445652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 254806 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133589367 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 258055 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012590 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41117.072022 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2616 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 633 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39583498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62533.172196 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 273 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 283 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035336 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 402000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.017668 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80400 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 410 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 384 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 384 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 397.840327 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 470952 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1381 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 341.022448 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 397.840327 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.777032 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 481 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.939453 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 949941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 949941 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 371151000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 371151000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/lbm/config.ini b/test_run/lbm/config.ini new file mode 100644 index 000000000..6450b7988 --- /dev/null +++ b/test_run/lbm/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross 20 reference.dat 0 1 /home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//data/ref/input/100_100_130_ldc.of +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/470.lbm//exe/lbm_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false 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+possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/lbm/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/lbm/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/lbm/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/lbm/config.json b/test_run/lbm/config.json new file mode 100644 index 000000000..c64be2f8c --- /dev/null +++ b/test_run/lbm/config.json @@ -0,0 +1,1815 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + 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"app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/lbm/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/lbm/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/lbm/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": 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"eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/lbm/fs/proc/cpuinfo b/test_run/lbm/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/lbm/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/lbm/fs/proc/stat b/test_run/lbm/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/lbm/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/lbm/fs/sys/devices/system/cpu/online b/test_run/lbm/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/lbm/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/lbm/fs/sys/devices/system/cpu/possible b/test_run/lbm/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/lbm/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/lbm/lbm.out b/test_run/lbm/lbm.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/lbm/stats.txt b/test_run/lbm/stats.txt new file mode 100644 index 000000000..7ac219d0d --- /dev/null +++ b/test_run/lbm/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 4902307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 36842 # Simulator instruction rate (inst/s) +host_mem_usage 854860 # Number of bytes of host memory used +host_op_rate 83783 # Simulator op (including micro ops) rate (op/s) +host_seconds 27.14 # Real time elapsed on the host +host_tick_rate 180611609 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 2274104 # Number of ops (including micro ops) simulated +sim_seconds 0.004902 # Number of seconds simulated +sim_ticks 4902307500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.321334 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 80345 # Number of BTB hits +system.cpu.branchPred.BTBLookups 80894 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 681 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 82458 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 224 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 184 # Number of indirect misses. +system.cpu.branchPred.lookups 83857 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 1019 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 71229 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 885 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71363 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 9 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 7 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 16 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 13 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 71818 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 11 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 6 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 13 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 6 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 3 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 382 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 224787 # number of cc regfile reads +system.cpu.cc_regfile_writes 224753 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 458 # The number of times a branch was mispredicted +system.cpu.commit.branches 72859 # Number of branches committed +system.cpu.commit.bw_lim_events 3268 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 25 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 117033 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000020 # Number of instructions committed +system.cpu.commit.committedOps 2274123 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 9747057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.233314 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.924085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8920827 91.52% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 211342 2.17% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 263671 2.71% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 192727 1.98% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 887 0.01% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26860 0.28% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 99059 1.02% 99.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28416 0.29% 99.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3268 0.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9747057 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 212 # Number of function calls committed. +system.cpu.commit.int_insts 2202108 # Number of committed integer instructions. +system.cpu.commit.loads 1635 # Number of loads committed +system.cpu.commit.membars 14 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 18 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 856639 37.67% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 35 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 2 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 5 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 50 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 37.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 75 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 72 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 50 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 37.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1635 0.07% 37.75% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1415539 62.25% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 2274123 # Class of committed instruction +system.cpu.commit.refs 1417174 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1343403 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 2274104 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 9.804606 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.804606 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 9350428 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 226 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 77569 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 2473522 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 94627 # Number of cycles decode is idle +system.cpu.decode.RunCycles 91391 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3247 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 834 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 222392 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 83857 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 165626 # Number of cache lines fetched +system.cpu.fetch.Cycles 9580362 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 474 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1144257 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6940 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.008553 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 178206 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 80767 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.116706 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.265638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.361026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9355453 95.83% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 462 0.00% 95.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 81714 0.84% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 306 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 404 0.00% 96.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 356 0.00% 96.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 80930 0.83% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 288 0.00% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 242172 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 9762085 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 536 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 76341 # Number of branches executed +system.cpu.iew.exec_nop 39 # number of nop insts executed +system.cpu.iew.exec_rate 0.247066 # Inst execution rate +system.cpu.iew.exec_refs 1509552 # number of memory reference insts executed +system.cpu.iew.exec_stores 1507002 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 12538 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2762 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1507465 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2424933 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2550 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 596 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2422384 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 3565955 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3563309 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 138537 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 25 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1127 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 91926 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 431 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1315617 # num instructions consuming a value +system.cpu.iew.wb_count 2385368 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.470059 # average fanout of values written-back +system.cpu.iew.wb_producers 618418 # num instructions producing a value +system.cpu.iew.wb_rate 0.243290 # insts written-back per cycle +system.cpu.iew.wb_sent 2422037 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2500193 # number of integer regfile reads +system.cpu.int_regfile_writes 838779 # number of integer regfile writes +system.cpu.ipc 0.101993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.101993 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 912819 37.67% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 42 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 2 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 61 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 92 0.00% 37.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 84 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 59 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 37.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2674 0.11% 37.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1507117 62.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2422980 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 36084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014892 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98 0.27% 0.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.01% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 50 0.14% 0.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35929 99.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 994108 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 11750159 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 987126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1060881 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2424861 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2422980 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 150789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 138838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 9762085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.248203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.908083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8884365 91.01% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186986 1.92% 92.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 293038 3.00% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119100 1.22% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 160453 1.64% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73781 0.76% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 32145 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8705 0.09% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3512 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 9762085 # Number of insts issued each cycle +system.cpu.iq.rate 0.247126 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1464935 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2894045 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1398242 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1514819 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2762 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1507465 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 4684140 # number of misc regfile reads +system.cpu.misc_regfile_writes 60 # number of misc regfile writes +system.cpu.numCycles 9804616 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3576234 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1001630 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 196981 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 7051196 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 2436342 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1070903 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 210854 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5679127 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3247 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 5771799 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 69269 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2514763 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 2970 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 102 # count of serializing insts renamed +system.cpu.rename.skidInsts 1791068 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1436706 # Number of vector rename lookups +system.cpu.rob.rob_reads 12098844 # The number of ROB reads +system.cpu.rob.rob_writes 4797353 # The number of ROB writes +system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1429226 # number of vector regfile reads +system.cpu.vec_regfile_writes 352 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 144291 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 321752 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 176581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 354068 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 391 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 632 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144072 # Transaction distribution +system.membus.trans_dist::CleanEvict 219 # Transaction distribution +system.membus.trans_dist::ReadExReq 173888 # Transaction distribution +system.membus.trans_dist::ReadExResp 173887 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 632 # Transaction distribution +system.membus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 496271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20389824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 177461 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 177461 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 177461 # Request fanout histogram +system.membus.reqLayer0.occupancy 936460000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 19.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 907473250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 656 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 320411 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 151 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 701 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 173890 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 173887 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 542 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 114 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 2941 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 2941 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 530317 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 531552 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 44352 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 22421760 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 22466112 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 144682 # Total snoops (count) +system.tol2bus.snoopTraffic 9220608 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 322169 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.001217 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.034861 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 321777 99.88% 99.88% # Request fanout histogram +system.tol2bus.snoop_fanout::1 392 0.12% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 322169 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 353524000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.2 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 262472000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 813000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 23 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1 # number of demand (read+write) hits +system.l2.demand_hits::total 24 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 23 # number of overall hits +system.l2.overall_hits::.cpu.data 1 # number of overall hits +system.l2.overall_hits::total 24 # number of overall hits +system.l2.demand_misses::.cpu.inst 519 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 174003 # number of demand (read+write) misses +system.l2.demand_misses::total 174522 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 519 # number of overall misses +system.l2.overall_misses::.cpu.data 174003 # number of overall misses +system.l2.overall_misses::total 174522 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40762500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 17963265500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 18004028000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40762500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 17963265500 # number of overall miss cycles +system.l2.overall_miss_latency::total 18004028000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 542 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 174004 # number of demand (read+write) accesses +system.l2.demand_accesses::total 174546 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 542 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 174004 # number of overall (read+write) accesses +system.l2.overall_accesses::total 174546 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.957565 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999994 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.999863 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.957565 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999994 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.999863 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.demand_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78540.462428 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 103235.378126 # average overall miss latency +system.l2.overall_avg_miss_latency::total 103161.939469 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 144072 # number of writebacks +system.l2.writebacks::total 144072 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 174003 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 174522 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 174003 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 174522 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35572500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 16223265500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 16258838000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35572500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 16223265500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 16258838000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.999863 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999994 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.999863 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 93235.550536 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 93162.111367 # average overall mshr miss latency +system.l2.replacements 144682 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 176339 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 176339 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 151 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 151 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 151 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 151 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_misses::.cpu.data 173890 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 173890 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 17953897500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 173890 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 103248.591063 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 173890 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 16215027500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 93248.763586 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 519 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40762500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 542 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.957565 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78540.462428 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 519 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35572500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.957565 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68540.462428 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 113 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 9368000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 114 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.991228 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 82902.654867 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 113 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 8238000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.991228 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 72902.654867 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 2941 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 2941 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 2941 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 55362000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18824.209453 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18824.209453 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 30365.095360 # Cycle average of tags in use +system.l2.tags.total_refs 351123 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 177450 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.978715 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 496.663908 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 68.643613 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 29799.787838 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.015157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.002095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.909417 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.926669 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 3120 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 29304 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 3009986 # Number of tag accesses +system.l2.tags.data_accesses 3009986 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 11136064 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11169280 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33216 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 9220608 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9220608 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 174001 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 174520 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 144072 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 144072 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 6775585 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2271596386 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2278371971 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 6775585 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1880870998 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1880870998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 6775585 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2271596386 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4159242969 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 144072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 174001.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000010576500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 9000 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 9000 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 438695 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 135333 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 174520 # Number of read requests accepted +system.mem_ctrls.writeReqs 144072 # Number of write requests accepted +system.mem_ctrls.readBursts 174520 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 144072 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 10869 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10878 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10850 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 10895 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 10938 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10907 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10846 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10863 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10898 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 11015 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10962 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10862 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10944 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 8964 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9014 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9013 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8966 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8980 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9024 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9086 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9067 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 8960 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8960 # Per bank write bursts +system.mem_ctrls.avgRdQLen 3.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 23.69 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 5679206250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 872600000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 8951456250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 32541.86 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 51291.86 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 161227 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 132655 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.08 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 174520 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 144072 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 47549 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 46137 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 50896 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 29930 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an 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length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 365 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2640 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5655 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 8814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9125 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9139 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9752 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9591 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 10159 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 9576 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 10617 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13932 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14020 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 10969 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 10027 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 9450 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 171 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 37 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 24680 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 826.069368 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 676.795020 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 328.058619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1587 6.43% 6.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1443 5.85% 12.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 890 3.61% 15.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 501 2.03% 17.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 902 3.65% 21.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 405 1.64% 23.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1154 4.68% 27.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3458 14.01% 41.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 14340 58.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 24680 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 9000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.390222 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.723502 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 342.009805 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8999 99.99% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::31744-32767 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 9000 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 9000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.005111 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.004843 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.096479 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 8971 99.68% 99.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.16% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 13 0.14% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 0.02% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 9000 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 11169280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9218944 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11169280 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9220608 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2278.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1880.53 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2278.37 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1880.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 32.49 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 17.80 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.69 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 4902290500 # Total gap between requests +system.mem_ctrls.avgGap 15387.36 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 11136064 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 9218944 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 6775584.762889721431 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2271596385.987619400024 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1880531566.002336740494 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 174001 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 144072 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14227250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 8937229000 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 108442678250 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27412.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 51363.09 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 752697.81 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.24 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 88129020 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 46826505 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 624564360 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 377035380 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 1662343440 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 482617920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 3668125185 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 748.244614 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 1206855250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 3531912250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 88114740 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 46834095 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 621508440 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 374884740 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 386608560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 1648007370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 494690400 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 3660648345 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 746.719447 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 1234393250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 163540000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 3504374250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 164918 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 164918 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 164918 # number of overall hits +system.cpu.icache.overall_hits::total 164918 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 708 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 708 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 708 # number of overall misses +system.cpu.icache.overall_misses::total 708 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52243997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 52243997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52243997 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 165626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 165626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 165626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 165626 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.004275 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004275 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.004275 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004275 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 73790.956215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73790.956215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 73790.956215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73790.956215 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.090909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 151 # number of writebacks +system.cpu.icache.writebacks::total 151 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 542 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 542 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 542 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 542 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 41828997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41828997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 41828997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41828997 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77175.271218 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77175.271218 # average overall mshr miss latency +system.cpu.icache.replacements 151 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 164918 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 164918 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 708 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 708 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 52243997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52243997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 165626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 165626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.004275 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004275 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 73790.956215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73790.956215 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 542 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 41828997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41828997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.003272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 77175.271218 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77175.271218 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 389.915117 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 165460 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 305.276753 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 389.915117 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.761553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.761553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 391 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 331794 # Number of tag accesses +system.cpu.icache.tags.data_accesses 331794 # Number of data accesses +system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 216139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 216163 # number of overall hits +system.cpu.dcache.overall_hits::total 216163 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 1201775 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1201775 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 1201777 # number of overall misses +system.cpu.dcache.overall_misses::total 1201777 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 91412553393 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91412553393 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 91412553393 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91412553393 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 1417914 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1417914 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 1417940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1417940 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.847566 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.847566 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.847551 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.847551 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 76064.615584 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76064.615584 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 76064.488997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76064.488997 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8299840 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 142444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.267389 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 176339 # number of writebacks +system.cpu.dcache.writebacks::total 176339 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1024832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1024832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1024832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1024832 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 176943 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176943 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 176945 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176945 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 18377267996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18377267996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 18377452996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18377452996 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.124791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.124791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.124790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.124790 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 103859.819241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103859.819241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 103859.690842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103859.690842 # average overall mshr miss latency +system.cpu.dcache.replacements 176430 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 2129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2129 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 260 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 260 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 19004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 2389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.108832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73092.307692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9290500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046463 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83698.198198 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 214010 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 214010 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1201508 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1201508 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 91393326895 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91393326895 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 1415518 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1415518 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.848812 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.848812 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 76065.516746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76065.516746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1024683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1024683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 176825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 176825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 18367761998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18367761998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.124919 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.124919 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 103875.368291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103875.368291 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 24 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 24 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 26 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.076923 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.076923 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 185000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.076923 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.076923 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.428571 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.428571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.062500 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 77500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.062500 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 77500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 509.260955 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 393134 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 176942 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 2.221824 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 509.260955 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994650 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3012882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3012882 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 4902307500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 4902307500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/leslie3d/config.ini b/test_run/leslie3d/config.ini new file mode 100644 index 000000000..53113a96f --- /dev/null +++ b/test_run/leslie3d/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 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+[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//data/ref/input/leslie3d.in +kvmInSE=false +maxStackSize=67108864 +output=leslie3d.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/leslie3d/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/leslie3d/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/leslie3d/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/leslie3d/config.json b/test_run/leslie3d/config.json new file mode 100644 index 000000000..64a74392d --- /dev/null +++ b/test_run/leslie3d/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/leslie3d/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/leslie3d/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/leslie3d/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": 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"OFF" + ], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.power_state", + "type": "PowerState", + "leaders": [] + }, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": [], + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "Process", + "executable": "/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//exe/leslie3d_base.amd64-armcross", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", + "cwd": "/home/min/a/bnwachuk/Final/gem5", + "pgid": 100, + "simpoint": 0, + "euid": 100, + "input": "/home/min/a/ece565/benchspec-2020/CPU2006/437.leslie3d//data/ref/input/leslie3d.in", + "path": "system.cpu.workload", + "name": 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"cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + 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"True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { 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0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/leslie3d/fs/proc/cpuinfo b/test_run/leslie3d/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/leslie3d/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/leslie3d/fs/proc/stat b/test_run/leslie3d/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/leslie3d/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/leslie3d/fs/sys/devices/system/cpu/online b/test_run/leslie3d/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/leslie3d/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/leslie3d/fs/sys/devices/system/cpu/possible b/test_run/leslie3d/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/leslie3d/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/leslie3d/leslie3d.stdout b/test_run/leslie3d/leslie3d.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/leslie3d/stats.txt b/test_run/leslie3d/stats.txt new file mode 100644 index 000000000..d4f448966 --- /dev/null +++ b/test_run/leslie3d/stats.txt @@ -0,0 +1,1375 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 633191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 139897 # Simulator instruction rate (inst/s) +host_mem_usage 857968 # Number of bytes of host memory used +host_op_rate 143694 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.15 # Real time elapsed on the host +host_tick_rate 88579095 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1027168 # Number of ops (including micro ops) simulated +sim_seconds 0.000633 # Number of seconds simulated +sim_ticks 633191500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.331508 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 271326 # Number of BTB hits +system.cpu.branchPred.BTBLookups 273152 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4136 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 288777 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1729 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2702 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 973 # Number of indirect misses. +system.cpu.branchPred.lookups 303846 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 220585 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 15411 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14913 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 221083 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 236 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 71 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6676 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4222 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 97 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 176 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 7184 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 8627 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 175 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 149 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 14793 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 24269 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 123 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1754 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 31282 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 50224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 45 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2133 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 12495 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 351 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 863 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 2717 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 4338 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 548 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 435 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 273 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 33753 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 811 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 5603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4512 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 412 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 5240 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 7180 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 681 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2024 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 6802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 14803 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 126 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 146 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 24296 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 31283 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 31 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 50204 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 14495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 315 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 255 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 830 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 7160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 176080 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 124 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1242 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 5816 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 229 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 741872 # number of cc regfile reads +system.cpu.cc_regfile_writes 745941 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3517 # The number of times a branch was mispredicted +system.cpu.commit.branches 247012 # Number of branches committed +system.cpu.commit.bw_lim_events 10828 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 105898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1002022 # Number of instructions committed +system.cpu.commit.committedOps 1029189 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1184416 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.868942 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.633643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 852717 71.99% 71.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 86958 7.34% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26662 2.25% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38740 3.27% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 162261 13.70% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2540 0.21% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1651 0.14% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2059 0.17% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10828 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1184416 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 4620 # Number of function calls committed. +system.cpu.commit.int_insts 800492 # Number of committed integer instructions. +system.cpu.commit.loads 35378 # Number of loads committed +system.cpu.commit.membars 138 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 3 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 756594 73.51% 73.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 384 0.04% 73.55% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 94 0.01% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 73.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 15 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 10 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 12 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 72 0.01% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 73.57% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 35378 3.44% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 236587 22.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1029189 # Class of committed instruction +system.cpu.commit.refs 271965 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2101 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1027168 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.266383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.266383 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 939021 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 633 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 256856 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1193254 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 81548 # Number of cycles decode is idle +system.cpu.decode.RunCycles 122138 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4010 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2198 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 52729 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 303846 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 33096 # Number of cache lines fetched +system.cpu.fetch.Cycles 1134130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1231249 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9258 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239932 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 60555 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 278871 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.972256 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.054599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.921750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 900384 75.07% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5040 0.42% 75.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4823 0.40% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6304 0.53% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 251564 20.97% 97.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5198 0.43% 97.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2375 0.20% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5224 0.44% 98.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18534 1.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1199446 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 66938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4018 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 266820 # Number of branches executed +system.cpu.iew.exec_nop 3248 # number of nop insts executed +system.cpu.iew.exec_rate 0.883459 # Inst execution rate +system.cpu.iew.exec_refs 295165 # number of memory reference insts executed +system.cpu.iew.exec_stores 254519 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 11776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 41845 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 258911 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1147285 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 40646 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1118798 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 5041 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4010 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5055 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 16436 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2895 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1054 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 6467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 22322 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1721 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1445197 # num instructions consuming a value +system.cpu.iew.wb_count 1105084 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.389950 # average fanout of values written-back +system.cpu.iew.wb_producers 563554 # num instructions producing a value +system.cpu.iew.wb_rate 0.872629 # insts written-back per cycle +system.cpu.iew.wb_sent 1116457 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1374875 # number of integer regfile reads +system.cpu.int_regfile_writes 605717 # number of integer regfile writes +system.cpu.ipc 0.789651 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.789651 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 827002 73.50% 73.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385 0.03% 73.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 96 0.01% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 43 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 21 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 14 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 16 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 79 0.01% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 73.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 41481 3.69% 77.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 256057 22.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1125209 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3779 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003358 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1189 31.46% 31.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.03% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.03% 31.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.05% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 31.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1706 45.14% 76.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 880 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1126587 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3449247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1102914 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1258414 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1143825 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1125209 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 212 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 116860 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 269 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 67635 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1199446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.938107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.588111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 834403 69.57% 69.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 57645 4.81% 74.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59296 4.94% 79.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 79441 6.62% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 149085 12.43% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9168 0.76% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6069 0.51% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2657 0.22% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1682 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1199446 # Number of insts issued each cycle +system.cpu.iq.rate 0.888521 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2397 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 4664 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2170 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2523 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1322 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 41845 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258911 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 837113 # number of misc regfile reads +system.cpu.misc_regfile_writes 561 # number of misc regfile writes +system.cpu.numCycles 1266384 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 17199 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1240714 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 76 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 110111 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1532 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2211765 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1167418 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1407025 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 145021 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 898782 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4010 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 902303 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 166281 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1427211 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 20802 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 866 # count of serializing insts renamed +system.cpu.rename.skidInsts 403798 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 212 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 2276 # Number of vector rename lookups +system.cpu.rob.rob_reads 2302630 # The number of ROB reads +system.cpu.rob.rob_writes 2285280 # The number of ROB writes +system.cpu.timesIdled 955 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 2115 # number of vector regfile reads +system.cpu.vec_regfile_writes 186 # number of vector regfile writes +system.cpu.workload.numSyscalls 35 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 27415 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 27242 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 55462 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 1 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 981 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1 # Transaction distribution +system.membus.trans_dist::CleanEvict 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 26347 # Transaction distribution +system.membus.trans_dist::ReadExResp 26347 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 981 # Transaction distribution +system.membus.trans_dist::InvalidateReq 81 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 54743 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1749056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 27409 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 27409 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 27409 # Request fanout histogram +system.membus.reqLayer0.occupancy 38625500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 142095500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 1786 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 26011 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1033 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 205 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 26353 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 26350 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1496 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 290 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 81 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 81 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4025 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 79654 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 83679 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 161856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 3369600 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 3531456 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 7 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 28227 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000177 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.013308 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 28222 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 5 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 28227 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 54774000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 8.7 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 40000500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2244000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 663 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 147 # number of demand (read+write) hits +system.l2.demand_hits::total 810 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 663 # number of overall hits +system.l2.overall_hits::.cpu.data 147 # number of overall hits +system.l2.overall_hits::total 810 # number of overall hits +system.l2.demand_misses::.cpu.inst 833 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 26496 # number of demand (read+write) misses +system.l2.demand_misses::total 27329 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 833 # number of overall misses +system.l2.overall_misses::.cpu.data 26496 # number of overall misses +system.l2.overall_misses::total 27329 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 65230000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1988340500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 2053570500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 65230000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1988340500 # number of overall miss cycles +system.l2.overall_miss_latency::total 2053570500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1496 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 26643 # number of demand (read+write) accesses +system.l2.demand_accesses::total 28139 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1496 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 26643 # number of overall (read+write) accesses +system.l2.overall_accesses::total 28139 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.556818 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.994483 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.971214 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.556818 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.994483 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.971214 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78307.322929 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75043.044233 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75142.540891 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 1 # number of writebacks +system.l2.writebacks::total 1 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 833 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 26496 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 27329 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 833 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 26496 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 27329 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 56900000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1723390500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1780290500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 56900000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1723390500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1780290500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.971214 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.994483 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.971214 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65043.421649 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65142.906802 # average overall mshr miss latency +system.l2.replacements 7 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 26010 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 26010 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1031 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1031 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1031 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1031 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 5 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 5 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 26348 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 26348 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1975755500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 26353 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999810 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 74986.925004 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 26348 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1712285500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999810 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 64987.304539 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 663 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 833 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 65230000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1496 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.556818 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78307.322929 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 833 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 56900000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.556818 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68307.322929 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 142 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 148 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12585000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 290 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.510345 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85033.783784 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 148 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 11105000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.510345 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75033.783784 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 81 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 81 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 81 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 81 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1525000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18827.160494 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18827.160494 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 12249.229006 # Cycle average of tags in use +system.l2.tags.total_refs 55376 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 27409 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.020358 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 68.558691 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 789.028674 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 11391.641641 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.002092 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.024079 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.347645 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.373817 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 27402 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 4388 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 22522 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.836243 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 471073 # Number of tag accesses +system.l2.tags.data_accesses 471073 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 53312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 1695680 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1748992 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 53312 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 64 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 64 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 833 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 26495 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 27328 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 1 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 84195698 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 2677989202 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2762184900 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 84195698 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 101075 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 101075 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 84195698 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 2677989202 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2762285975 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 1.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 833.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 26495.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000579000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 54769 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 27328 # Number of read requests accepted +system.mem_ctrls.writeReqs 1 # Number of write requests accepted +system.mem_ctrls.readBursts 27328 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1772 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1704 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 1666 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1604 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 1597 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1622 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1620 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1697 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1766 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1832 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1740 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1725 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1755 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1692 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.76 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.09 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 140438500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 136640000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 652838500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 5139.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 23889.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 25352 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.77 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 27328 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7425 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7778 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 9212 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 2906 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 885.495441 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 752.763476 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.372978 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 104 5.27% 5.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 85 4.31% 9.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 66 3.34% 12.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23 1.17% 14.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 46 2.33% 16.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 0.46% 16.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 33 1.67% 18.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 11 0.56% 19.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1597 80.90% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1974 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 1748992 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1748992 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 64 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 2762.18 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2762.18 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 21.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 633124500 # Total gap between requests +system.mem_ctrls.avgGap 23166.76 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 53312 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 1695680 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 84195697.510152921081 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 2677989202.318729877472 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 833 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 26495 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 1 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 22622500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 630216000 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27157.86 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 23786.22 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 0.00 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 92.77 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 7339920 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 3901260 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 99817200 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 177114390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 93996960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 431955570 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 682.187885 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 236432000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 21060000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 375699500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6768720 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3590070 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 95304720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 49785840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 172093830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 98224800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 425767980 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 672.415817 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 249295750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 21060000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 362835750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 31326 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 31326 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 31326 # number of overall hits +system.cpu.icache.overall_hits::total 31326 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1769 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1769 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1769 # number of overall misses +system.cpu.icache.overall_misses::total 1769 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 90817500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90817500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 90817500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90817500 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 33095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 33095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 33095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 33095 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.053452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.053452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.053452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.053452 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 51338.326738 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51338.326738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 51338.326738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51338.326738 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 618 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1033 # number of writebacks +system.cpu.icache.writebacks::total 1033 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 273 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 273 # number of overall MSHR hits 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WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 26376 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2023177995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.111592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76705.262170 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 136 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 144 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 144 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.055556 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.055556 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 8 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 8 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 615000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 615000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.055556 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76875 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 44 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 58 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 1839973 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 102 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.568627 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31723.672414 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 58 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 1781973 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.568627 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30723.672414 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 161 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012422 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 82000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.006211 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 82000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 138 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.477586 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 89018 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 26721 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.331387 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.477586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.924761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 573017 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 573017 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 633191500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 633191500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/libquantum/config.ini b/test_run/libquantum/config.ini new file mode 100644 index 000000000..c79716d94 --- /dev/null +++ b/test_run/libquantum/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system 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+ "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/libquantum/fs/proc/cpuinfo b/test_run/libquantum/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/libquantum/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/libquantum/fs/proc/stat b/test_run/libquantum/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/libquantum/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/libquantum/fs/sys/devices/system/cpu/online b/test_run/libquantum/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/libquantum/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/libquantum/fs/sys/devices/system/cpu/possible b/test_run/libquantum/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/libquantum/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/libquantum/ref.out b/test_run/libquantum/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/libquantum/stats.txt b/test_run/libquantum/stats.txt new file mode 100644 index 000000000..7950d444b --- /dev/null +++ b/test_run/libquantum/stats.txt @@ -0,0 +1,1358 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 156283000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 196960 # Simulator instruction rate (inst/s) +host_mem_usage 850916 # Number of bytes of host memory used +host_op_rate 200841 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.08 # Real time elapsed on the host +host_tick_rate 30780404 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1019736 # Number of ops (including micro ops) simulated +sim_seconds 0.000156 # Number of seconds simulated +sim_ticks 156283000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.556468 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118292 # Number of BTB hits +system.cpu.branchPred.BTBLookups 118819 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 917 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 143507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 16 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 223 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 207 # Number of indirect misses. +system.cpu.branchPred.lookups 158035 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 35991 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 103468 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 35878 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 103581 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 86 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 9243 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 381 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 52 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 212 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 113 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 450 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 8355 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 456 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 907 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 78 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 16839 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1291 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 1144 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 605 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 26857 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 251 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 23350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 909 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 356 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 51 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 45800 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 413 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 76 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 17 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 373 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 8305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 74 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 29 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 8684 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 127 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 968 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 16840 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1250 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 688 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1102 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 27054 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 873 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1098 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 24756 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 92619 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 85 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 629 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 55 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 369735 # number of cc regfile reads +system.cpu.cc_regfile_writes 385833 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 671 # The number of times a branch was mispredicted +system.cpu.commit.branches 152825 # Number of branches committed +system.cpu.commit.bw_lim_events 48481 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 56 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14700 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000086 # Number of instructions committed +system.cpu.commit.committedOps 1019822 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 267479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.812718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.461220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92809 34.70% 34.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 26484 9.90% 44.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9629 3.60% 48.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 5117 1.91% 50.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2873 1.07% 51.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4221 1.58% 52.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6771 2.53% 55.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71094 26.58% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 48481 18.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267479 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 374 # Number of function calls committed. +system.cpu.commit.int_insts 810700 # Number of committed integer instructions. +system.cpu.commit.loads 256050 # Number of loads committed +system.cpu.commit.membars 48 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 10 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 571430 56.03% 56.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6238 0.61% 56.64% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7 0.00% 56.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 4094 0.40% 57.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 15846 1.55% 58.60% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 6163 0.60% 59.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 21987 2.16% 61.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21987 2.16% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 22 0.00% 63.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 2070 0.20% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.72% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 32 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 37 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 40 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.73% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2082 0.20% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 63.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 256050 25.11% 89.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 111727 10.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1019822 # Class of committed instruction +system.cpu.commit.refs 367777 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 110708 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1019736 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.312568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.312568 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 69648 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 118068 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1040742 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 47684 # Number of cycles decode is idle +system.cpu.decode.RunCycles 140140 # Number of cycles decode is running +system.cpu.decode.SquashCycles 713 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 839 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 11559 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 158035 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 42789 # Number of cache lines fetched +system.cpu.fetch.Cycles 215002 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 516 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1025109 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1918 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.505602 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 53749 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 118937 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.279635 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 269744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.883860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.387563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102170 37.88% 37.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9565 3.55% 41.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6294 2.33% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5938 2.20% 45.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5209 1.93% 47.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6036 2.24% 50.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12883 4.78% 54.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 93825 34.78% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27824 10.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269744 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 42824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 154172 # Number of branches executed +system.cpu.iew.exec_nop 130 # number of nop insts executed +system.cpu.iew.exec_rate 3.294656 # Inst execution rate +system.cpu.iew.exec_refs 371135 # number of memory reference insts executed +system.cpu.iew.exec_stores 112764 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2318 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 258513 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 113591 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1034781 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 258371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1104 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1029804 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2877 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 713 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2932 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 569 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 140 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 78 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2438 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 557 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1277106 # num instructions consuming a value +system.cpu.iew.wb_count 1027868 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.577195 # average fanout of values written-back +system.cpu.iew.wb_producers 737139 # num instructions producing a value +system.cpu.iew.wb_rate 3.288462 # insts written-back per cycle +system.cpu.iew.wb_sent 1028662 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1294575 # number of integer regfile reads +system.cpu.int_regfile_writes 665220 # number of integer regfile writes +system.cpu.ipc 3.199304 # IPC: Instructions Per Cycle +system.cpu.ipc_total 3.199304 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 578607 56.13% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6240 0.61% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 9 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4094 0.40% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15852 1.54% 58.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 6163 0.60% 59.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 21995 2.13% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 21995 2.13% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 22 0.00% 63.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 2072 0.20% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 38 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 41 0.00% 63.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 44 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2087 0.20% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 63.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 258670 25.09% 89.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 112972 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1030912 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 5321 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005161 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 519 9.75% 9.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.02% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2475 46.51% 56.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 195 3.66% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 59.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 5 0.09% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 60.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.02% 60.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.04% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 60.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1818 34.17% 94.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 305 5.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 922482 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 2112204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 917053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 937630 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1034581 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1030912 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 14810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11951 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 269744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.821816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.843448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 61206 22.69% 22.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17814 6.60% 29.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21088 7.82% 37.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22536 8.35% 45.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26893 9.97% 55.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24003 8.90% 64.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18524 6.87% 71.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 56857 21.08% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 20823 7.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269744 # Number of insts issued each cycle +system.cpu.iq.rate 3.298201 # Inst issue rate +system.cpu.iq.vec_alu_accesses 113740 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 224805 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 110815 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 111851 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2064 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2465 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 258513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 113591 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 948337 # number of misc regfile reads +system.cpu.misc_regfile_writes 70292 # number of misc regfile writes +system.cpu.numCycles 312568 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 5775 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1206644 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4616 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 53304 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 6698 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2146469 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1038011 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1225360 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 146000 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 40512 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 713 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 55711 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 18540 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1304214 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 8241 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 282 # count of serializing insts renamed +system.cpu.rename.skidInsts 60610 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 171953 # Number of vector rename lookups +system.cpu.rob.rob_reads 1253156 # The number of ROB reads +system.cpu.rob.rob_writes 2071426 # The number of ROB writes +system.cpu.timesIdled 418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 171247 # number of vector regfile reads +system.cpu.vec_regfile_writes 94563 # number of vector regfile writes +system.cpu.workload.numSyscalls 7 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1859 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 5706 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 12316 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 615 # Transaction distribution +system.membus.trans_dist::ReadExReq 698 # Transaction distribution +system.membus.trans_dist::ReadExResp 698 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 615 # Transaction distribution +system.membus.trans_dist::InvalidateReq 546 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 84032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1859 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1859 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1859 # Request fanout histogram +system.membus.reqLayer0.occupancy 2153000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 6928250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2880 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 5434 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 135 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 137 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3160 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2357 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 568 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 568 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 1185 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 17739 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 18924 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 42240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 700736 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 742976 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 6610 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000151 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012300 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 6609 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 6610 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 11727000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 7.5 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8556500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 12 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4717 # number of demand (read+write) hits +system.l2.demand_hits::total 4729 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 12 # number of overall hits +system.l2.overall_hits::.cpu.data 4717 # number of overall hits +system.l2.overall_hits::total 4729 # number of overall hits +system.l2.demand_misses::.cpu.inst 513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 800 # number of demand (read+write) misses +system.l2.demand_misses::total 1313 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 513 # number of overall misses +system.l2.overall_misses::.cpu.data 800 # number of overall misses +system.l2.overall_misses::total 1313 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40757500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 61617000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 102374500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40757500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 61617000 # number of overall miss cycles +system.l2.overall_miss_latency::total 102374500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 525 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5517 # number of demand (read+write) accesses +system.l2.demand_accesses::total 6042 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 525 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5517 # number of overall (read+write) accesses +system.l2.overall_accesses::total 6042 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.977143 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.145006 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.217312 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.977143 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.145006 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.217312 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.demand_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79449.317739 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77021.250000 # average overall miss latency +system.l2.overall_avg_miss_latency::total 77969.916222 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 800 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1313 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 800 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1313 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35627500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 53617000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 89244500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35627500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 53617000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 89244500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.217312 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.145006 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.217312 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67021.250000 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 67969.916222 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 5434 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 5434 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 135 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 135 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 135 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 135 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 2462 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 2462 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 698 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 698 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 52965500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3160 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.220886 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 75881.805158 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 698 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 45985500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.220886 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 65881.805158 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 12 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40757500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79449.317739 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35627500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69449.317739 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 2255 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 102 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 8651500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2357 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.043275 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 84818.627451 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 102 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 7631500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.043275 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 74818.627451 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 22 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 22 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 546 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 546 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 568 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.961268 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 546 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 10445000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.961268 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19130.036630 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19130.036630 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1068.548216 # Cycle average of tags in use +system.l2.tags.total_refs 11769 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1879 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 6.263438 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 265.121704 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 444.344216 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 359.082296 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.008091 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.013560 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.010958 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.032610 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1857 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 954 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 881 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.056671 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 100399 # Number of tag accesses +system.l2.tags.data_accesses 100399 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 32832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 51200 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 84032 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 32832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 800 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1313 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 210080431 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 327610809 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 537691240 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 210080431 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 210080431 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 327610809 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 537691240 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 800.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000574000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2616 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1313 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1313 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 157 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 117 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 4 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 104 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 142 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 140 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 109 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 41 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 103 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 10714750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 6565000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 35333500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8160.51 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26910.51 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1092 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 83.17 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1313 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 688 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 427 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 156 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 221 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 380.235294 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 226.255947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 366.440593 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 64 28.96% 28.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 47 21.27% 50.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 38 17.19% 67.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 6 2.71% 70.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 2.71% 72.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 3.62% 76.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.71% 79.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.26% 81.45% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 18.55% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 221 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 84032 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 84032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 537.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 537.69 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 153415000 # Total gap between requests +system.mem_ctrls.avgGap 116843.11 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 32832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 51200 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 210080431.012970060110 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 327610808.597224235535 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 800 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14512750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 20820750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28289.96 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26025.94 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 642600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 341550 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 5776260 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 12292800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 37806390 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 28176000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 85035600 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 544.112923 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 72846750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 5200000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 78236250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 935340 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 497145 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 3598560 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 12292800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 30736680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 34129440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 82189965 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 525.904705 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 88357250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 5200000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 62725750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 42116 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 42116 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 42116 # number of overall hits +system.cpu.icache.overall_hits::total 42116 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 672 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 672 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 672 # number of overall misses +system.cpu.icache.overall_misses::total 672 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 51529999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51529999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 51529999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51529999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 42788 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 42788 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 42788 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 42788 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.015705 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015705 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.015705 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015705 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 76681.546131 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76681.546131 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 76681.546131 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76681.546131 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 750 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 135 # number of writebacks +system.cpu.icache.writebacks::total 135 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses 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(read+write) accesses +system.cpu.dcache.overall_accesses::total 369300 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.136202 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.136202 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.136198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.136198 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 18453.683593 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18453.683593 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 18452.949819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18452.949819 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12602 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 683 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.450952 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 5434 # number of writebacks +system.cpu.dcache.writebacks::total 5434 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44213 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 44213 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44213 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 6083 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 35938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.009142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15260.509554 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 68760 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 42358 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 820589909 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 111118 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 111118 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.381198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 19372.725554 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19372.725554 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 39193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 39193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3165 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3165 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 83846993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83846993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.028483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.028483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26491.940916 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 23 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 25 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.080000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.080000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 1 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 563 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 17880061 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 564 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.998227 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31758.545293 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 563 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 17317061 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.998227 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30758.545293 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 21500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036364 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.StoreCondReq_hits::.cpu.data 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 48 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 48 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 436.655859 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 325186 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6083 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 53.458162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 436.655859 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.852843 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 450 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 744889 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 744889 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 156283000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 156283000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/mcf/config.ini b/test_run/mcf/config.ini new file mode 100644 index 000000000..dbe27cf40 --- /dev/null +++ b/test_run/mcf/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker 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+clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//data/ref/input/inp.in +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/429.mcf//exe/mcf_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=inp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/mcf/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/mcf/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/mcf/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/mcf/config.json b/test_run/mcf/config.json new file mode 100644 index 000000000..4faf797d1 --- /dev/null +++ b/test_run/mcf/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/mcf/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/mcf/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/mcf/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.itb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.itb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "itb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": 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"prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "write_allocator": null, + "size": 32768, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dcache.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.tol2bus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 4, + "writeback_clean": false, + "tags": { + "tag_latency": 2, + "replacement_policy": "system.cpu.dcache.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 2, 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"addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "type": "DerivO3CPU", + "wbWidth": 8, + "numPhysVecRegs": 256, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + 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"clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + 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"cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/mcf/fs/proc/cpuinfo b/test_run/mcf/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/mcf/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/mcf/fs/proc/stat b/test_run/mcf/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/mcf/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/mcf/fs/sys/devices/system/cpu/online b/test_run/mcf/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/mcf/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/mcf/fs/sys/devices/system/cpu/possible b/test_run/mcf/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/mcf/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/mcf/inp.out b/test_run/mcf/inp.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/mcf/stats.txt b/test_run/mcf/stats.txt new file mode 100644 index 000000000..aeb787117 --- /dev/null +++ b/test_run/mcf/stats.txt @@ -0,0 +1,1361 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 500536000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 148487 # Simulator instruction rate (inst/s) +host_mem_usage 850952 # Number of bytes of host memory used +host_op_rate 168442 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.73 # Real time elapsed on the host +host_tick_rate 74321136 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1134416 # Number of ops (including micro ops) simulated +sim_seconds 0.000501 # Number of seconds simulated +sim_ticks 500536000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.358374 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 92293 # Number of BTB hits +system.cpu.branchPred.BTBLookups 92889 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 809 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 181500 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 3097 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3299 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 202 # Number of indirect misses. +system.cpu.branchPred.lookups 226647 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 118031 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60367 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 116682 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 61716 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 7 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 6619 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 4134 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 2960 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 4214 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 3 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 600 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1232 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 602 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 594 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 224 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 563 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 69 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 31 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 23 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 154608 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 346 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1189 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 4 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 5426 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 1800 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 4062 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4854 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 596 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1232 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 602 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 594 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 2 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 224 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 23041 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 8 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 38 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 11371 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 469065 # number of cc regfile reads +system.cpu.cc_regfile_writes 445002 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 567 # The number of times a branch was mispredicted +system.cpu.commit.branches 222072 # Number of branches committed +system.cpu.commit.bw_lim_events 63204 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 14510 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000623 # Number of instructions committed +system.cpu.commit.committedOps 1135038 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 921910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.231181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320907 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 599089 64.98% 64.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 111489 12.09% 77.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 58121 6.30% 83.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 30329 3.29% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25620 2.78% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7612 0.83% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 14974 1.62% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11472 1.24% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63204 6.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 921910 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 10970 # Number of function calls committed. +system.cpu.commit.int_insts 986971 # Number of committed integer instructions. +system.cpu.commit.loads 170934 # Number of loads committed +system.cpu.commit.membars 1232 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 830 0.07% 0.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 769661 67.81% 67.88% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 6011 0.53% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 3 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 1895 0.17% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.58% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 1893 0.17% 68.75% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 1668 0.15% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.89% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 2267 0.20% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 170934 15.06% 84.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 179876 15.85% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1135038 # Class of committed instruction +system.cpu.commit.refs 350810 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 19901 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1134416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.001072 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.001072 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 369143 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 245 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 92282 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1154444 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 337025 # Number of cycles decode is idle +system.cpu.decode.RunCycles 207687 # Number of cycles decode is running +system.cpu.decode.SquashCycles 679 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 9570 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 226647 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 151079 # Number of cache lines fetched +system.cpu.fetch.Cycles 515682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 503 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1024163 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1842 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.226404 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 407448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 106761 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.023065 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 924104 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.529422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 694266 75.13% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24064 2.60% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21313 2.31% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29222 3.16% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 37715 4.08% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20366 2.20% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6389 0.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 10142 1.10% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 80627 8.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 924104 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 76969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 223488 # Number of branches executed +system.cpu.iew.exec_nop 654 # number of nop insts executed +system.cpu.iew.exec_rate 1.165904 # Inst execution rate +system.cpu.iew.exec_refs 376201 # number of memory reference insts executed +system.cpu.iew.exec_stores 181843 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 2328 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 172837 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1266 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 182525 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1150122 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 194358 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 818 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1167155 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 11080 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11091 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 1371 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10811 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16776 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1902 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 487 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 170 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1099277 # num instructions consuming a value +system.cpu.iew.wb_count 1144060 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.512096 # average fanout of values written-back +system.cpu.iew.wb_producers 562935 # num instructions producing a value +system.cpu.iew.wb_rate 1.142834 # insts written-back per cycle +system.cpu.iew.wb_sent 1144769 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1326039 # number of integer regfile reads +system.cpu.int_regfile_writes 763044 # number of integer regfile writes +system.cpu.ipc 0.998929 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.998929 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 848 0.07% 0.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 776608 66.49% 66.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6014 0.51% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 1951 0.17% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1948 0.17% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1706 0.15% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 2303 0.20% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 194587 16.66% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 182006 15.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1167974 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 28747 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024613 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6136 21.34% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 21.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.01% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 21.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7980 27.76% 49.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 14627 50.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1174093 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3246005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1123907 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1143560 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1148202 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1167974 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15046 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 924104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.263899 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.974668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 558743 60.46% 60.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 87176 9.43% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72815 7.88% 77.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64315 6.96% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49642 5.37% 90.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39656 4.29% 94.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27197 2.94% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14287 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10273 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 924104 # Number of insts issued each cycle +system.cpu.iq.rate 1.166722 # Inst issue rate +system.cpu.iq.vec_alu_accesses 21780 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 42868 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 20153 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 20989 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 16339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7820 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 172837 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 182525 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 795052 # number of misc regfile reads +system.cpu.misc_regfile_writes 4929 # number of misc regfile writes +system.cpu.numCycles 1001073 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 10901 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1211210 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 5977 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 340701 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 119 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1857450 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1152162 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1227536 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 214110 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 97675 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 679 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 108200 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 16315 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1311537 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 249513 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 3792 # count of serializing insts renamed +system.cpu.rename.skidInsts 38106 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 24991 # Number of vector rename lookups +system.cpu.rob.rob_reads 2007201 # The number of ROB reads +system.cpu.rob.rob_writes 2301310 # The number of ROB writes +system.cpu.timesIdled 7434 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 24540 # number of vector regfile reads +system.cpu.vec_regfile_writes 10206 # number of vector regfile writes +system.cpu.workload.numSyscalls 13 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4607 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15831 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 32533 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1281 # Transaction distribution +system.membus.trans_dist::ReadExReq 3311 # Transaction distribution +system.membus.trans_dist::ReadExResp 3311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1281 # Transaction distribution +system.membus.trans_dist::InvalidateReq 15 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 293888 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4607 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4607 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4607 # Request fanout histogram +system.membus.reqLayer0.occupancy 5392000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 23805750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 13349 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 4041 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 10990 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 800 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3338 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 11349 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 2000 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 15 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 15 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 33688 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15547 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 49235 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 1429696 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 600256 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2029952 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 16702 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000060 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.007738 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 16701 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 16702 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31297500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8014500 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 17023500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 10829 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1266 # number of demand (read+write) hits +system.l2.demand_hits::total 12095 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 10829 # number of overall hits +system.l2.overall_hits::.cpu.data 1266 # number of overall hits +system.l2.overall_hits::total 12095 # number of overall hits +system.l2.demand_misses::.cpu.inst 520 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4072 # number of demand (read+write) misses +system.l2.demand_misses::total 4592 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 520 # number of overall misses +system.l2.overall_misses::.cpu.data 4072 # number of overall misses +system.l2.overall_misses::total 4592 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 40890000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 355596000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 396486000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 40890000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 355596000 # number of overall miss cycles +system.l2.overall_miss_latency::total 396486000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 11349 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5338 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16687 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 11349 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5338 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16687 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.045819 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.762833 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.275184 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.045819 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.762833 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.275184 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78634.615385 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 87327.111984 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86342.770035 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 520 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4072 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 4592 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 520 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4072 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 4592 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 35690000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 314876000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 350566000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 35690000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 314876000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 350566000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.275184 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.762833 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.275184 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 77327.111984 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76342.770035 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 4041 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 4041 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 10989 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 10989 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 10989 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 10989 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 27 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 27 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3311 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3311 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 282094000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3338 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.991911 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85199.033525 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3311 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 248984000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.991911 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75199.033525 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 10829 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 520 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 40890000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 11349 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.045819 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78634.615385 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 520 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 35690000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.045819 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68634.615385 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1239 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 761 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 73502000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 2000 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.380500 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 96586.070959 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 761 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 65892000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.380500 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 86586.070959 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 15 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 15 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 15 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 15 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 284500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18966.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18966.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2520.152590 # Cycle average of tags in use +system.l2.tags.total_refs 32517 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 4605 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 7.061238 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 11.282538 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 502.340959 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2006.529093 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000344 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.015330 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.061234 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.076909 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 4605 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 742 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 3779 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.140533 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 264861 # Number of tag accesses +system.l2.tags.data_accesses 264861 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 33280 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 260608 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 293888 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 33280 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 520 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4072 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 4592 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 66488724 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 520657855 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 587146579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 66488724 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 66488724 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 520657855 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 587146579 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 520.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4072.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000696500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 9183 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 4592 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 4592 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 322 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 275 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 310 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 422 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 261 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 286 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 312 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 257 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 301 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 208 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 273 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.53 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 74344250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 22960000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 160444250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 16189.95 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34939.95 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 4061 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.44 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 4592 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 2205 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1063 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 694 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 619 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 529 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 553.981096 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 351.714124 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 410.059059 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 90 17.01% 17.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 113 21.36% 38.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 5.67% 44.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 28 5.29% 49.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 4.35% 53.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 17 3.21% 56.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 3.21% 60.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 32 6.05% 66.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 179 33.84% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 529 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 293888 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 293888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 587.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 587.15 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.59 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 500327000 # Total gap between requests +system.mem_ctrls.avgGap 108956.23 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 33280 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 260608 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 66488724.087777905166 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 520657854.779676198959 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 520 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4072 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 14303500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 146140750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27506.73 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 35889.18 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 88.44 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1899240 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1001880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 14915460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 201196320 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 22777440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 281127300 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 561.652509 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 57508250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 16640000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 426387750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1892100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1005675 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 17871420 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 153099150 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 63280320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 276485625 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 552.379100 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 163110250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 16640000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 320785750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 139575 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 139575 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 139575 # number of overall hits +system.cpu.icache.overall_hits::total 139575 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 11504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 11504 # number of overall misses +system.cpu.icache.overall_misses::total 11504 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 201794498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201794498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 201794498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201794498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 151079 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 151079 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 151079 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 151079 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.076146 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.076146 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.076146 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.076146 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 17541.246349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 17541.246349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17541.246349 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 10990 # number of writebacks +system.cpu.icache.writebacks::total 10990 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 155 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 155 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 11349 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11349 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 11349 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11349 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 181213498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 181213498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 379303401 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.015722 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015722 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.015696 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015696 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 70863.345981 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70863.345981 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 70871.338004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70871.338004 # average overall mshr miss latency +system.cpu.dcache.replacements 4841 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157984 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3671 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 194832000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 161655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 53073.277036 # average ReadReq miss latency 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# average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 172379 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 6250 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 500534278 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 178629 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.034989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 80085.484480 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80085.484480 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2915 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2915 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 288790906 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 288790906 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 86593.974813 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86593.974813 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 69 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 687 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.100437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002911 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 13 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 411995 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 13 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31691.923077 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 13 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 398995 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30691.923077 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 640 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 602 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 8564000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1242 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.484702 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14225.913621 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 601 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 91000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000805 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 91000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1232 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1232 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 473.788749 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 338206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5353 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.180646 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 473.788749 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.925369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 692269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 692269 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 500536000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 500536000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/milc/config.ini b/test_run/milc/config.ini new file mode 100644 index 000000000..60110fa68 --- /dev/null +++ b/test_run/milc/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + 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+[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//exe/milc_base.amd64-armcross +gid=100 +input=/home/min/a/ece565/benchspec-2020/CPU2006/433.milc//data/ref/input/su3imp.in +kvmInSE=false +maxStackSize=67108864 +output=su3imp.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/milc/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/milc/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/milc/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/milc/config.json b/test_run/milc/config.json new file mode 100644 index 000000000..afd27cd76 --- /dev/null +++ b/test_run/milc/config.json @@ -0,0 +1,1810 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/milc/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/milc/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/milc/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", 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"name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/milc/fs/proc/cpuinfo b/test_run/milc/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/milc/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/milc/fs/proc/stat b/test_run/milc/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/milc/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/milc/fs/sys/devices/system/cpu/online b/test_run/milc/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/milc/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/milc/fs/sys/devices/system/cpu/possible b/test_run/milc/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/milc/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/milc/stats.txt b/test_run/milc/stats.txt new file mode 100644 index 000000000..95469d9b2 --- /dev/null +++ b/test_run/milc/stats.txt @@ -0,0 +1,1388 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 771934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 106332 # Simulator instruction rate (inst/s) +host_mem_usage 852696 # Number of bytes of host memory used +host_op_rate 110082 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.40 # Real time elapsed on the host +host_tick_rate 82079517 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000005 # Number of instructions simulated +sim_ops 1035288 # Number of ops (including micro ops) simulated +sim_seconds 0.000772 # Number of seconds simulated +sim_ticks 771934000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.792148 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 67887 # Number of BTB hits +system.cpu.branchPred.BTBLookups 68717 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1100 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 42422 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 82 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 306 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 224 # Number of indirect misses. +system.cpu.branchPred.lookups 143579 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 21294 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 6454 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 14513 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 13235 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 62 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 18 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 234 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 319 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1598 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 10 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 469 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 42 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 328 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 11 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 410 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 138 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 350 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 529 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 231 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 760 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 930 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 414 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1635 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 37 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 281 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 93 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 101 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 11 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 36 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 16937 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 387 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 174 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 149 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 199 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 26 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1951 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 71 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 8 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 323 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 409 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 59 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 350 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 231 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 530 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 761 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1869 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1647 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 687 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 196 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 214 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 10082 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 14 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 80 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 49901 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 68964 # number of cc regfile reads +system.cpu.cc_regfile_writes 68721 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 797 # The number of times a branch was mispredicted +system.cpu.commit.branches 89552 # Number of branches committed +system.cpu.commit.bw_lim_events 63878 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 169 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 505862 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000413 # Number of instructions committed +system.cpu.commit.committedOps 1035696 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1429782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.724373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.819359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1058409 74.03% 74.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 200068 13.99% 88.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61768 4.32% 92.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9481 0.66% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20769 1.45% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6490 0.45% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5334 0.37% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3585 0.25% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63878 4.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1429782 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 30618 # Number of function calls committed. +system.cpu.commit.int_insts 1016144 # Number of committed integer instructions. +system.cpu.commit.loads 160773 # Number of loads committed +system.cpu.commit.membars 142 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 35 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 521896 50.39% 50.39% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 158304 15.28% 65.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 60283 5.82% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 71.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 83 0.01% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 138 0.01% 71.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 140 0.01% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 103 0.01% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 71.54% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160773 15.52% 87.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 133941 12.93% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1035696 # Class of committed instruction +system.cpu.commit.refs 294714 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1073 # Number of committed Vector instructions. +system.cpu.committedInsts 1000005 # Number of Instructions Simulated +system.cpu.committedOps 1035288 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.543861 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.543861 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1103566 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 305 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 67843 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1736058 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 125816 # Number of cycles decode is idle +system.cpu.decode.RunCycles 212734 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4634 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1033 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 49279 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 143579 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 215175 # Number of cache lines fetched +system.cpu.fetch.Cycles 1257140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1758524 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 9874 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.092999 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 233891 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 117870 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.139037 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.215674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.571580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1160787 77.59% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24293 1.62% 79.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 54513 3.64% 82.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17903 1.20% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26423 1.77% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35114 2.35% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 27991 1.87% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 9593 0.64% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 139412 9.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1496029 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 47840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 2747 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 132264 # Number of branches executed +system.cpu.iew.exec_nop 464 # number of nop insts executed +system.cpu.iew.exec_rate 0.984822 # Inst execution rate +system.cpu.iew.exec_refs 473801 # number of memory reference insts executed +system.cpu.iew.exec_stores 198453 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 332881 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 276092 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 214 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 228886 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1701929 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 275348 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1520436 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17214 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 49608 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4634 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75400 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 3665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 149 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 33 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 115309 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 94929 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2518 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1610580 # num instructions consuming a value +system.cpu.iew.wb_count 1454780 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.646638 # average fanout of values written-back +system.cpu.iew.wb_producers 1041462 # num instructions producing a value +system.cpu.iew.wb_rate 0.942295 # insts written-back per cycle +system.cpu.iew.wb_sent 1519421 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 2248203 # number of integer regfile reads +system.cpu.int_regfile_writes 1261314 # number of integer regfile writes +system.cpu.ipc 0.647727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.647727 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 779760 51.22% 51.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 199683 13.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 67953 4.46% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 85 0.01% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 140 0.01% 68.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 140 0.01% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 107 0.01% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 275910 18.12% 86.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 198634 13.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1522447 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1173303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.770669 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7553 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 612118 52.17% 52.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 533999 45.51% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 2 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 98.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11437 0.97% 99.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8193 0.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 2694513 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5738105 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1453690 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2366292 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1701251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1522447 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 666110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 26240 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 514802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1496029 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.017659 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.601098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 888614 59.40% 59.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200614 13.41% 72.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 178533 11.93% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95716 6.40% 91.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45502 3.04% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45883 3.07% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22769 1.52% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17602 1.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 796 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1496029 # Number of insts issued each cycle +system.cpu.iq.rate 0.986124 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1202 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 2360 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1090 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1315 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 4086 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 166 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 276092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 228886 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 923178 # number of misc regfile reads +system.cpu.misc_regfile_writes 569 # number of misc regfile writes +system.cpu.numCycles 1543869 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 463634 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 914731 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 93277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 136560 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 125 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2724794 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1715294 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1498240 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 239996 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 537737 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4634 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 638173 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 583452 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 2637927 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 13032 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 390 # count of serializing insts renamed +system.cpu.rename.skidInsts 224398 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 223 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1492 # Number of vector rename lookups +system.cpu.rob.rob_reads 2857867 # The number of ROB reads +system.cpu.rob.rob_writes 3149444 # The number of ROB writes +system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1321 # number of vector regfile reads +system.cpu.vec_regfile_writes 571 # number of vector regfile writes +system.cpu.workload.numSyscalls 26 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 13062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 29025 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 15493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 25 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 31663 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 25 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 753 # Transaction distribution +system.membus.trans_dist::WritebackDirty 13041 # Transaction distribution +system.membus.trans_dist::CleanEvict 21 # Transaction distribution +system.membus.trans_dist::ReadExReq 15203 # Transaction distribution +system.membus.trans_dist::ReadExResp 15202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 753 # Transaction distribution +system.membus.trans_dist::InvalidateReq 7 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 44980 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1855744 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 15963 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15963 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15963 # Request fanout histogram +system.membus.reqLayer0.occupancy 85449500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 11.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 83558250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 959 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 28109 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 412 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 59 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 15204 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 15202 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 816 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 143 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 7 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 7 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 2044 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 45787 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 47831 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 78592 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 1946432 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 2025024 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 13087 # Total snoops (count) +system.tol2bus.snoopTraffic 834624 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 29257 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000889 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.029798 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 29231 99.91% 99.91% # Request fanout histogram +system.tol2bus.snoop_fanout::1 26 0.09% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 29257 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 31311500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 23021000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 3.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 1224000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 203 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 4 # number of demand (read+write) hits +system.l2.demand_hits::total 207 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 203 # number of overall hits +system.l2.overall_hits::.cpu.data 4 # number of overall hits +system.l2.overall_hits::total 207 # number of overall hits +system.l2.demand_misses::.cpu.inst 613 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 15343 # number of demand (read+write) misses +system.l2.demand_misses::total 15956 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 613 # number of overall misses +system.l2.overall_misses::.cpu.data 15343 # number of overall misses +system.l2.overall_misses::total 15956 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 47921500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 1333591000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 1381512500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 47921500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 1333591000 # number of overall miss cycles +system.l2.overall_miss_latency::total 1381512500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 816 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 15347 # number of demand (read+write) accesses +system.l2.demand_accesses::total 16163 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 816 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 15347 # number of overall (read+write) accesses +system.l2.overall_accesses::total 16163 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.751225 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.999739 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.987193 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.751225 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.999739 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.987193 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.demand_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78175.367047 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 86918.529623 # average overall miss latency +system.l2.overall_avg_miss_latency::total 86582.633492 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 13041 # number of writebacks +system.l2.writebacks::total 13041 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 613 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 15343 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 15956 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 613 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 15343 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 15956 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 41791500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 1180181000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 1221972500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 41791500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 1180181000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 1221972500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.987193 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.999739 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.987193 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 76919.833149 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 76583.886939 # average overall mshr miss latency +system.l2.replacements 13087 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 15068 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 15068 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 411 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 411 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 411 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 411 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 1 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 1 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 15203 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 15203 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 1321531000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 15204 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.999934 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 86925.672565 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 15203 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 1169521000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.999934 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 76926.988094 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 203 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 613 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 47921500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 816 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.751225 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78175.367047 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 613 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 41791500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.751225 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68175.367047 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 140 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 12060000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 143 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.979021 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 86142.857143 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 140 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 10660000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.979021 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 76142.857143 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 7 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 7 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 7 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 7 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 133500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19071.428571 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19071.428571 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 2615.918231 # Cycle average of tags in use +system.l2.tags.total_refs 31653 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 15957 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.983644 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 1.225835 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 565.825416 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2048.866980 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000037 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.017268 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.062526 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.079831 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2870 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1846 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 822 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.087585 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 269253 # Number of tag accesses +system.l2.tags.data_accesses 269253 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 39232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 981952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1021184 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 39232 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 834624 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 834624 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 613 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 15343 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 15956 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 13041 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 13041 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 50822998 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 1272067301 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1322890299 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 50822998 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1081211606 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 1081211606 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 50822998 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 1272067301 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2404101905 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 13041.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 613.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 15343.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000013500250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 813 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 813 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 43428 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 12201 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 15956 # Number of read requests accepted +system.mem_ctrls.writeReqs 13041 # Number of write requests accepted +system.mem_ctrls.readBursts 15956 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 13041 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 992 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1054 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 982 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 971 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 972 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 960 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 1073 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 985 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1026 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 956 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 979 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1036 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 1008 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 976 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 814 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 811 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 816 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 818 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 815 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 813 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 810 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 810 # Per bank write bursts +system.mem_ctrls.avgRdQLen 2.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.02 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 249603250 # Total ticks spent queuing +system.mem_ctrls.totBusLat 79780000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 548778250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 15643.22 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 34393.22 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 13782 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 11296 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.38 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.62 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 15956 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 13041 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 7854 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 7660 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 818 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 814 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 813 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 3886 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 476.557900 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 444.203406 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 118.434932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 147 3.78% 3.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 4.04% 7.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 28 0.72% 8.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 185 4.76% 13.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3341 85.98% 99.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 0.21% 99.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 0.08% 99.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 0.10% 99.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 0.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 3886 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 813 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.611316 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.109728 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 102.759447 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 812 99.88% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2944-3071 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 813 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 813 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.007380 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.006268 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.210429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 812 99.88% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.12% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 813 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 1021184 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 832896 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1021184 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 834624 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 1322.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1078.97 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1322.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1081.21 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 18.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.34 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 8.43 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 771884000 # Total gap between requests +system.mem_ctrls.avgGap 26619.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 39232 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 981952 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 832896 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 50822997.821057237685 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 1272067301.090507745743 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 1078973072.827469587326 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 613 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 15343 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 13041 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 16555500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 532222750 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 15715577750 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27007.34 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 34688.31 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 1205089.93 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 86.48 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 14080080 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 7460970 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 57398460 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 33971760 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 334312410 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 14896800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 522969840 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 677.479992 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 36020250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 710173750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 13708800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 7286400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 33961320 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 60849360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 335170830 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 14173920 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 521678010 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 675.806494 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 34169250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 25740000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 712024750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 214182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 214182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 214182 # number of overall hits +system.cpu.icache.overall_hits::total 214182 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 993 # number of overall misses +system.cpu.icache.overall_misses::total 993 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 62276498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62276498 # 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# average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 139 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11812000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 84978.417266 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84978.417266 # average ReadReq mshr miss latency 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+system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 167 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.005988 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 264000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 263000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.005988 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 263000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 142 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 142 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 264.979661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 295294 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 15352 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.234888 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 264.979661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.517538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.529297 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 833190 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 833190 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 771934000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 771934000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/milc/su3imp.out b/test_run/milc/su3imp.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/namd/config.ini b/test_run/namd/config.ini new file mode 100644 index 000000000..21079292e --- /dev/null +++ b/test_run/namd/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 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+opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross --input /home/min/a/ece565/benchspec-2020/CPU2006/444.namd//data/all/input/namd.input --iterations 1 --output namd.out +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/444.namd//exe/namd_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=namd.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/namd/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/namd/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/namd/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/namd/config.json b/test_run/namd/config.json new file mode 100644 index 000000000..d650e0b70 --- /dev/null +++ b/test_run/namd/config.json @@ -0,0 +1,1816 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/namd/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/namd/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/namd/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/namd/fs/proc/cpuinfo b/test_run/namd/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/namd/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/namd/fs/proc/stat b/test_run/namd/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/namd/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/namd/fs/sys/devices/system/cpu/online b/test_run/namd/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/namd/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/namd/fs/sys/devices/system/cpu/possible b/test_run/namd/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/namd/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/namd/namd.stdout b/test_run/namd/namd.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/namd/stats.txt b/test_run/namd/stats.txt new file mode 100644 index 000000000..c59840032 --- /dev/null +++ b/test_run/namd/stats.txt @@ -0,0 +1,1346 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 342062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 156793 # Simulator instruction rate (inst/s) +host_mem_usage 853424 # Number of bytes of host memory used +host_op_rate 174295 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.38 # Real time elapsed on the host +host_tick_rate 53631716 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1111649 # Number of ops (including micro ops) simulated +sim_seconds 0.000342 # Number of seconds simulated +sim_ticks 342062500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.672835 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 118809 # Number of BTB hits +system.cpu.branchPred.BTBLookups 120407 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 4928 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197507 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2833 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3243 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 410 # Number of indirect misses. +system.cpu.branchPred.lookups 252244 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 101918 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 65407 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 97895 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 69430 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 234 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12202 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3091 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1934 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 549 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 5339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 986 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1294 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 1869 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 1433 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 568 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 590 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1553 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 981 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1682 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1384 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 768 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 526 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 379 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 818 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 872 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 1097 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 812 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1409 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 264 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 1142 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 124175 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 959 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 3431 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 1422 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 4096 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3369 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3051 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 5683 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2247 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1586 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1202 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 973 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1537 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 634 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1807 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1249 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 1394 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 738 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 513 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 962 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 1080 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1488 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 37083 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 680 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1093 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 12668 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 107 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 406413 # number of cc regfile reads +system.cpu.cc_regfile_writes 399910 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4465 # The number of times a branch was mispredicted +system.cpu.commit.branches 216048 # Number of branches committed +system.cpu.commit.bw_lim_events 53496 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 486 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 118898 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001856 # Number of instructions committed +system.cpu.commit.committedOps 1113505 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 605513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.838945 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.532655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 255756 42.24% 42.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 143185 23.65% 65.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57737 9.54% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36800 6.08% 81.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21553 3.56% 85.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8832 1.46% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10972 1.81% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17182 2.84% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53496 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 605513 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 11108 # Number of function calls committed. +system.cpu.commit.int_insts 980744 # Number of committed integer instructions. +system.cpu.commit.loads 176934 # Number of loads committed +system.cpu.commit.membars 475 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 185 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 796966 71.57% 71.59% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3693 0.33% 71.92% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 912 0.08% 72.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 438 0.04% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 15 0.00% 72.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 21 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 9 0.00% 72.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1629 0.15% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.19% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 433 0.04% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 647 0.06% 72.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 598 0.05% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 526 0.05% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 72.39% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 176934 15.89% 88.28% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 130493 11.72% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1113505 # Class of committed instruction +system.cpu.commit.refs 307427 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 10353 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1111649 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.684126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.684126 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 123704 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 477 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 117668 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1269158 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 241422 # Number of cycles decode is idle +system.cpu.decode.RunCycles 244786 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4577 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 1653 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 8066 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 252244 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 191602 # Number of cache lines fetched +system.cpu.fetch.Cycles 351490 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1163577 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 10080 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.368710 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 265962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 134310 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.700823 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 622555 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.077656 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.946208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 354909 57.01% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36395 5.85% 62.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35829 5.76% 68.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29315 4.71% 73.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 25782 4.14% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22071 3.55% 81.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22996 3.69% 84.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16066 2.58% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 79192 12.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 622555 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 61571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 4789 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 226272 # Number of branches executed +system.cpu.iew.exec_nop 1973 # number of nop insts executed +system.cpu.iew.exec_rate 1.731738 # Inst execution rate +system.cpu.iew.exec_refs 336529 # number of memory reference insts executed +system.cpu.iew.exec_stores 137581 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 18776 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199413 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 143076 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1232740 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 198948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1184727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 75 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4577 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 13404 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 51 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11145 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 22474 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 12581 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 51 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3178 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1611 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1051584 # num instructions consuming a value +system.cpu.iew.wb_count 1169811 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.565495 # average fanout of values written-back +system.cpu.iew.wb_producers 594666 # num instructions producing a value +system.cpu.iew.wb_rate 1.709935 # insts written-back per cycle +system.cpu.iew.wb_sent 1171681 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1338795 # number of integer regfile reads +system.cpu.int_regfile_writes 842064 # number of integer regfile writes +system.cpu.ipc 1.461719 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.461719 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 205 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 843381 70.75% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3830 0.32% 71.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 913 0.08% 71.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 443 0.04% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 22 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 9 0.00% 71.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1911 0.16% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 1 0.00% 71.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 490 0.04% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 729 0.06% 71.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 662 0.06% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 561 0.05% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 71.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 200822 16.85% 88.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138126 11.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1192128 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19491 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016350 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7584 38.91% 38.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 286 1.47% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 16 0.08% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 1 0.01% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 37 0.19% 40.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 3 0.02% 40.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 32 0.16% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 40.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3651 18.73% 59.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7880 40.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1198409 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3001822 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1158219 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1335839 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1230257 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1192128 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 119104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 604 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 91660 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 622555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.914896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.081400 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 224872 36.12% 36.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 111647 17.93% 54.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 80394 12.91% 66.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 65833 10.57% 77.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57137 9.18% 86.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 35638 5.72% 92.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25524 4.10% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9768 1.57% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11742 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 622555 # Number of insts issued each cycle +system.cpu.iq.rate 1.742556 # Inst issue rate +system.cpu.iq.vec_alu_accesses 13005 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 25084 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 11592 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 14079 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 11813 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10481 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 143076 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 814624 # number of misc regfile reads +system.cpu.misc_regfile_writes 2390 # number of misc regfile writes +system.cpu.numCycles 684126 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 20510 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1188200 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 4829 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 245465 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 1607 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 197 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 1901749 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1255514 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1346306 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 248576 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 43450 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4577 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 52052 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 158085 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1414708 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 51375 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2390 # count of serializing insts renamed +system.cpu.rename.skidInsts 24882 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 512 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 11865 # Number of vector rename lookups +system.cpu.rob.rob_reads 1783497 # The number of ROB reads +system.cpu.rob.rob_writes 2481923 # The number of ROB writes +system.cpu.timesIdled 2175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 11159 # number of vector regfile reads +system.cpu.vec_regfile_writes 5976 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1418 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 3 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 3085 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 7097 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1021 # Transaction distribution +system.membus.trans_dist::ReadExReq 385 # Transaction distribution +system.membus.trans_dist::ReadExResp 385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1021 # Transaction distribution +system.membus.trans_dist::InvalidateReq 12 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 89984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1418 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1418 # Request fanout histogram +system.membus.reqLayer0.occupancy 1743000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 7466000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 3603 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 123 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 98 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 397 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 397 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3346 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 257 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 12 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 12 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 9556 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 1553 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 11109 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 397440 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 49728 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 447168 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 4012 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000748 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.027338 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 4009 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 4012 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 6535500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 987499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 5019000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2570 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 24 # number of demand (read+write) hits +system.l2.demand_hits::total 2594 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2570 # number of overall hits +system.l2.overall_hits::.cpu.data 24 # number of overall hits +system.l2.overall_hits::total 2594 # number of overall hits +system.l2.demand_misses::.cpu.inst 776 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 630 # number of demand (read+write) misses +system.l2.demand_misses::total 1406 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 776 # number of overall misses +system.l2.overall_misses::.cpu.data 630 # number of overall misses +system.l2.overall_misses::total 1406 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 61228500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 53298500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 114527000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 61228500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 53298500 # number of overall miss cycles +system.l2.overall_miss_latency::total 114527000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3346 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 654 # number of demand (read+write) accesses +system.l2.demand_accesses::total 4000 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3346 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 654 # number of overall (read+write) accesses +system.l2.overall_accesses::total 4000 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.231919 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.963303 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.351500 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.231919 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.963303 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.351500 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.demand_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78902.706186 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 84600.793651 # average overall miss latency +system.l2.overall_avg_miss_latency::total 81455.903272 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 776 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 630 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1406 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 776 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 630 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1406 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 53468500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 46998500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 100467000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 53468500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 46998500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 100467000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.351500 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.963303 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.351500 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 74600.793651 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 71455.903272 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 123 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 123 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 123 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2862 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2862 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2862 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2862 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 12 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 12 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 385 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 385 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 32903000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 397 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.969773 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 85462.337662 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 385 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 29053000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.969773 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 75462.337662 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2570 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 776 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 61228500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3346 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.231919 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78902.706186 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 776 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 53468500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.231919 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68902.706186 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 12 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 245 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 20395500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 257 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.953307 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 83246.938776 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 245 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 17945500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.953307 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 73246.938776 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_misses::.cpu.data 12 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 12 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 12 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 12 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 230000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19166.666667 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19166.666667 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1147.163949 # Cycle average of tags in use +system.l2.tags.total_refs 7082 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1414 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 5.008487 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 3.100039 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 718.567739 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 425.496172 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000095 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.021929 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.012985 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.035009 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1414 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1307 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.043152 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 58166 # Number of tag accesses +system.l2.tags.data_accesses 58166 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 49664 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 40320 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 89984 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 49664 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 776 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 630 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1406 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 145189841 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 117873196 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 263063037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 145189841 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 145189841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 117873196 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 263063037 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 776.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 630.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000595500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 2857 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1406 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1406 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 188 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.12 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 16247000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 7030000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 42609500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 11555.48 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 30305.48 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1036 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1406 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 925 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 309 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 119 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 366 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 244.459016 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 165.753947 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 253.358390 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 108 29.51% 29.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 154 42.08% 71.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 34 9.29% 80.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21 5.74% 86.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 2.19% 88.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 3.28% 92.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 1.64% 93.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.09% 94.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 19 5.19% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 366 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 89984 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 89984 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 263.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 263.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.06 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.06 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 341590500 # Total gap between requests +system.mem_ctrls.avgGap 242951.99 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 49664 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 40320 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 145189841.037822037935 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 117873195.687922537327 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 776 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 630 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 21553250 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 21056250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27774.81 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 33422.62 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 73.68 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1342320 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 705870 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 4219740 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 142332420 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 11493120 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 186522990 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 545.289209 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 28704750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 302177750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1299480 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5819100 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 26429520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 102551550 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 44992800 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 181775550 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 531.410342 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 116125500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 11180000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 214757000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 188002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 188002 # number of overall hits +system.cpu.icache.overall_hits::total 188002 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3599 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3599 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3599 # number of overall misses +system.cpu.icache.overall_misses::total 3599 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 110804999 # number of demand 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27894.500598 # average overall mshr miss latency +system.cpu.icache.replacements 2864 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 188002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188002 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 3599 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3599 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 110804999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 110804999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 191601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 191601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.018784 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018784 # miss rate for ReadReq accesses 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27894.500598 # average ReadReq mshr miss latency +system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.tagsinuse 455.896294 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 191348 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.187089 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 455.896294 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.890422 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.890422 # Average percentage of cache occupancy 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(read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 191127451 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 191127451 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 191127451 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 303382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 303382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 304639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 304639 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.008188 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008188 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.008164 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008164 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 76943.418277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76943.418277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 76850.603538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76850.603538 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4244 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.136986 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 123 # number of writebacks +system.cpu.dcache.writebacks::total 123 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1821 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 1821 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1821 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 666 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 666 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 54682992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54682992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 54913492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54913492 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.002185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.002186 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002186 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 82478.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82478.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 82452.690691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82452.690691 # average overall mshr miss latency +system.cpu.dcache.replacements 221 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 172595 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 172595 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 770 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 56980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56980000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 173365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 173365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.004441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 74000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 254 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 20680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.001465 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001465 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 81419.291339 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81419.291339 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 128296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128296 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 1706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1706 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 133892953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 133892953 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 130002 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013123 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78483.559789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 33755994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003085 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84179.536160 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1254 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1257 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002387 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 230500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002387 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76833.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 7 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 254498 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 15 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.533333 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31812.250000 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 246498 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.533333 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30812.250000 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 486 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 486 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 475 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 475 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 344.568452 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 303779 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 666 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 456.124625 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 344.568452 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.672985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.869141 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 611866 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 611866 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 342062500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 342062500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/omnetpp/config.ini b/test_run/omnetpp/config.ini new file mode 100644 index 000000000..6994a3926 --- /dev/null +++ b/test_run/omnetpp/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 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+clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//data/ref/input/omnetpp.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/471.omnetpp//exe/omnetpp_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=omnetpp.log +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/omnetpp/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/omnetpp/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/omnetpp/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/omnetpp/config.json b/test_run/omnetpp/config.json new file mode 100644 index 000000000..59eaebaf6 --- /dev/null +++ b/test_run/omnetpp/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/omnetpp/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/omnetpp/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/omnetpp/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.tol2bus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.tol2bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": [], + "path": "system.tol2bus", + "snoop_response_latency": 1, + "name": "tol2bus", + "use_default_range": false + }, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[0]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "itb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.itb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": 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[ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/omnetpp/fs/proc/cpuinfo b/test_run/omnetpp/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/omnetpp/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/omnetpp/fs/proc/stat b/test_run/omnetpp/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/omnetpp/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/omnetpp/fs/sys/devices/system/cpu/online b/test_run/omnetpp/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/omnetpp/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/omnetpp/fs/sys/devices/system/cpu/possible b/test_run/omnetpp/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/omnetpp/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/omnetpp/omnetpp.log b/test_run/omnetpp/omnetpp.log new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/omnetpp/stats.txt b/test_run/omnetpp/stats.txt new file mode 100644 index 000000000..46f486042 --- /dev/null +++ b/test_run/omnetpp/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 600830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 143146 # Simulator instruction rate (inst/s) +host_mem_usage 872264 # Number of bytes of host memory used +host_op_rate 153898 # Simulator op (including micro ops) rate (op/s) +host_seconds 6.99 # Real time elapsed on the host +host_tick_rate 86004196 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1075135 # Number of ops (including micro ops) simulated +sim_seconds 0.000601 # Number of seconds simulated +sim_ticks 600830500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.016583 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 148545 # Number of BTB hits +system.cpu.branchPred.BTBLookups 153113 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6561 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 256294 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1996 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3048 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 1052 # Number of indirect misses. +system.cpu.branchPred.lookups 344799 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 124051 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 60754 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113162 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 71643 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 344 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 45 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 5324 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2167 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 57 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 329 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3284 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1458 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 339 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 3422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 757 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1066 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1083 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 405 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 765 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 867 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 766 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1038 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1241 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 905 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 993 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 494 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 1436 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 209 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 568 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 152787 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 781 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 1385 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 307 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 2578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 552 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 955 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1446 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 4254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 1870 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2792 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1115 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 782 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 948 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 638 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 502 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 452 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 815 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 890 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1314 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1593 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 1083 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 578 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1194 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 24677 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 269 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1362 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 31611 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 517 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 559188 # number of cc regfile reads +system.cpu.cc_regfile_writes 492774 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 4887 # The number of times a branch was mispredicted +system.cpu.commit.branches 250422 # Number of branches committed +system.cpu.commit.bw_lim_events 61679 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 540 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 250346 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1003357 # Number of instructions committed +system.cpu.commit.committedOps 1078492 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1060509 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.016957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.129603 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 743853 70.14% 70.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104575 9.86% 80.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 71710 6.76% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25390 2.39% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28256 2.66% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8269 0.78% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10913 1.03% 93.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5864 0.55% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61679 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1060509 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 24973 # Number of function calls committed. +system.cpu.commit.int_insts 934829 # Number of committed integer instructions. +system.cpu.commit.loads 104843 # Number of loads committed +system.cpu.commit.membars 532 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 12 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 870934 80.75% 80.76% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 40054 3.71% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 22 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 84.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 38 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 47 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 49 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 84.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 47 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 84.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 104843 9.72% 94.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 62445 5.79% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1078492 # Class of committed instruction +system.cpu.commit.refs 167288 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 699 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1075135 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.201662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.201662 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 617643 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1684 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 144015 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1375078 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 199308 # Number of cycles decode is idle +system.cpu.decode.RunCycles 230164 # Number of cycles decode is running +system.cpu.decode.SquashCycles 4951 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 7329 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 42522 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 344799 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 251042 # Number of cache lines fetched +system.cpu.fetch.Cycles 796828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3081 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1341720 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 13250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.286935 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 290887 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182152 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.116554 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.312222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 757448 69.20% 69.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52806 4.82% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72422 6.62% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 31200 2.85% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 29155 2.66% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36050 3.29% 89.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 20265 1.85% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35303 3.23% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59939 5.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1094588 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 107074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 5288 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 292397 # Number of branches executed +system.cpu.iew.exec_nop 3630 # number of nop insts executed +system.cpu.iew.exec_rate 1.036673 # Inst execution rate +system.cpu.iew.exec_refs 190511 # number of memory reference insts executed +system.cpu.iew.exec_stores 68247 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 236197 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131642 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 697 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 72865 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1329304 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8709 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1245730 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1309 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1325 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4951 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5211 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 7688 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2529 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 10420 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2944 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1319747 # num instructions consuming a value +system.cpu.iew.wb_count 1234451 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.515417 # average fanout of values written-back +system.cpu.iew.wb_producers 680220 # num instructions producing a value +system.cpu.iew.wb_rate 1.027286 # insts written-back per cycle +system.cpu.iew.wb_sent 1237611 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1401236 # number of integer regfile reads +system.cpu.int_regfile_writes 922560 # number of integer regfile writes +system.cpu.ipc 0.832181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.832181 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1018643 81.20% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 40062 3.19% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 26 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 54 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 84.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 70 0.01% 84.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 69 0.01% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 57 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 84.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126059 10.05% 94.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 69382 5.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1254440 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 10878 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008672 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8498 78.12% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.02% 78.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 6 0.06% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 78.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 685 6.30% 84.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1687 15.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1264404 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3613205 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1233634 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1575017 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1325083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1254440 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 591 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 250524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 671 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 145632 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1094588 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.146039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.729328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 605474 55.32% 55.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 173599 15.86% 71.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 126763 11.58% 82.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70125 6.41% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 49712 4.54% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23222 2.12% 95.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 26221 2.40% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11120 1.02% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8352 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1094588 # Number of insts issued each cycle +system.cpu.iq.rate 1.043921 # Inst issue rate +system.cpu.iq.vec_alu_accesses 897 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 1811 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 817 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 1221 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 8896 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6565 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 131642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 72865 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 776684 # number of misc regfile reads +system.cpu.misc_regfile_writes 2121 # number of misc regfile writes +system.cpu.numCycles 1201662 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 386132 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1228037 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 116818 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 213486 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 2867 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 5124 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2147241 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1354877 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1542516 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 250910 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7919 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 4951 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 144869 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 314451 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1523758 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 94240 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 2166 # count of serializing insts renamed +system.cpu.rename.skidInsts 218820 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 593 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1144 # Number of vector rename lookups +system.cpu.rob.rob_reads 2327278 # The number of ROB reads +system.cpu.rob.rob_writes 2691796 # The number of ROB writes +system.cpu.timesIdled 1246 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 944 # number of vector regfile reads +system.cpu.vec_regfile_writes 295 # number of vector regfile writes +system.cpu.workload.numSyscalls 9 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 6851 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 6920 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 14864 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 5670 # Transaction distribution +system.membus.trans_dist::ReadExReq 1032 # Transaction distribution +system.membus.trans_dist::ReadExResp 1031 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5670 # Transaction distribution +system.membus.trans_dist::InvalidateReq 149 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 428864 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 6851 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6851 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6851 # Request fanout histogram +system.membus.reqLayer0.occupancy 8063000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 35377250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 6743 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1272 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1208 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 4440 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1049 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1048 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1718 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 5026 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 151 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 151 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 4644 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 18162 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 22806 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 187264 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 470080 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 657344 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 7944 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.011220 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 7943 99.99% 99.99% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 7944 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 9912000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 9185499 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.5 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2577998 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 205 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 886 # number of demand (read+write) hits +system.l2.demand_hits::total 1091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 205 # number of overall hits +system.l2.overall_hits::.cpu.data 886 # number of overall hits +system.l2.overall_hits::total 1091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1513 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 5189 # number of demand (read+write) misses +system.l2.demand_misses::total 6702 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1513 # number of overall misses +system.l2.overall_misses::.cpu.data 5189 # number of overall misses +system.l2.overall_misses::total 6702 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 118284000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 389913000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 508197000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 118284000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 389913000 # number of overall miss cycles +system.l2.overall_miss_latency::total 508197000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1718 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 6075 # number of demand (read+write) accesses +system.l2.demand_accesses::total 7793 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1718 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 6075 # number of overall (read+write) accesses +system.l2.overall_accesses::total 7793 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.880675 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.854156 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.860003 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.880675 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.854156 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.860003 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.demand_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78178.453404 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 75142.223935 # average overall miss latency +system.l2.overall_avg_miss_latency::total 75827.663384 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1513 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 5189 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 6702 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1513 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 5189 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 6702 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 103154000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 338033000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 441187000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 103154000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 338033000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 441187000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.860003 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.854156 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.860003 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 65144.151089 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 65829.155476 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1272 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1272 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1208 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1208 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1208 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1208 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 17 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 17 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 1032 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 1032 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 81513500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1049 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.983794 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 78985.949612 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 1032 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 71203500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.983794 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 68995.639535 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1513 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 118284000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1718 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.880675 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78178.453404 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1513 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 103154000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.880675 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68178.453404 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 869 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 4157 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 308399500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 5026 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.827099 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 74187.996151 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 4157 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 266829500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.827099 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 64187.996151 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 2 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 2 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 149 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 149 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 151 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.986755 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 149 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 2848000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.986755 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19114.093960 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19114.093960 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3524.172320 # Cycle average of tags in use +system.l2.tags.total_refs 14713 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 6852 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.147256 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 103.457419 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1250.327723 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 2170.387178 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.038157 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.066235 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.107549 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 6850 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1057 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 5723 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.209045 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 125756 # Number of tag accesses +system.l2.tags.data_accesses 125756 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 96832 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 332032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 428864 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 96832 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1513 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 5188 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 6701 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 161163589 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 552621746 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 713785335 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 161163589 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 161163589 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 552621746 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 713785335 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1513.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 5189.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000592250 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 13490 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 6702 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 6702 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 366 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 531 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 375 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 330 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 419 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 552 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 349 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 486 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 454 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 472 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 340 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 373 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 566 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 387 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.18 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 40720500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 33510000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 166383000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 6075.87 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 24825.87 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 5865 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.51 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 6702 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 5584 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 809 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 836 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 512.382775 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 327.950498 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 396.797343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 152 18.18% 18.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 165 19.74% 37.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 89 10.65% 48.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 53 6.34% 54.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 52 6.22% 61.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 22 2.63% 63.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 21 2.51% 66.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 22 2.63% 68.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 260 31.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 836 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 428928 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 428928 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 713.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 713.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 600814000 # Total gap between requests +system.mem_ctrls.avgGap 89646.97 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 96832 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 332096 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 161163589.398341149092 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 552728265.292790651321 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1513 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 5189 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 40921500 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 125461500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27046.60 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 24178.36 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2977380 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1578720 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24468780 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 167296710 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 89837760 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 333486630 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 555.042778 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 231136500 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 20020000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 349674000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 2998800 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 23383500 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 47327280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 169256370 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 88187520 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 332747370 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 553.812381 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 227066750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 20020000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 353743750 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 248600 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 248600 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 248600 # number of overall hits +system.cpu.icache.overall_hits::total 248600 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 2440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 2440 # number of overall misses +system.cpu.icache.overall_misses::total 2440 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 160765498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 160765498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 160765498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 160765498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 251040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 251040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 251040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 251040 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.009720 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009720 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.009720 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009720 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 65887.499180 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65887.499180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 65887.499180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65887.499180 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 1208 # number of writebacks +system.cpu.icache.writebacks::total 1208 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 722 # number of demand (read+write) MSHR hits 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latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 62135.917343 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62135.917343 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8845 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.522088 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1272 # number of writebacks +system.cpu.dcache.writebacks::total 1272 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 17188 # number of demand (read+write) MSHR hits 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number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 58103 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 3672 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3672 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 241178421 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241178421 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 61775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 61775 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.059442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 65680.397876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65680.397876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 2612 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2612 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1060 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1060 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 83626987 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83626987 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017159 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 78893.383962 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78893.383962 # average WriteReq mshr miss latency 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184500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92250 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 11 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 140 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4488404 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4488404 # number of WriteLineReq miss cycles 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MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.927152 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31060.028571 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 562 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008897 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 4 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.007117 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 54375 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 530 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 530 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 472.929101 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156727 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 6224 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.181073 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 472.929101 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.923690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 354060 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 354060 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 600830500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 600830500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/perlbench/config.ini b/test_run/perlbench/config.ini new file mode 100644 index 000000000..dee4e1549 --- /dev/null +++ b/test_run/perlbench/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=25000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc 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32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/perlbench/fs/proc/cpuinfo b/test_run/perlbench/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/perlbench/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/perlbench/fs/proc/stat b/test_run/perlbench/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/perlbench/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/perlbench/fs/sys/devices/system/cpu/online b/test_run/perlbench/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/perlbench/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/perlbench/fs/sys/devices/system/cpu/possible b/test_run/perlbench/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/perlbench/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/perlbench/stats.txt b/test_run/perlbench/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/povray/SPEC-benchmark-ref.stdout b/test_run/povray/SPEC-benchmark-ref.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/povray/config.ini b/test_run/povray/config.ini new file mode 100644 index 000000000..fb26d616a --- /dev/null +++ b/test_run/povray/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 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+indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB 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+prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 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+children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/453.povray//exe/povray_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/453.povray//data/ref/input/SPEC-benchmark-ref.ini +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 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+size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 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+lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/povray/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/povray/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/povray/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/povray/config.json b/test_run/povray/config.json new file mode 100644 index 000000000..9293109e8 --- /dev/null +++ b/test_run/povray/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/povray/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/povray/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/povray/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + 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"ArmInterrupts", + "name": "interrupts", + "cxx_class": "ArmISA::Interrupts" + } + ], + "numPhysVecPredRegs": 32, + "cacheLoadPorts": 200, + "smtCommitPolicy": "RoundRobin", + "power_gating_on_idle": false, + "issueToExecuteDelay": 1, + "dtb": { + "stage2_mmu": { + "name": "stage2_mmu", + "tlb": "system.cpu.dtb", + "sys": "system", + "stage2_tlb": { + "name": "stage2_tlb", + "is_stage2": true, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb.stage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dtb.stage2_mmu", + "type": "ArmStage2MMU" + }, + "name": "dtb", + "is_stage2": false, + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "power_model": [], + "sys": "system", + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.cpu.dtb.walker.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.tol2bus.slave[3]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "pwr_gating_latency": 300, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 1280, + "renameToIEWDelay": 2, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "l2": { + "replacement_policy": { + "eventq_index": 0, + "path": "system.l2.replacement_policy", + "type": "LRURP", + "name": "replacement_policy", + "cxx_class": "LRURP" + }, + "cpu_side": { + "peer": "system.tol2bus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "write_allocator": null, + "size": 2097152, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.power_state", + "type": "PowerState", + "leaders": [] + }, + "mem_side": { + "peer": "system.membus.slave[1]", + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "mshrs": 20, + "writeback_clean": false, + "tags": { + "tag_latency": 20, + "replacement_policy": "system.l2.replacement_policy", + "name": "tags", + "eventq_index": 0, + "warmup_percentage": 0, + "clk_domain": "system.cpu_clk_domain", + "indexing_policy": { + "name": "indexing_policy", + "eventq_index": 0, + "assoc": 8, + "cxx_class": "SetAssociative", + "path": "system.l2.tags.indexing_policy", + "entry_size": 64, + "type": "SetAssociative", + "size": 2097152 + }, + "system": "system", + "sequential_access": false, + "assoc": 8, + "power_model": [], + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.l2.tags.power_state", + "type": "PowerState", + "leaders": [] + }, + "cxx_class": "BaseSetAssoc", + "path": "system.l2.tags", + "entry_size": 64, + "block_size": 64, + "type": "BaseSetAssoc", + "size": 2097152 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": [], + "compressor": null, + "is_read_only": false, + "warmup_percentage": 0, + "prefetch_on_access": false, + "path": "system.l2", + "data_latency": 20, + "tag_latency": 20, + "name": "l2", + "addr_ranges": [ + "0:18446744073709551615" + ], + "type": "Cache", + "sequential_access": false, + "assoc": 8 + }, + "cpu_voltage_domain": { + "name": "cpu_voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.cpu_voltage_domain", + "type": "VoltageDomain" + }, + "mem_ctrls": [ + { + "tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/povray/fs/proc/cpuinfo b/test_run/povray/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/povray/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/povray/fs/proc/stat b/test_run/povray/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/povray/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/povray/fs/sys/devices/system/cpu/online b/test_run/povray/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/povray/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/povray/fs/sys/devices/system/cpu/possible b/test_run/povray/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/povray/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/povray/stats.txt b/test_run/povray/stats.txt new file mode 100644 index 000000000..82448706a --- /dev/null +++ b/test_run/povray/stats.txt @@ -0,0 +1,1364 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 440535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 137870 # Simulator instruction rate (inst/s) +host_mem_usage 859768 # Number of bytes of host memory used +host_op_rate 162346 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.25 # Real time elapsed on the host +host_tick_rate 60734951 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000002 # Number of instructions simulated +sim_ops 1177555 # Number of ops (including micro ops) simulated +sim_seconds 0.000441 # Number of seconds simulated +sim_ticks 440535000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 97.198572 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 115989 # Number of BTB hits +system.cpu.branchPred.BTBLookups 119332 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 7435 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 213239 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 1230 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 2181 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 951 # Number of indirect misses. +system.cpu.branchPred.lookups 290314 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 125053 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 46817 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 113188 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 58682 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 918 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 207 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 12467 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 2851 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 3499 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1409 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 3608 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 980 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 1897 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2217 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 1418 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 2515 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1455 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 1565 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 3315 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 2539 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 724 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 912 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 1115 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 1141 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 664 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 235 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 966 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2236 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 375 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 687 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 118623 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2119 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2831 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 3677 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3598 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 3364 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 3420 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 1802 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 3217 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 2303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 2015 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 1788 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 2153 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1816 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 2903 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 2587 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 1068 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1492 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 2976 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 1833 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 1305 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 514 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 729 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 1067 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 43932 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 362 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1603 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 29908 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 306 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 385761 # number of cc regfile reads +system.cpu.cc_regfile_writes 379620 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 6003 # The number of times a branch was mispredicted +system.cpu.commit.branches 236171 # Number of branches committed +system.cpu.commit.bw_lim_events 73367 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 75 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 136896 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000964 # Number of instructions committed +system.cpu.commit.committedOps 1178517 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 736122 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.600981 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.554495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 393460 53.45% 53.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 135494 18.41% 71.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47723 6.48% 78.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 40908 5.56% 83.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13088 1.78% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12972 1.76% 87.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 13065 1.77% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6045 0.82% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73367 9.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 736122 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 25599 # Number of function calls committed. +system.cpu.commit.int_insts 1058462 # Number of committed integer instructions. +system.cpu.commit.loads 219653 # Number of loads committed +system.cpu.commit.membars 58 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 85 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 803955 68.22% 68.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 43 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 8 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 3 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 6 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 24 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 32 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 211 0.02% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 346 0.03% 68.28% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 340 0.03% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 4 0.00% 68.31% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 252 0.02% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 68.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 219653 18.64% 86.97% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 153553 13.03% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1178517 # Class of committed instruction +system.cpu.commit.refs 373206 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2565 # Number of committed Vector instructions. +system.cpu.committedInsts 1000002 # Number of Instructions Simulated +system.cpu.committedOps 1177555 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.881069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881069 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 352277 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1467 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 112500 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1366665 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 166919 # Number of cycles decode is idle +system.cpu.decode.RunCycles 199841 # Number of cycles decode is running +system.cpu.decode.SquashCycles 6169 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 5195 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 31333 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 290314 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 188047 # Number of cache lines fetched +system.cpu.fetch.Cycles 500939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3491 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1223026 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 15202 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.329501 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 247929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 147127 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.388113 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 756539 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.886749 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.851187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458670 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35950 4.75% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45265 5.98% 71.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36757 4.86% 76.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21735 2.87% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 35827 4.74% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 17076 2.26% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19955 2.64% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85304 11.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 756539 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 124532 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 6907 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 248720 # Number of branches executed +system.cpu.iew.exec_nop 1123 # number of nop insts executed +system.cpu.iew.exec_rate 1.425137 # Inst execution rate +system.cpu.iew.exec_refs 396422 # number of memory reference insts executed +system.cpu.iew.exec_stores 160107 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 22254 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 246607 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1641 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 168064 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1316053 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 236315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1255647 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 2356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6169 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2685 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 324 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5311 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 52 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 149 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2782 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 26945 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 14506 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 149 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 4240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2667 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1198971 # num instructions consuming a value +system.cpu.iew.wb_count 1244234 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.560166 # average fanout of values written-back +system.cpu.iew.wb_producers 671623 # num instructions producing a value +system.cpu.iew.wb_rate 1.412184 # insts written-back per cycle +system.cpu.iew.wb_sent 1248252 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1406014 # number of integer regfile reads +system.cpu.int_regfile_writes 902367 # number of integer regfile writes +system.cpu.ipc 1.134985 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134985 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 98 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 864482 68.23% 68.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 11 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 28 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 42 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 235 0.02% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 384 0.03% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 387 0.03% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 4 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 266 0.02% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 239173 18.88% 87.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 161918 12.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1267085 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 19465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015362 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4588 23.57% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 1 0.01% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 5 0.03% 23.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 18 0.09% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525 33.52% 57.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8328 42.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1283510 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3305038 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1241483 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1448868 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1314816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1267085 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 114 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 137324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 746 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 104243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 756539 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.674844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.170087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360054 47.59% 47.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 105577 13.96% 61.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 70744 9.35% 70.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 70123 9.27% 80.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57524 7.60% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29199 3.86% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28653 3.79% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15678 2.07% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18987 2.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 756539 # Number of insts issued each cycle +system.cpu.iq.rate 1.438119 # Inst issue rate +system.cpu.iq.vec_alu_accesses 2942 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 5874 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2751 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 3525 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 3911 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5794 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 246607 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 168064 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 951083 # number of misc regfile reads +system.cpu.misc_regfile_writes 272 # number of misc regfile writes +system.cpu.numCycles 881071 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 35111 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1212533 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 12363 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 181263 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 453 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2001540 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1344395 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1383743 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 215925 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 24594 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 6169 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 58674 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171123 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1509943 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 259397 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 14972 # count of serializing insts renamed +system.cpu.rename.skidInsts 139589 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 132 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 3983 # Number of vector rename lookups +system.cpu.rob.rob_reads 1977635 # The number of ROB reads +system.cpu.rob.rob_writes 2651412 # The number of ROB writes +system.cpu.timesIdled 1992 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 3332 # number of vector regfile reads +system.cpu.vec_regfile_writes 1671 # number of vector regfile writes +system.cpu.workload.numSyscalls 16 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 2830 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 4903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 10828 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 2059 # Transaction distribution +system.membus.trans_dist::ReadExReq 761 # Transaction distribution +system.membus.trans_dist::ReadExResp 761 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2059 # Transaction distribution +system.membus.trans_dist::InvalidateReq 10 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5650 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 180480 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2830 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2830 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2830 # Request fanout histogram +system.membus.reqLayer0.occupancy 3507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 14927500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 4828 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1995 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 2596 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 312 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 1083 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 3108 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1720 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 14 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 14 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 8812 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 7941 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 16753 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 365056 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 307072 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 672128 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 5925 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000169 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.012991 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 5924 99.98% 99.98% # Request fanout histogram +system.tol2bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 5925 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 10005000 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 4211999 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 4662000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1580 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1511 # number of demand (read+write) hits +system.l2.demand_hits::total 3091 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1580 # number of overall hits +system.l2.overall_hits::.cpu.data 1511 # number of overall hits +system.l2.overall_hits::total 3091 # number of overall hits +system.l2.demand_misses::.cpu.inst 1528 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 1292 # number of demand (read+write) misses +system.l2.demand_misses::total 2820 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1528 # number of overall misses +system.l2.overall_misses::.cpu.data 1292 # number of overall misses +system.l2.overall_misses::total 2820 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 120129500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 101875000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 222004500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 120129500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 101875000 # number of overall miss cycles +system.l2.overall_miss_latency::total 222004500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 3108 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2803 # number of demand (read+write) accesses +system.l2.demand_accesses::total 5911 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 3108 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2803 # number of overall (read+write) accesses +system.l2.overall_accesses::total 5911 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.491634 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.460935 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.477077 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.491634 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.460935 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.477077 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78725 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78618.782723 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 78850.619195 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78725 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1528 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 1292 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 2820 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1528 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 1292 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 2820 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 104849500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 88955000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 193804500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 104849500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 88955000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 193804500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.477077 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.460935 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.477077 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 68850.619195 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68725 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1995 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1995 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 2596 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 2596 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 2596 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 2596 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 322 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 322 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 761 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 761 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 59075000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.702678 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 77628.120894 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 761 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 51465000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.702678 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 67628.120894 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1580 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1528 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 120129500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 3108 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.491634 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78618.782723 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1528 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 104849500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.491634 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68618.782723 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 1189 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 531 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 42800000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1720 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.308721 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80602.636535 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37490000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.308721 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70602.636535 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 4 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 4 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 10 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 10 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 14 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.714286 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 10 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 188000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.714286 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 18800 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 18800 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1655.197760 # Cycle average of tags in use +system.l2.tags.total_refs 10817 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 2833 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 3.818214 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 6.404433 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1024.255259 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 624.538068 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000195 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.031258 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.019059 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.050513 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 2829 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 670 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 2156 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.086334 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 89449 # Number of tag accesses +system.l2.tags.data_accesses 89449 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 97792 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 82688 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 180480 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 97792 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1528 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 1292 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 2820 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 221984632 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 187699048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 409683680 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 221984632 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 221984632 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 187699048 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 409683680 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1528.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 1292.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000578500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 5675 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 2820 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 2820 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 134 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 298 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 133 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 216 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 289 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 221 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 141 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 130 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 137 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 179 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 183 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 24911000 # Total ticks spent queuing +system.mem_ctrls.totBusLat 14100000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 77786000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8833.69 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27583.69 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2231 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.11 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 2820 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1806 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 666 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 261 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 73 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an 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does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue 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# What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 588 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 306.829932 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 191.362404 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 311.414367 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 186 31.63% 31.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 157 26.70% 58.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 86 14.63% 72.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 38 6.46% 79.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 23 3.91% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 1.36% 84.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 17 2.89% 87.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 18 3.06% 90.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 55 9.35% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 588 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 180480 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 180480 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 409.68 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 409.68 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.20 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 437498000 # Total gap between requests +system.mem_ctrls.avgGap 155141.13 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 97792 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 82688 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 221984632.322062969208 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 187699047.748760044575 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1528 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 1292 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 41993750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 35792250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27482.82 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 27702.98 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 79.11 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 2241960 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 1187835 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 10695720 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 144782850 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 47243040 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 240571245 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 546.088835 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 121360750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 304614250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1963500 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 1043625 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 9439080 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 34419840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 141036240 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 50398080 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 238300365 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 540.934012 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 129731500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 14560000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 296243500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 184461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 184461 # number of overall hits +system.cpu.icache.overall_hits::total 184461 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 3585 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3585 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 3585 # number of overall misses +system.cpu.icache.overall_misses::total 3585 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 168059999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 168059999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 168059999 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 188046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188046 # number of demand (read+write) accesses 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blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 79.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 2596 # number of writebacks +system.cpu.icache.writebacks::total 2596 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 477 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 477 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 477 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 477 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 3108 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3108 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 3108 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3108 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 141521999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 141521999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 141521999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 141521999 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 45534.748713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45534.748713 # average overall mshr miss latency +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 184461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184461 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 3585 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3585 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 168059999 # number of ReadReq miss cycles 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+system.cpu.icache.tags.avg_refs 60.350386 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 87500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::.cpu.inst 474.750503 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::.cpu.inst 0.927247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.927247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379200 # Number of tag accesses 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number of overall hits +system.cpu.dcache.overall_hits::total 372567 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 9926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 9954 # number of overall misses +system.cpu.dcache.overall_misses::total 9954 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 439411405 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 439411405 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 439411405 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 439411405 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 381726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 381726 # number of demand (read+write) accesses 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was blocked +system.cpu.dcache.blocked_cycles::no_targets 1075 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 333 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 20 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.969970 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.750000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 1995 # number of writebacks +system.cpu.dcache.writebacks::total 1995 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 7137 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7137 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 7137 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7137 # number of overall MSHR hits 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+system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007362 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 43679.629975 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43679.629975 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 43538.348011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43538.348011 # average overall mshr miss latency +system.cpu.dcache.replacements 2307 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223323 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4711 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 159264500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 228034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33806.941201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 57217500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33816.489362 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148477 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5208 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 279924408 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 153685 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53748.926267 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 64389491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59072.927523 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 767 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 28 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035220 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 27 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 781500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.033962 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 28944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 222497 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31785.285714 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 215497 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30785.285714 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 210500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 72 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.027778 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 105250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.013889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 108500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 58 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 58 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 411.700494 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 375512 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 133.302094 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 411.700494 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804103 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 768119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 768119 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 440535000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 440535000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/sjeng/config.ini b/test_run/sjeng/config.ini new file mode 100644 index 000000000..ededcfd48 --- /dev/null +++ b/test_run/sjeng/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + 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+pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 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+eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross /home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//data/ref/input/ref.txt +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/458.sjeng//exe/sjeng_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/sjeng/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/sjeng/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/sjeng/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/sjeng/config.json b/test_run/sjeng/config.json new file mode 100644 index 000000000..02ee76497 --- /dev/null +++ b/test_run/sjeng/config.json @@ -0,0 +1,1811 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/sjeng/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/sjeng/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/sjeng/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "tol2bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 32, + "master": { + "peer": [ + "system.l2.cpu_side" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": 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"tBURST_MAX": 5000, + "dll": true, + "tBURST_MIN": 5000, + "max_accesses_per_row": 16, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.mem_ctrls.power_state", + "type": "PowerState", + "leaders": [] + }, + "IDD62": 0.0, + "tCCD_L": 0, + "IDD2P1": 0.032, + "IDD2P0": 0.0, + "IDD4W2": 0.0, + "tCS": 2500, + "power_model": [], + "qos_priority_escalation": false, + "tCL": 13750, + "tCK": 1250, + "tBURST": 5000, + "image_file": "", + "IDD3P0": 0.0, + "IDD3P1": 0.038, + "name": "mem_ctrls", + "device_size": 536870912, + "tREFI": 7800000, + "qos_policy": null, + "tXPDLL": 0, + "tRFC": 260000, + "qos_priorities": 1, + "IDD52": 0.0, + "write_low_thresh_perc": 50, + "write_buffer_size": 64, + "VDD": 1.5, + "write_high_thresh_perc": 85, + "IDD2N2": 0.0, + "port": { + "peer": "system.membus.master[0]", + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "IDD4R": 0.157, + "IDD4W": 0.125, + "tWR": 15000, + "banks_per_rank": 8, + "tXAW": 30000, + "qos_masters": [ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/sjeng/fs/proc/cpuinfo b/test_run/sjeng/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/sjeng/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/sjeng/fs/proc/stat b/test_run/sjeng/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/sjeng/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/sjeng/fs/sys/devices/system/cpu/online b/test_run/sjeng/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/sjeng/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/sjeng/fs/sys/devices/system/cpu/possible b/test_run/sjeng/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/sjeng/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/sjeng/ref.out b/test_run/sjeng/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/sjeng/stats.txt b/test_run/sjeng/stats.txt new file mode 100644 index 000000000..91476e7ea --- /dev/null +++ b/test_run/sjeng/stats.txt @@ -0,0 +1,1415 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 980748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 106199 # Simulator instruction rate (inst/s) +host_mem_usage 855280 # Number of bytes of host memory used +host_op_rate 106934 # Simulator op (including micro ops) rate (op/s) +host_seconds 9.42 # Real time elapsed on the host +host_tick_rate 104151735 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000001 # Number of instructions simulated +sim_ops 1006944 # Number of ops (including micro ops) simulated +sim_seconds 0.000981 # Number of seconds simulated +sim_ticks 980748500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.766989 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 200381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 200849 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 660 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 202147 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 162 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 162 # Number of indirect misses. +system.cpu.branchPred.lookups 207743 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 3582 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 126240 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 3154 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 126668 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 44 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 8 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 824 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 236 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1412 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 591 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 893 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1040 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 225 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 362 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 238 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 2732 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 3784 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 171 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 4198 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 10706 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 5 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 413 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 561 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 2 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 239 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 267 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 0 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 33 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 100795 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 291 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 114 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 581 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 242 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 123 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 2000 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 18 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 916 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 133 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 1438 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 2770 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 201 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 16 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 3784 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 4198 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 171 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 1 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 10709 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 254 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 162 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 561 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 32 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 210 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 28293 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 9 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 41 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 2330 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 42 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 763581 # number of cc regfile reads +system.cpu.cc_regfile_writes 763725 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 463 # The number of times a branch was mispredicted +system.cpu.commit.branches 134686 # Number of branches committed +system.cpu.commit.bw_lim_events 49449 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 31 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 198975 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000027 # Number of instructions committed +system.cpu.commit.committedOps 1006970 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 1903352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.581430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1624847 85.37% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 85631 4.50% 89.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12379 0.65% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 49231 2.59% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 58284 3.06% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21793 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 971 0.05% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 767 0.04% 97.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 49449 2.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1903352 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 2158 # Number of function calls committed. +system.cpu.commit.int_insts 879162 # Number of committed integer instructions. +system.cpu.commit.loads 161698 # Number of loads committed +system.cpu.commit.membars 20 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 625681 62.14% 62.14% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 633 0.06% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 2 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 19 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 23 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 62.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161698 16.06% 78.26% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 218868 21.74% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1006970 # Class of committed instruction +system.cpu.commit.refs 380566 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 339 # Number of committed Vector instructions. +system.cpu.committedInsts 1000001 # Number of Instructions Simulated +system.cpu.committedOps 1006944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.961496 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.961496 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 1647816 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 202 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 185395 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1239183 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 79217 # Number of cycles decode is idle +system.cpu.decode.RunCycles 142072 # Number of cycles decode is running +system.cpu.decode.SquashCycles 1988 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 753 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 57398 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 207743 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 64422 # Number of cache lines fetched +system.cpu.fetch.Cycles 1852627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 408 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1295277 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4370 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.105910 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 73603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 202711 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.660351 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.676031 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.761491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1643977 85.25% 85.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3025 0.16% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25385 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1234 0.06% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 190628 9.88% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4849 0.25% 96.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6124 0.32% 97.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3430 0.18% 97.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 49839 2.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1928491 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 33007 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 539 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 184716 # Number of branches executed +system.cpu.iew.exec_nop 50 # number of nop insts executed +system.cpu.iew.exec_rate 0.617105 # Inst execution rate +system.cpu.iew.exec_refs 432521 # number of memory reference insts executed +system.cpu.iew.exec_stores 268651 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 24614 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 162739 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 269164 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1211943 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 163870 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 682 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1210451 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 80974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1988 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 81014 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 79369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3749 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1041 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 50295 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 396 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 143 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1569905 # num instructions consuming a value +system.cpu.iew.wb_count 1161920 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.418041 # average fanout of values written-back +system.cpu.iew.wb_producers 656285 # num instructions producing a value +system.cpu.iew.wb_rate 0.592364 # insts written-back per cycle +system.cpu.iew.wb_sent 1208711 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1602908 # number of integer regfile reads +system.cpu.int_regfile_writes 757605 # number of integer regfile writes +system.cpu.ipc 0.509815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.509815 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 777546 64.20% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 635 0.05% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 1 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 27 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 28 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 64.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 164047 13.54% 77.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 268787 22.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1211134 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 23303 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019241 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 569 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 2 0.01% 2.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 3 0.01% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21971 94.28% 96.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 758 3.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1233956 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4373200 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1161517 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1416130 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1211854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1211134 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 204944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 237898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 1928491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.628022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.395842 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1513888 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 121000 6.27% 84.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31671 1.64% 86.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 101187 5.25% 91.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 108415 5.62% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28444 1.47% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 20642 1.07% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2453 0.13% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 791 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1928491 # Number of insts issued each cycle +system.cpu.iq.rate 0.617454 # Inst issue rate +system.cpu.iq.vec_alu_accesses 474 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 946 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 403 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 719 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 2099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2216 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 162739 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 269164 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1877143 # number of misc regfile reads +system.cpu.misc_regfile_writes 81 # number of misc regfile writes +system.cpu.numCycles 1961498 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 106316 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1270067 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 7588 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 100412 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 180 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2955535 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1213947 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1526987 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 176735 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 1527719 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 1988 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 1538180 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 256905 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1606307 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 4860 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 99 # count of serializing insts renamed +system.cpu.rename.skidInsts 379312 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 640 # Number of vector rename lookups +system.cpu.rob.rob_reads 3040140 # The number of ROB reads +system.cpu.rob.rob_writes 2437041 # The number of ROB writes +system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 458 # number of vector regfile reads +system.cpu.vec_regfile_writes 126 # number of vector regfile writes +system.cpu.workload.numSyscalls 10 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 65557 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 164732 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 98357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 350 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 197581 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 350 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 537 # Transaction distribution +system.membus.trans_dist::WritebackDirty 65372 # Transaction distribution +system.membus.trans_dist::CleanEvict 168 # Transaction distribution +system.membus.trans_dist::ReadExReq 2717 # Transaction distribution +system.membus.trans_dist::ReadExResp 2717 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 537 # Transaction distribution +system.membus.trans_dist::InvalidateReq 95921 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 167969 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4392064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 99175 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 99175 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 99175 # Request fanout histogram +system.membus.reqLayer0.occupancy 436705000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 44.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17318250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 563 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 163555 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 71 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 624 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 2736 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 421 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 142 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 95925 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 95922 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 913 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 295889 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 296802 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 6467712 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 6499200 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 65893 # Total snoops (count) +system.tol2bus.snoopTraffic 4184000 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 165117 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.002126 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.046057 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 164766 99.79% 99.79% # Request fanout histogram +system.tol2bus.snoop_fanout::1 351 0.21% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 165117 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 197041500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 20.1 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 52278000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 5.3 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 631500 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 6 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 39 # number of demand (read+write) hits +system.l2.demand_hits::total 45 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 6 # number of overall hits +system.l2.overall_hits::.cpu.data 39 # number of overall hits +system.l2.overall_hits::total 45 # number of overall hits +system.l2.demand_misses::.cpu.inst 415 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 2839 # number of demand (read+write) misses +system.l2.demand_misses::total 3254 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 415 # number of overall misses +system.l2.overall_misses::.cpu.data 2839 # number of overall misses +system.l2.overall_misses::total 3254 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 32613000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 227186000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 259799000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 32613000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 227186000 # number of overall miss cycles +system.l2.overall_miss_latency::total 259799000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 421 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 2878 # number of demand (read+write) accesses +system.l2.demand_accesses::total 3299 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 421 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 2878 # number of overall (read+write) accesses +system.l2.overall_accesses::total 3299 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.985748 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.986449 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.986360 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.985748 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.986449 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.986360 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.demand_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78585.542169 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 80023.247622 # average overall miss latency +system.l2.overall_avg_miss_latency::total 79839.889367 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.writebacks::.writebacks 65375 # number of writebacks +system.l2.writebacks::total 65375 # number of writebacks +system.l2.demand_mshr_misses::.cpu.inst 415 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 2839 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 3254 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 415 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 2839 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 3254 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 28463000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 198796000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 227259000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 28463000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 198796000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 227259000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.986360 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.986449 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.986360 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 70023.247622 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 69839.889367 # average overall mshr miss latency +system.l2.replacements 65893 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 98180 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 98180 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 71 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 71 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 71 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 71 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 19 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 19 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 2717 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 2717 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 216717000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 2736 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.993056 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 79763.341921 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 2717 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 189547000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 69763.341921 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 415 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 32613000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 421 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.985748 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78585.542169 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 415 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 28463000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.985748 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68585.542169 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 122 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 10469000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 142 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.859155 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 85811.475410 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 122 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 9249000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.859155 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 75811.475410 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 1 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 1 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 95924 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 95925 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.999990 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 95924 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 1867311000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.999990 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19466.567282 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19466.567282 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 23292.165447 # Cycle average of tags in use +system.l2.tags.total_refs 101656 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 98662 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 1.030346 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 22101.183594 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 161.770983 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1029.210870 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.674475 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.004937 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.031409 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.710820 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 1194 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 10740 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 20834 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 1679302 # Number of tag accesses +system.l2.tags.data_accesses 1679302 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 26560 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 181696 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 208256 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 26560 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_written::.writebacks 4183808 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4183808 # Number of bytes written to this memory +system.mem_ctrls.num_reads::.cpu.inst 415 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 2839 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 3254 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::.writebacks 65372 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 65372 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 27081357 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 185262583 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 212343939 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 27081357 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::.writebacks 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 4265933621 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.writebacks 4265933621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 27081357 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 185262583 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4478277560 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.writebacks::samples 65372.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.inst::samples 415.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 2839.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000056666500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 592 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 592 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 16022 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 67132 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 3254 # Number of read requests accepted +system.mem_ctrls.writeReqs 65372 # Number of write requests accepted +system.mem_ctrls.readBursts 3254 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 65372 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 274 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 184 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 191 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 189 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 176 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 207 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 217 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 187 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 178 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 308 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 302 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 4057 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 4030 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 3888 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3947 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 4046 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 4088 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 4091 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 4144 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 4157 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 4156 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 4121 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 4096 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 4102 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 4228 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 4107 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 16.38 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 31713500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 16270000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 92726000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 9746.00 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28496.00 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 17 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 2870 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 61148 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 88.20 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 93.54 # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 3254 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 65372 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1468 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 1234 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 491 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 593 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1170 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2364 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1702 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 4354 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3585 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 5869 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 4237 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 6370 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 5698 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 5444 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 5067 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3054 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2674 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 1493 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 929 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 275 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 260 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 266 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 202 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 299 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 277 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 304 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 289 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 328 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 278 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 282 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 325 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 283 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 270 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 292 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 232 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 298 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 298 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 209 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 225 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 174 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 113 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 63 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 54 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 4587 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 956.986266 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 889.505183 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 215.926431 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 106 2.31% 2.31% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 81 1.77% 4.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 52 1.13% 5.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 90 1.96% 7.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 37 0.81% 7.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 38 0.83% 8.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 32 0.70% 9.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 64 1.40% 10.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4087 89.10% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4587 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 592 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 5.496622 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 133.738576 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-127 591 99.83% 99.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::3200-3327 1 0.17% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 592 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 592 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 110.395270 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 97.326672 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 53.606284 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16-23 9 1.52% 1.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24-31 17 2.87% 4.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32-39 10 1.69% 6.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40-47 3 0.51% 6.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48-55 73 12.33% 18.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::56-63 2 0.34% 19.26% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::64-71 7 1.18% 20.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::72-79 2 0.34% 20.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::80-87 108 18.24% 39.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::88-95 3 0.51% 39.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::96-103 6 1.01% 40.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::104-111 8 1.35% 41.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::112-119 104 17.57% 59.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::120-127 2 0.34% 59.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::128-135 172 29.05% 88.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::168-175 13 2.20% 91.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::176-183 9 1.52% 92.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::184-191 6 1.01% 93.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::192-199 9 1.52% 95.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::200-207 3 0.51% 95.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::216-223 1 0.17% 95.78% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::248-255 2 0.34% 96.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::256-263 2 0.34% 96.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::264-271 3 0.51% 96.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::272-279 8 1.35% 98.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::288-295 1 0.17% 98.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::296-303 4 0.68% 99.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::304-311 2 0.34% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::312-319 3 0.51% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 592 # Writes before turning the bus around for reads +system.mem_ctrls.bytesReadDRAM 208256 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 4182656 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 208256 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4183808 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 212.34 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 4264.76 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 212.34 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 4265.93 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 34.98 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.66 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 33.32 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 980732500 # Total gap between requests +system.mem_ctrls.avgGap 14290.98 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 26560 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 181696 # Per-master bytes read from memory +system.mem_ctrls.masterWriteBytes::.writebacks 4182656 # Per-master bytes write to memory +system.mem_ctrls.masterReadRate::.cpu.inst 27081356.739265978336 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 185262582.609099060297 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterWriteRate::.writebacks 4264759008.043346405029 # Per-master bytes write to memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 415 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 2839 # Per-master read serviced memory accesses +system.mem_ctrls.masterWriteAccesses::.writebacks 65372 # Per-master write serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 11386750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 81339250 # Per-master read total memory access latency +system.mem_ctrls.masterWriteTotalLat::.writebacks 18580665500 # Per-master write total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27437.95 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 28650.67 # Per-master read average memory access latency +system.mem_ctrls.masterWriteAvgLat::.writebacks 284229.72 # Per-master write average memory access latency +system.mem_ctrls.pageHitRate 93.29 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 16529100 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 8774040 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 12580680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 172578420 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 76830000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 274550760 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 145406880 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 707249880 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 721.132767 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 366755250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 32500000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states 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# average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10303500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10303500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.000870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 74663.043478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74663.043478 # average ReadReq mshr miss latency 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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80829.801532 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 5 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 8 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.375000 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 262000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 87333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 95921 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 3167256066 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 95921 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 33019.422921 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 95921 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 3071339066 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 32019.464622 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 344500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 344500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 343500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 343500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 20 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 20 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 500.623213 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 357948 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 98800 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.622955 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 500.623213 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.977780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 512 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 853742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 853742 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 980748500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 980748500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/soplex/config.ini b/test_run/soplex/config.ini new file mode 100644 index 000000000..534ff0244 --- /dev/null +++ b/test_run/soplex/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 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+tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/450.soplex//exe/soplex_base.amd64-armcross -m10000 /home/min/a/ece565/benchspec-2020/CPU2006/450.soplex//data/ref/input/ref.mps +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/450.soplex//exe/soplex_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=test.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/soplex/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/soplex/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/soplex/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/soplex/config.json b/test_run/soplex/config.json new file mode 100644 index 000000000..362981cf2 --- /dev/null +++ b/test_run/soplex/config.json @@ -0,0 +1,1687 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/soplex/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/soplex/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/soplex/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.cpu_voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + 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-1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/soplex/fs/proc/cpuinfo b/test_run/soplex/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/soplex/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/soplex/fs/proc/stat b/test_run/soplex/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/soplex/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/soplex/fs/sys/devices/system/cpu/online b/test_run/soplex/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/soplex/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/soplex/fs/sys/devices/system/cpu/possible b/test_run/soplex/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/soplex/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/soplex/stats.txt b/test_run/soplex/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/specrand_f/config.ini b/test_run/specrand_f/config.ini new file mode 100644 index 000000000..0098d88b1 --- /dev/null +++ b/test_run/specrand_f/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + 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+issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 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system.cpu.fuPool.FUList8.opList3 + +[system.cpu.fuPool.FUList8.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList9] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/999.specrand//exe/specrand_f_base.amd64-armcross 324342 24239 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/999.specrand//exe/specrand_f_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=rand.24239.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/specrand_f/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/specrand_f/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/specrand_f/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/specrand_f/config.json b/test_run/specrand_f/config.json new file mode 100644 index 000000000..3ddfbdf80 --- /dev/null +++ b/test_run/specrand_f/config.json @@ -0,0 +1,1687 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/specrand_f/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/specrand_f/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/specrand_f/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + 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32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/specrand_f/fs/proc/cpuinfo b/test_run/specrand_f/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/specrand_f/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/specrand_f/fs/proc/stat b/test_run/specrand_f/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/specrand_f/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/specrand_f/fs/sys/devices/system/cpu/online b/test_run/specrand_f/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/specrand_f/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/specrand_f/fs/sys/devices/system/cpu/possible b/test_run/specrand_f/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/specrand_f/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/specrand_f/stats.txt b/test_run/specrand_f/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/specrand_i/config.ini b/test_run/specrand_i/config.ini new file mode 100644 index 000000000..3f641a7ee --- /dev/null +++ b/test_run/specrand_i/config.ini @@ -0,0 +1,1266 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +children=indirectBranchPred +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] 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+addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/998.specrand//exe/specrand_i_base.amd64-armcross 324342 24239 +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/998.specrand//exe/specrand_i_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=rand.24239.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/specrand_i/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/specrand_i/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/specrand_i/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/specrand_i/config.json b/test_run/specrand_i/config.json new file mode 100644 index 000000000..ee7c518a7 --- /dev/null +++ b/test_run/specrand_i/config.json @@ -0,0 +1,1687 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": 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"device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/specrand_i/fs/proc/cpuinfo b/test_run/specrand_i/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/specrand_i/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/specrand_i/fs/proc/stat b/test_run/specrand_i/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/specrand_i/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/specrand_i/fs/sys/devices/system/cpu/online b/test_run/specrand_i/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/specrand_i/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/specrand_i/fs/sys/devices/system/cpu/possible b/test_run/specrand_i/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/specrand_i/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/specrand_i/stats.txt b/test_run/specrand_i/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/sphinx3/an4.out b/test_run/sphinx3/an4.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/sphinx3/config.ini b/test_run/sphinx3/config.ini new file mode 100644 index 000000000..ceb884f80 --- /dev/null +++ b/test_run/sphinx3/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls 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+commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 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+eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/482.sphinx3/run/sphinx_livepretend_base.amd64-armcross ctlfile . args.an4 +cwd=/home/min/a/ece565/benchspec-2020/CPU2006/482.sphinx3/run/ +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/482.sphinx3/run/sphinx_livepretend_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=an4.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/sphinx3/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/sphinx3/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/sphinx3/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/sphinx3/config.json b/test_run/sphinx3/config.json new file mode 100644 index 000000000..b7906d7e2 --- /dev/null +++ b/test_run/sphinx3/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/sphinx3/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "test_run/sphinx3/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "test_run/sphinx3/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": 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b/test_run/sphinx3/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/sphinx3/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/sphinx3/fs/proc/stat b/test_run/sphinx3/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/sphinx3/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/sphinx3/fs/sys/devices/system/cpu/online b/test_run/sphinx3/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/sphinx3/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/sphinx3/fs/sys/devices/system/cpu/possible b/test_run/sphinx3/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/sphinx3/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/sphinx3/stats.txt b/test_run/sphinx3/stats.txt new file mode 100644 index 000000000..65c4de2f4 --- /dev/null +++ b/test_run/sphinx3/stats.txt @@ -0,0 +1,1362 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 262124000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 195982 # Simulator instruction rate (inst/s) +host_mem_usage 855596 # Number of bytes of host memory used +host_op_rate 210193 # Simulator op (including micro ops) rate (op/s) +host_seconds 5.10 # Real time elapsed on the host +host_tick_rate 51369489 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1072552 # Number of ops (including micro ops) simulated +sim_seconds 0.000262 # Number of seconds simulated +sim_ticks 262124000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 96.464447 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 63381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 65704 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 3839 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 95325 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 994 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 1699 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 705 # Number of indirect misses. +system.cpu.branchPred.lookups 140686 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 46115 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 33541 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 45341 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 34315 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 321 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 103 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 1573 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 1223 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 453 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 208 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1422 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 125 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 99 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 258 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 269 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 265 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 114 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 113 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 69 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 103 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 55 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 74 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 58 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 71 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 111 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 76 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 103 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 667 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 99 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 401 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 70432 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1312 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 390 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 164 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 1364 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 381 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 692 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 167 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 1655 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 216 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 152 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 354 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 127 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 101 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 107 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 79 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 46 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 55 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 109 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 77 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 77 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 140 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 144 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 5369 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 174 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 463 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 18625 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 220 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 179476 # number of cc regfile reads +system.cpu.cc_regfile_writes 176795 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 3085 # The number of times a branch was mispredicted +system.cpu.commit.branches 119983 # Number of branches committed +system.cpu.commit.bw_lim_events 96974 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 228 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 61655 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1000505 # Number of instructions committed +system.cpu.commit.committedOps 1073057 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 418375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.564821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.292903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194354 46.45% 46.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 59808 14.30% 60.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29677 7.09% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8925 2.13% 69.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5687 1.36% 71.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12453 2.98% 74.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7164 1.71% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3333 0.80% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 96974 23.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 418375 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 17242 # Number of function calls committed. +system.cpu.commit.int_insts 734201 # Number of committed integer instructions. +system.cpu.commit.loads 142765 # Number of loads committed +system.cpu.commit.membars 204 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 116 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 548333 51.10% 51.11% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3271 0.30% 51.42% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 457 0.04% 51.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 71130 6.63% 58.09% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 4 0.00% 58.09% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 22496 2.10% 60.18% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 48537 4.52% 64.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 149838 13.96% 78.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3 0.00% 78.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 40433 3.77% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 82.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 276 0.03% 82.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 82.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 332 0.03% 82.50% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 300 0.03% 82.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 82.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 333 0.03% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 82.55% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 142765 13.30% 95.86% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 44433 4.14% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1073057 # Class of committed instruction +system.cpu.commit.refs 187198 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 433458 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1072552 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.524249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.524249 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 54009 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 772 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 62851 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1160527 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 156875 # Number of cycles decode is idle +system.cpu.decode.RunCycles 209741 # Number of cycles decode is running +system.cpu.decode.SquashCycles 3188 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 2606 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 4140 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 140686 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 126273 # Number of cache lines fetched +system.cpu.fetch.Cycles 256214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2031 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1099785 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 7884 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.268357 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 167713 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 83000 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.097829 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 427953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.767416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 205833 48.10% 48.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13163 3.08% 51.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34349 8.03% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25506 5.96% 65.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21816 5.10% 70.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 10056 2.35% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 22547 5.27% 77.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4345 1.02% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 90338 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 427953 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 96296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 3849 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 126141 # Number of branches executed +system.cpu.iew.exec_nop 623 # number of nop insts executed +system.cpu.iew.exec_rate 2.123289 # Inst execution rate +system.cpu.iew.exec_refs 199745 # number of memory reference insts executed +system.cpu.iew.exec_stores 46919 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 19278 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 153387 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 274 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1244 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 50232 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1134863 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 152826 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1113132 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 160 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 731 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3188 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1021 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 277 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 2573 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 92 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1848 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 10609 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5799 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 92 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1474 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1358128 # num instructions consuming a value +system.cpu.iew.wb_count 1106645 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.631922 # average fanout of values written-back +system.cpu.iew.wb_producers 858231 # num instructions producing a value +system.cpu.iew.wb_rate 2.110915 # insts written-back per cycle +system.cpu.iew.wb_sent 1108482 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 843864 # number of integer regfile reads +system.cpu.int_regfile_writes 556092 # number of integer regfile writes +system.cpu.ipc 1.907491 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.907491 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 134 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 578928 51.75% 51.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 3335 0.30% 52.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 483 0.04% 52.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 71137 6.36% 58.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 58.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 22501 2.01% 60.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 48544 4.34% 64.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 149850 13.40% 78.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3 0.00% 78.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 40472 3.62% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 320 0.03% 81.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 81.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 381 0.03% 81.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 342 0.03% 81.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 81.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 385 0.03% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153991 13.77% 95.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 47790 4.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1118601 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 39140 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034990 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2336 5.97% 5.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 523 1.34% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 9434 24.10% 31.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 8931 22.82% 54.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 54.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 13417 34.28% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 1 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 1 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 88.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1557 3.98% 92.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2940 7.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 691665 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1804991 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 672835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 760861 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1133966 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1118601 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 274 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 61589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 796 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 41055 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 427953 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.613841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.212838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102583 23.97% 23.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 51282 11.98% 35.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69011 16.13% 52.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 68408 15.98% 68.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52050 12.16% 80.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33459 7.82% 88.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21697 5.07% 93.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17308 4.04% 97.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12155 2.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 427953 # Number of insts issued each cycle +system.cpu.iq.rate 2.133721 # Inst issue rate +system.cpu.iq.vec_alu_accesses 465942 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 900090 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 433810 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 435056 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 1920 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2168 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 153387 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 50232 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1655966 # number of misc regfile reads +system.cpu.misc_regfile_writes 292823 # number of misc regfile writes +system.cpu.numCycles 524249 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 23162 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1424093 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 2569 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 160142 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 521 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 578 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2968369 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1150360 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1504695 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 210258 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 5064 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 3188 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 10163 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 80438 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 889297 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 21040 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 987 # count of serializing insts renamed +system.cpu.rename.skidInsts 17013 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 274 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 720945 # Number of vector rename lookups +system.cpu.rob.rob_reads 1455684 # The number of ROB reads +system.cpu.rob.rob_writes 2279181 # The number of ROB writes +system.cpu.timesIdled 1397 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 719978 # number of vector regfile reads +system.cpu.vec_regfile_writes 436284 # number of vector regfile writes +system.cpu.workload.numSyscalls 23 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1903 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 3 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 2245 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 5451 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1527 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution +system.membus.trans_dist::ReadExResp 182 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1527 # Transaction distribution +system.membus.trans_dist::InvalidateReq 194 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 3612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 109376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 109376 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1903 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1903 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1903 # Request fanout histogram +system.membus.reqLayer0.occupancy 2366500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 9057750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 2741 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 308 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 1763 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 174 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 217 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 217 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 2272 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 469 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 248 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 248 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 6307 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 2350 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 8657 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 258240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 63616 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 321856 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 0 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 3206 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000936 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.030580 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 3203 99.91% 99.91% # Request fanout histogram +system.tol2bus.snoop_fanout::1 3 0.09% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 3206 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 4796500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 1153000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 3408000 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 1082 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 167 # number of demand (read+write) hits +system.l2.demand_hits::total 1249 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 1082 # number of overall hits +system.l2.overall_hits::.cpu.data 167 # number of overall hits +system.l2.overall_hits::total 1249 # number of overall hits +system.l2.demand_misses::.cpu.inst 1190 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 519 # number of demand (read+write) misses +system.l2.demand_misses::total 1709 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1190 # number of overall misses +system.l2.overall_misses::.cpu.data 519 # number of overall misses +system.l2.overall_misses::total 1709 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 92408500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 42177500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 134586000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 92408500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 42177500 # number of overall miss cycles +system.l2.overall_miss_latency::total 134586000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 2272 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 686 # number of demand (read+write) accesses +system.l2.demand_accesses::total 2958 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 2272 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 686 # number of overall (read+write) accesses +system.l2.overall_accesses::total 2958 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.523768 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.756560 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.577755 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.523768 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.756560 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.577755 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 77654.201681 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 81266.859345 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78751.316559 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 77654.201681 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 81266.859345 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78751.316559 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1190 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 519 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 1709 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1190 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 519 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 1709 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 80508500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 36987500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 117496000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 80508500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 36987500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 117496000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.756560 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.577755 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.756560 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.577755 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 71266.859345 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68751.316559 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 71266.859345 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68751.316559 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 308 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 308 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 308 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 308 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 1762 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 1762 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 1762 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 1762 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 35 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 35 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 182 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 182 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 15019500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 15019500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 217 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 217 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.838710 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.838710 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 82524.725275 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 82524.725275 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 182 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 182 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 13199500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 13199500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.838710 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.838710 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 72524.725275 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 72524.725275 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 1082 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 1082 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1190 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1190 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 92408500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 92408500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 2272 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 2272 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.523768 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.523768 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 77654.201681 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 77654.201681 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1190 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1190 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 80508500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 80508500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.523768 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.523768 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 67654.201681 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 67654.201681 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 132 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 132 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 337 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 337 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 27158000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 27158000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 469 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 469 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.718550 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.718550 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80587.537092 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80587.537092 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 337 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 337 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 23788000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 23788000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.718550 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.718550 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70587.537092 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70587.537092 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 54 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 54 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 194 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 194 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 248 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 248 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.782258 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.782258 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 194 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 194 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 3710500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 3710500 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.782258 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.782258 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19126.288660 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19126.288660 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 1352.510825 # Cycle average of tags in use +system.l2.tags.total_refs 5254 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 1851 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.838466 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 54.036738 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 907.826980 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 390.647106 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.001649 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.027705 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.011922 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.041275 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 1777 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.054840 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 45435 # Number of tag accesses +system.l2.tags.data_accesses 45435 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 76160 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 33216 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 109376 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 76160 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 76160 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1190 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 519 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1709 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 290549511 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 126718652 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 417268163 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 290549511 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 290549511 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 290549511 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 126718652 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 417268163 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1190.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 519.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000582000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 3420 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 1709 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1709 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 148 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 17 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 197 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 203 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 15085750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 8545000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 47129500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8827.24 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27577.24 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 1344 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 78.64 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1709 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1019 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 477 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 159 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 365 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 299.660274 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 187.787436 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 307.137251 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 111 30.41% 30.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 111 30.41% 60.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 42 11.51% 72.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 31 8.49% 80.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 3.29% 84.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 2.19% 86.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.19% 88.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 2.19% 90.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 34 9.32% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 365 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 109376 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 109376 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 417.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 417.27 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 3.26 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 219764000 # Total gap between requests +system.mem_ctrls.avgGap 128592.16 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 76160 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 33216 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 290549510.918496549129 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 126718652.240924134851 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1190 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 519 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 31535750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 15593750 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 26500.63 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 30045.76 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 78.64 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 1156680 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 614790 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 6897240 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 64134120 # Energy for active background per rank (pJ) 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power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 1449420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 770385 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 5305020 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 86269500 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 28008000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 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(read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 197458 # number of overall hits +system.cpu.dcache.overall_hits::total 197458 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 3082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::.cpu.data 3093 # number of overall misses +system.cpu.dcache.overall_misses::total 3093 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 183074284 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 183074284 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 183074284 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 183074284 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 200238 # number of demand (read+write) accesses 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miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7139 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 331 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.567976 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::.writebacks 308 # number of writebacks +system.cpu.dcache.writebacks::total 308 # number of writebacks +system.cpu.dcache.demand_mshr_hits::.cpu.data 2155 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2155 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::.cpu.data 2155 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2155 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses::.cpu.data 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 927 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::.cpu.data 932 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 932 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 51327831 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51327831 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 51599331 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51599331 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.004629 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004629 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.004647 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004647 # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 55369.828479 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55369.828479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 55364.089056 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55364.089056 # average overall mshr miss latency +system.cpu.dcache.replacements 482 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 154147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 154147 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1849 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1849 # number of ReadReq misses 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misses +system.cpu.dcache.WriteReq_mshr_misses::total 226 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 15933495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15933495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.005141 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005141 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 70502.190265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70502.190265 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 302 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 302 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 313 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 313 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.035144 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.035144 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.015974 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.015974 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 54300 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54300 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 43 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 43 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 239 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 239 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 6803836 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 6803836 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 282 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 282 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.847518 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.847518 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 28467.933054 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 28467.933054 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 239 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 239 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 6564836 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 6564836 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.847518 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.847518 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 27467.933054 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 27467.933054 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 218 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 218 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 219000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 219000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.018018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 54750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 189000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 189000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.009009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.009009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 94500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 94500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 204 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 204 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 204 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 204 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 356.298250 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 198814 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 934 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 212.862955 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 195500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 356.298250 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.695895 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.695895 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 452 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 432 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.882812 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 402888 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 402888 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 262124000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 262124000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/tonto/stats.txt b/test_run/tonto/stats.txt new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/xalancbmk/config.ini b/test_run/xalancbmk/config.ini new file mode 100644 index 000000000..a486ae0a6 --- /dev/null +++ b/test_run/xalancbmk/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=1000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 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+type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList9.opList + +[system.cpu.fuPool.FUList9.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.icache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.icache.replacement_policy +response_latency=2 +sequential_access=false +size=32768 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.tol2bus.slave[0] + +[system.cpu.icache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.icache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.icache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.icache.tags.indexing_policy +power_model= +power_state=system.cpu.icache.tags.power_state +replacement_policy=system.cpu.icache.replacement_policy +sequential_access=false +size=32768 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.icache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=32768 + +[system.cpu.icache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +decoderFlavor=Generic +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=16842768 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=1052672 +id_aa64mmfr2_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=268435456 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +impdef_nop=false +midr=0 +pmu=Null +sve_vl_se=1 +system=system + +[system.cpu.itb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.itb.walker + +[system.cpu.itb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.itb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.itb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.itb.stage2_mmu.stage2_tlb.walker + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross -v /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/t5.xml /home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//data/ref/input/xalanc.xsl +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/483.xalancbmk//exe/Xalan_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=ref.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=2097152 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=2097152 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/xalancbmk/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/xalancbmk/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/xalancbmk/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/test_run/xalancbmk/config.json b/test_run/xalancbmk/config.json new file mode 100644 index 000000000..dc532c23e --- /dev/null +++ b/test_run/xalancbmk/config.json @@ -0,0 +1,1813 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "test_run/xalancbmk/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + 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"num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/xalancbmk/fs/proc/cpuinfo b/test_run/xalancbmk/fs/proc/cpuinfo new file mode 100644 index 000000000..e1e9e07fe --- /dev/null +++ b/test_run/xalancbmk/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 2048K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/test_run/xalancbmk/fs/proc/stat b/test_run/xalancbmk/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/test_run/xalancbmk/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/test_run/xalancbmk/fs/sys/devices/system/cpu/online b/test_run/xalancbmk/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/xalancbmk/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/xalancbmk/fs/sys/devices/system/cpu/possible b/test_run/xalancbmk/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/test_run/xalancbmk/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/test_run/xalancbmk/ref.out b/test_run/xalancbmk/ref.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_run/xalancbmk/stats.txt b/test_run/xalancbmk/stats.txt new file mode 100644 index 000000000..f6fe4674c --- /dev/null +++ b/test_run/xalancbmk/stats.txt @@ -0,0 +1,1365 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 579856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 128678 # Simulator instruction rate (inst/s) +host_mem_usage 890868 # Number of bytes of host memory used +host_op_rate 156456 # Simulator op (including micro ops) rate (op/s) +host_seconds 7.77 # Real time elapsed on the host +host_tick_rate 74613189 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1000000 # Number of instructions simulated +sim_ops 1215895 # Number of ops (including micro ops) simulated +sim_seconds 0.000580 # Number of seconds simulated +sim_ticks 579856000 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 92.857196 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 125269 # Number of BTB hits +system.cpu.branchPred.BTBLookups 134905 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 107 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 11090 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 208840 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2001 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 5384 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 3383 # Number of indirect misses. +system.cpu.branchPred.lookups 273110 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 99747 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 76380 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 95577 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 80550 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 1187 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 233 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 19143 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 3731 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 1461 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 1001 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 2431 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 1071 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 834 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 2172 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 2216 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 3513 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 1300 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 1037 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 983 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 1106 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 1086 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 299 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 406 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 255 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 39 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 17 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 2272 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 369 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 806 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 125944 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 2445 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 2345 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 11110 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 3527 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 4603 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 1906 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 928 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 2495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 3138 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 862 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 4631 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 1319 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 1155 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 1495 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 1303 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 629 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 847 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 990 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 575 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 160 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 48 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 23 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 12 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 39556 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 358 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 1467 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 22387 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 987 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 419976 # number of cc regfile reads +system.cpu.cc_regfile_writes 419014 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 7417 # The number of times a branch was mispredicted +system.cpu.commit.branches 221019 # Number of branches committed +system.cpu.commit.bw_lim_events 61414 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 571 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 143338 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 1001904 # Number of instructions committed +system.cpu.commit.committedOps 1217799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 902904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.338428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 554856 61.45% 61.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 105154 11.65% 73.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72671 8.05% 81.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36450 4.04% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25173 2.79% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23567 2.61% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17219 1.91% 92.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6400 0.71% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61414 6.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902904 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 16953 # Number of function calls committed. +system.cpu.commit.int_insts 1112699 # Number of committed integer instructions. +system.cpu.commit.loads 173888 # Number of loads committed +system.cpu.commit.membars 554 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 5 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 844574 69.35% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1323 0.11% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 95 0.01% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 1 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 2 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 21 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 22 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 20 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 55 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 173888 14.28% 83.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 197792 16.24% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1217799 # Class of committed instruction +system.cpu.commit.refs 371680 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 1107 # Number of committed Vector instructions. +system.cpu.committedInsts 1000000 # Number of Instructions Simulated +system.cpu.committedOps 1215895 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.159715 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.159715 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 374344 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 3766 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 125047 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 1416652 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 260178 # Number of cycles decode is idle +system.cpu.decode.RunCycles 263754 # Number of cycles decode is running +system.cpu.decode.SquashCycles 7605 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 14784 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 19324 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 273110 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 214136 # Number of cache lines fetched +system.cpu.fetch.Cycles 589369 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5867 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 1237549 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 165 # Number of stall cycles due to pending traps +system.cpu.fetch.SquashCycles 22604 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.235498 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 324221 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 149657 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.067115 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 925205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.614934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.765819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 597384 64.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 80324 8.68% 73.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34451 3.72% 76.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27811 3.01% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 24777 2.68% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24101 2.60% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15521 1.68% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17941 1.94% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 102895 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 925205 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 234510 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 9099 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 236093 # Number of branches executed +system.cpu.iew.exec_nop 2122 # number of nop insts executed +system.cpu.iew.exec_rate 1.139700 # Inst execution rate +system.cpu.iew.exec_refs 411841 # number of memory reference insts executed +system.cpu.iew.exec_stores 208001 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 23049 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 199610 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 629 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4062 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 215816 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1362258 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 203840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11775 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1321727 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 48124 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 7605 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 48219 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 4300 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 26 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 11458 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 25721 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 18022 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 108 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 5522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3577 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 1201356 # num instructions consuming a value +system.cpu.iew.wb_count 1299572 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.538563 # average fanout of values written-back +system.cpu.iew.wb_producers 647006 # num instructions producing a value +system.cpu.iew.wb_rate 1.120596 # insts written-back per cycle +system.cpu.iew.wb_sent 1304297 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 1618351 # number of integer regfile reads +system.cpu.int_regfile_writes 892161 # number of integer regfile writes +system.cpu.ipc 0.862281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.862281 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 32 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 915262 68.64% 68.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1337 0.10% 68.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 103 0.01% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 1 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 5 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 2 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 23 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 24 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 65 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 68.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 206702 15.50% 84.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 209919 15.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1333503 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 11914 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008934 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3953 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4390 36.85% 70.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3571 29.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 1343852 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 3602156 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1298270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1502413 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1359507 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1333503 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 629 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 144232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 58 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 86393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 925205 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.441305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.054051 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 498135 53.84% 53.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 118576 12.82% 66.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 83984 9.08% 75.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 64521 6.97% 82.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52354 5.66% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39145 4.23% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42831 4.63% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14003 1.51% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11656 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 925205 # Number of insts issued each cycle +system.cpu.iq.rate 1.149854 # Inst issue rate +system.cpu.iq.vec_alu_accesses 1533 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 3047 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 1302 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 2061 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 9744 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13227 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 199610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 215816 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 935747 # number of misc regfile reads +system.cpu.misc_regfile_writes 2172 # number of misc regfile writes +system.cpu.numCycles 1159715 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 76994 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 1229281 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 8458 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 273167 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 4162 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 2182900 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 1394927 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 1400311 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 268873 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 102227 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 7605 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 124732 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 171018 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 1710175 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 173834 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.skidInsts 98664 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 639 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 1643 # Number of vector rename lookups +system.cpu.rob.rob_reads 2201236 # The number of ROB reads +system.cpu.rob.rob_writes 2744762 # The number of ROB writes +system.cpu.timesIdled 3555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 1296 # number of vector regfile reads +system.cpu.vec_regfile_writes 152 # number of vector regfile writes +system.cpu.workload.numSyscalls 28 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 7702 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 8 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 10142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 21309 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 4080 # Transaction distribution +system.membus.trans_dist::ReadExReq 3453 # Transaction distribution +system.membus.trans_dist::ReadExResp 3453 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4080 # Transaction distribution +system.membus.trans_dist::InvalidateReq 169 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15235 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 482112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 7702 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7702 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7702 # Request fanout histogram +system.membus.reqLayer0.occupancy 9544500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 39849750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 7371 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 3884 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 5199 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1059 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 3624 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 5712 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 1659 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 172 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 172 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 16622 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 15853 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 32475 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 698240 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 586688 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 1284928 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 1 # Total snoops (count) +system.tol2bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 11167 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000716 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.026757 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 11159 99.93% 99.93% # Request fanout histogram +system.tol2bus.snoop_fanout::1 8 0.07% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 11167 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 19737500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 8012496 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 8568499 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 2643 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 818 # number of demand (read+write) hits +system.l2.demand_hits::total 3461 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 2643 # number of overall hits +system.l2.overall_hits::.cpu.data 818 # number of overall hits +system.l2.overall_hits::total 3461 # number of overall hits +system.l2.demand_misses::.cpu.inst 3068 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 4465 # number of demand (read+write) misses +system.l2.demand_misses::total 7533 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 3068 # number of overall misses +system.l2.overall_misses::.cpu.data 4465 # number of overall misses +system.l2.overall_misses::total 7533 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 244130500 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 348269000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 592399500 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 244130500 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 348269000 # number of overall miss cycles +system.l2.overall_miss_latency::total 592399500 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 5711 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 5283 # number of demand (read+write) accesses +system.l2.demand_accesses::total 10994 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 5711 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 5283 # number of overall (read+write) accesses +system.l2.overall_accesses::total 10994 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.537209 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.845164 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.685192 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.537209 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.845164 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.685192 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.demand_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 79573.174707 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 77999.776036 # average overall miss latency +system.l2.overall_avg_miss_latency::total 78640.581442 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 3068 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 4465 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 7533 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 3068 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 4465 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 7533 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 213450500 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 303619000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 517069500 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 213450500 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 303619000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 517069500 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.685192 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.845164 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.685192 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 67999.776036 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 68640.581442 # average overall mshr miss latency +system.l2.replacements 0 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 3884 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 3884 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 5196 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 5196 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 5196 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 5196 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 171 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 171 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 3453 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 3453 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 265522000 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 3624 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.952815 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 76896.032436 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 3453 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 230992000 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.952815 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 66896.032436 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 2643 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 3068 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 244130500 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 5711 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.537209 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 79573.174707 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 3068 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 213450500 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.537209 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 69573.174707 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 647 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 1012 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 82747000 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 1659 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 1659 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.610006 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.610006 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 81765.810277 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 81765.810277 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 1012 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 1012 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 72627000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 72627000 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.610006 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.610006 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 71765.810277 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 3 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 3 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 169 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 169 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 172 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.982558 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 169 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 3236000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.982558 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19147.928994 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19147.928994 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 3795.325559 # Cycle average of tags in use +system.l2.tags.total_refs 21134 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 7705 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 2.742894 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 104.826620 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1882.074184 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 1808.424755 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.003199 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.057436 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.055189 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.115824 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 7702 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::2 6364 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.235046 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 178129 # Number of tag accesses +system.l2.tags.data_accesses 178129 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 196352 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 285760 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 482112 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 196352 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 3068 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 4465 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 7533 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 338622003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 492812008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 831434011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 338622003 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 338622003 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 492812008 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 831434011 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 3068.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 4465.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000681500 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 15052 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 7533 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 7533 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 615 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 664 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 376 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 668 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 653 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 381 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 361 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 344 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 303 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 438 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 468 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 542 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 626 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.48 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 65889750 # Total ticks spent queuing +system.mem_ctrls.totBusLat 37665000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 207133500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 8746.81 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27496.81 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 6067 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.54 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 7533 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 4675 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 2113 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 553 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1463 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 328.136705 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 196.673606 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 334.671504 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 480 32.81% 32.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 368 25.15% 57.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 159 10.87% 68.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 110 7.52% 76.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 46 3.14% 79.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 53 3.62% 83.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 33 2.26% 85.37% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 19 1.30% 86.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 195 13.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1463 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 482112 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 482112 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 831.43 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 831.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 6.50 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 579750500 # Total gap between requests +system.mem_ctrls.avgGap 76961.44 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 196352 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 285760 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 338622002.704119622707 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 492812008.498661696911 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 3068 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 4465 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 87227000 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 119906500 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 28431.23 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 26854.76 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 80.54 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 3991260 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 2117610 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 24782940 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 209475570 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 46264320 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 332115060 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 572.754373 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 118055750 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 19240000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 442560250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 6475980 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 3434475 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 29002680 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 45483360.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 254494740 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 8353440 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 347244675 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 598.846395 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 18199250 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 19240000 # Time in different power states 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accesses +system.cpu.icache.demand_miss_rate::total 0.033260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.033260 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033260 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 49393.358186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49393.358186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1632 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 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latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49196.515756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 49196.515756 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49196.515756 # average overall mshr miss latency +system.cpu.icache.replacements 5199 # number of replacements +system.cpu.icache.ReadReq_hits::.cpu.inst 207011 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 207011 # number of ReadReq hits +system.cpu.icache.ReadReq_misses::.cpu.inst 7122 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7122 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_latency::.cpu.inst 351779497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351779497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses::.cpu.inst 214133 # number of ReadReq accesses(hits+misses) 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time (in ticks) in various power states +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_hits::.cpu.data 340975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 340975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::.cpu.data 341602 # number of overall hits +system.cpu.dcache.overall_hits::total 341602 # number of overall hits +system.cpu.dcache.demand_misses::.cpu.data 41857 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 41857 # number of demand (read+write) misses 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accesses +system.cpu.dcache.demand_miss_rate::total 0.109335 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::.cpu.data 0.109170 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109170 # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::.cpu.data 61350.558186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61350.558186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::.cpu.data 61341.765139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61341.765139 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32596 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3937 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 845 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 38 # number of cycles access was blocked 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latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.708463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 67960.186319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67960.186319 # average overall mshr miss latency +system.cpu.dcache.replacements 4943 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 174785 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10716 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 584602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 185501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 185501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.057768 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.057768 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 54554.124673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54554.124673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 9065 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 9065 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 1651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 91811500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 91811500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.008900 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008900 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 55609.630527 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55609.630527 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 166188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166188 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 30997 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 30997 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 1978714400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1978714400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 197185 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 197185 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.157198 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63835.674420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3652 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 273940482 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.018521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75011.084885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 627 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 633 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.009479 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 6 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 345000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 57500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 57500 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_hits::.cpu.data 2 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 2 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_misses::.cpu.data 144 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 144 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 4633914 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 4633914 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 146 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 146 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 0.986301 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.986301 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 32179.958333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 32179.958333 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 144 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 4489914 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.986301 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 31179.958333 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 570 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_misses::.cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 263000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 574 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.006969 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003484 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 48750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::.cpu.data 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 542 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 542 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 476.083078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 348169 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5455 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 63.825665 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 176500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 476.083078 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.929850 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 774617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 774617 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 579856000 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 579856000 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ---------- diff --git a/test_run/zeusmp/config.ini b/test_run/zeusmp/config.ini new file mode 100644 index 000000000..6824b89cb --- /dev/null +++ b/test_run/zeusmp/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=500000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=65536 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state +replacement_policy=system.cpu.dcache.replacement_policy +sequential_access=false +size=65536 +system=system +tag_latency=2 +warmup_percentage=0 + +[system.cpu.dcache.tags.indexing_policy] +type=SetAssociative +assoc=2 +entry_size=64 +eventq_index=0 +size=65536 + +[system.cpu.dcache.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb] +type=ArmTLB +children=stage2_mmu walker +eventq_index=0 +is_stage2=false +size=64 +sys=system +walker=system.cpu.dtb.walker + +[system.cpu.dtb.stage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dtb.stage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dtb.stage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +sys=system +walker=system.cpu.dtb.stage2_mmu.stage2_tlb.walker + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 system.cpu.fuPool.FUList9 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] 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+power_state=system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.itb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.itb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/434.zeusmp//exe/zeusmp_base.amd64-armcross +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/434.zeusmp//exe/zeusmp_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=zeusmp.stdout +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=4194304 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=4194304 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=4194304 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=test_run/zeusmp/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=test_run/zeusmp/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=test_run/zeusmp/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 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+ "" + ], + "ranks_per_channel": 2, + "qos_q_policy": "fifo", + "tRAS": 35000, + "static_frontend_latency": 10000, + "devices_per_rank": 8, + "tWTR_L": 7500, + "range": "0:536870912", + "mem_sched_policy": "frfcfs", + "IDD2P12": 0.0, + "device_rowbuffer_size": 1024, + "activation_limit": 4, + "tWTR": 7500, + "enable_dram_powerdown": false, + "qos_syncro_scheduler": false, + "path": "system.mem_ctrls", + "bank_groups_per_rank": 0, + "tPPD": 0, + "IDD2N": 0.032, + "qos_turnaround_policy": null, + "in_addr_map": true, + "tRTW": 2500, + "burst_length": 8, + "tRTP": 7500, + "eventq_index": 0, + "IDD2P02": 0.0, + "addr_mapping": "RoRaBaCoCh", + "type": "DRAMCtrl", + "IDD3P02": 0.0, + "tAAD": 1250, + "static_backend_latency": 10000, + "beats_per_clock": 2, + "conf_table_reported": true, + "tXS": 270000, + "tXP": 6000, + "IDD3N": 0.038, + "tCCD_L_WR": 0, + "kvm_map": true, + "VDD2": 0.0, + "data_clock_sync": false, + "IDD3P12": 0.0, + "IDD3N2": 0.0, + "two_cycle_activate": false, + "device_bus_width": 8, + "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/test_run/zeusmp/zeusmp.stdout b/test_run/zeusmp/zeusmp.stdout new file mode 100644 index 000000000..e69de29bb diff --git a/tsl_tage/hmmer/bombesin.out b/tsl_tage/hmmer/bombesin.out new file mode 100644 index 000000000..e69de29bb diff --git a/tsl_tage/hmmer/config.ini b/tsl_tage/hmmer/config.ini new file mode 100644 index 000000000..345941aad --- /dev/null +++ b/tsl_tage/hmmer/config.ini @@ -0,0 +1,1338 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain +cache_line_size=64 +eventq_index=0 +exit_on_work_items=false +init_param=0 +m5ops_base=0 +mem_mode=timing +mem_ranges=0:536870912 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +workload=Null +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb power_state tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cacheLoadPorts=200 +cacheStorePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=200000000 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=1280 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numPhysVecPredRegs=32 +numPhysVecRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +power_gating_on_idle=false +power_model= +power_state=system.cpu.power_state +profile=0 +progress_interval=0 +pwr_gating_latency=300 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +syscallRetryLatency=10000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wait_for_remote_gdb=false +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TAGE_SC_L_8KB +children=indirectBranchPred loop_predictor statistical_corrector tage +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +eventq_index=0 +indirectBranchPred=system.cpu.branchPred.indirectBranchPred +instShiftAmt=2 +loop_predictor=system.cpu.branchPred.loop_predictor +numThreads=1 +statistical_corrector=system.cpu.branchPred.statistical_corrector +tage=system.cpu.branchPred.tage + +[system.cpu.branchPred.indirectBranchPred] +type=SimpleIndirectPredictor +eventq_index=0 +indirectGHRBits=13 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +numThreads=1 + +[system.cpu.branchPred.loop_predictor] +type=TAGE_SC_L_LoopPredictor +eventq_index=0 +initialLoopAge=7 +initialLoopIter=0 +logLoopTableAssoc=2 +logSizeLoopPred=3 +loopTableAgeBits=4 +loopTableConfidenceBits=4 +loopTableIterBits=10 +loopTableTagBits=10 +optionalAgeReset=false +restrictAllocation=true +useDirectionBit=true +useHashing=true +useSpeculation=false +withLoopBits=7 + +[system.cpu.branchPred.statistical_corrector] +type=TAGE_SC_L_8KB_StatisticalCorrector +bwWeightInitValue=7 +bwm=16 8 +bwnb=2 +chooserConfWidth=7 +eventq_index=0 +extraWeightsWidth=6 +gm=6 3 +gnb=2 +iWeightInitValue=7 +im=8 +inb=1 +initialUpdateThresholdValue=0 +lWeightInitValue=7 +lm=6 3 +lnb=2 +logBias=7 +logBwnb=7 +logGnb=7 +logInb=7 +logLnb=7 +logSizeUp=6 +numEntriesFirstLocalHistories=64 +pUpdateThresholdWidth=8 +scCountersWidth=6 +updateThresholdWidth=12 + +[system.cpu.branchPred.tage] +type=TAGE_SC_L_TAGE_8KB +eventq_index=0 +firstLongTagTable=11 +histBufferSize=2097152 +initialTCounterValue=512 +instShiftAmt=2 +logRatioBiModalHystEntries=2 +logTagTableSize=7 +logTagTableSizes=12 +logUResetPeriod=10 +longTagsSize=12 +longTagsTageFactor=17 +maxHist=1000 +maxNumAlloc=2 +minHist=4 +nHistoryTables=30 +noSkip=false false true false true false true true true true true true true true true true true true true true true false true false true false true false true false true +numThreads=1 +numUseAltOnNa=16 +pathHistBits=27 +shortTagsSize=8 +shortTagsTageFactor=9 +speculativeHistUpdate=false +tagTableCounterBits=3 +tagTableTagWidths=0 +tagTableUBits=2 +truncatePathHist=false +useAltOnNaBits=5 + +[system.cpu.dcache] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=2 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +power_model= +power_state=system.cpu.dcache.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.cpu.dcache.replacement_policy +response_latency=2 +sequential_access=false +size=65536 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.tol2bus.slave[1] + +[system.cpu.dcache.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dcache.replacement_policy] +type=LRURP +eventq_index=0 + +[system.cpu.dcache.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.cpu.dcache.tags.indexing_policy +power_model= +power_state=system.cpu.dcache.tags.power_state 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+type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state +sys=system + +[system.cpu.dtb.stage2_mmu.stage2_tlb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.dtb.walker] +type=ArmTableWalker +children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.dtb.walker.power_state +sys=system +port=system.tol2bus.slave[3] + +[system.cpu.dtb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 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+children=power_state +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +power_model= +power_state=system.cpu.itb.walker.power_state +sys=system +port=system.tol2bus.slave[2] + +[system.cpu.itb.walker.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.cpu.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states=ON CLK_GATED OFF + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=Process +cmd=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross --fixed 0 --mean 325 --num 5000 --sd 200 --seed 0 /home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//data/ref/input/nph3.hmm +cwd=/home/min/a/bnwachuk/Final/gem5 +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/min/a/ece565/benchspec-2020/CPU2006/456.hmmer//exe/hmmer_base.amd64-armcross +gid=100 +input=cin +kvmInSE=false +maxStackSize=67108864 +output=bombesin.out +pgid=100 +pid=100 +ppid=0 +release=5.1.0 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu_voltage_domain + +[system.cpu_voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2] +type=Cache +children=power_state replacement_policy tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +compressor=Null +data_latency=20 +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +power_model= +power_state=system.l2.power_state +prefetch_on_access=false +prefetcher=Null +replacement_policy=system.l2.replacement_policy +response_latency=20 +sequential_access=false +size=4194304 +system=system +tag_latency=20 +tags=system.l2.tags +tgts_per_mshr=12 +warmup_percentage=0 +write_allocator=Null +write_buffers=8 +writeback_clean=false +cpu_side=system.tol2bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.l2.replacement_policy] +type=LRURP +eventq_index=0 + +[system.l2.tags] +type=BaseSetAssoc +children=indexing_policy power_state +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +entry_size=64 +eventq_index=0 +indexing_policy=system.l2.tags.indexing_policy +power_model= +power_state=system.l2.tags.power_state +replacement_policy=system.l2.replacement_policy +sequential_access=false +size=4194304 +system=system +tag_latency=20 +warmup_percentage=0 + +[system.l2.tags.indexing_policy] +type=SetAssociative +assoc=8 +entry_size=64 +eventq_index=0 +size=4194304 + +[system.l2.tags.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.mem_ctrls] +type=DRAMCtrl +children=power_state +IDD0=0.055 +IDD02=0.0 +IDD2N=0.032 +IDD2N2=0.0 +IDD2P0=0.0 +IDD2P02=0.0 +IDD2P1=0.032 +IDD2P12=0.0 +IDD3N=0.038 +IDD3N2=0.0 +IDD3P0=0.0 +IDD3P02=0.0 +IDD3P1=0.038 +IDD3P12=0.0 +IDD4R=0.157 +IDD4R2=0.0 +IDD4W=0.125 +IDD4W2=0.0 +IDD5=0.235 +IDD52=0.0 +IDD6=0.02 +IDD62=0.0 +VDD=1.5 +VDD2=0.0 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +beats_per_clock=2 +burst_length=8 +clk_domain=system.clk_domain +conf_table_reported=true +data_clock_sync=false +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +enable_dram_powerdown=false +eventq_index=0 +image_file= +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +power_model= +power_state=system.mem_ctrls.power_state +qos_masters= +qos_policy=Null +qos_priorities=1 +qos_priority_escalation=false +qos_q_policy=fifo +qos_syncro_scheduler=false +qos_turnaround_policy=Null +range=0:536870912 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tAAD=1250 +tBURST=5000 +tBURST_MAX=5000 +tBURST_MIN=5000 +tCCD_L=0 +tCCD_L_WR=0 +tCK=1250 +tCL=13750 +tCS=2500 +tPPD=0 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tWTR_L=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +two_cycle_activate=false +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.mem_ctrls.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=true +point_of_unification=true +power_model= +power_state=system.membus.power_state +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrls.port +slave=system.system_port system.l2.mem_side + +[system.membus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.redirect_paths0] +type=RedirectPath +app_path=/proc +eventq_index=0 +host_paths=tsl_tage/hmmer/fs/proc + +[system.redirect_paths1] +type=RedirectPath +app_path=/sys +eventq_index=0 +host_paths=tsl_tage/hmmer/fs/sys + +[system.redirect_paths2] +type=RedirectPath +app_path=/tmp +eventq_index=0 +host_paths=tsl_tage/hmmer/fs/tmp + +[system.tol2bus] +type=CoherentXBar +children=power_state snoop_filter +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +max_outstanding_snoops=512 +max_routing_table_size=512 +point_of_coherency=false +point_of_unification=true +power_model= +power_state=system.tol2bus.power_state +response_latency=1 +snoop_filter=system.tol2bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.tol2bus.power_state] +type=PowerState +clk_gate_bins=20 +clk_gate_max=1000000000000 +clk_gate_min=1000 +default_state=UNDEFINED +eventq_index=0 +leaders= +possible_states= + +[system.tol2bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.0 + diff --git a/tsl_tage/hmmer/config.json b/tsl_tage/hmmer/config.json new file mode 100644 index 000000000..b89b82d4f --- /dev/null +++ b/tsl_tage/hmmer/config.json @@ -0,0 +1,1821 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "max_routing_table_size": 512, + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "max_outstanding_snoops": 512, + "point_of_unification": true, + "width": 16, + "master": { + "peer": [ + "system.mem_ctrls.port" + ], + "is_source": "True", + "role": "GEM5 REQUESTER" + }, + "power_state": { + "default_state": "UNDEFINED", + "name": "power_state", + "possible_states": [], + "clk_gate_min": 1000, + "clk_gate_bins": 20, + "eventq_index": 0, + "clk_gate_max": 1000000000000, + "cxx_class": "PowerState", + "path": "system.membus.power_state", + "type": "PowerState", + "leaders": [] + }, + "eventq_index": 0, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.l2.mem_side" + ], + "is_source": "False", + "role": "GEM5 RESPONDER" + }, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": [], + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "use_default_range": false + }, + "mmap_using_noreserve": false, + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + 1.0 + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "redirect_paths": [ + { + "app_path": "/proc", + "name": "redirect_paths0", + "host_paths": [ + "tsl_tage/hmmer/fs/proc" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths0", + "type": "RedirectPath" + }, + { + "app_path": "/sys", + "name": "redirect_paths1", + "host_paths": [ + "tsl_tage/hmmer/fs/sys" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths1", + "type": "RedirectPath" + }, + { + "app_path": "/tmp", + "name": "redirect_paths2", + "host_paths": [ + "tsl_tage/hmmer/fs/tmp" + ], + "eventq_index": 0, + "cxx_class": "RedirectPath", + "path": "system.redirect_paths2", + "type": "RedirectPath" + } + ], + "symbolfile": "", + "thermal_components": [], + "thermal_model": null, + "cxx_class": "System", + "work_begin_exit_count": 0, + "work_end_ckpt_count": 0, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:536870912" + ], + "exit_on_work_items": false, + "eventq_index": 0, + "m5ops_base": 0, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "cache_line_size": 64, + "workload": null, + "work_cpus_ckpt_count": 0, + "readfile": "", + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + 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+ "cxx_class": "DRAMCtrl", + "null": false, + "tRRD_L": 0, + "tRRD": 6000, + "clk_domain": "system.clk_domain", + "IDD6": 0.02, + "IDD5": 0.23500000000000001, + "tRCD": 13750, + "IDD0": 0.055, + "min_writes_per_switch": 16, + "IDD02": 0.0, + "page_policy": "open_adaptive", + "read_buffer_size": 32, + "IDD4R2": 0.0, + "tXSDLL": 0, + "tRP": 13750 + } + ], + "num_work_ids": 16, + "work_item_id": -1, + "work_begin_cpu_id_exit": -1 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff --git a/tsl_tage/hmmer/fs/proc/cpuinfo b/tsl_tage/hmmer/fs/proc/cpuinfo new file mode 100644 index 000000000..e0e43ef09 --- /dev/null +++ b/tsl_tage/hmmer/fs/proc/cpuinfo @@ -0,0 +1,19 @@ +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping : 0 +cpu MHz : 2000.000 +cache size: : 4096K +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + diff --git a/tsl_tage/hmmer/fs/proc/stat b/tsl_tage/hmmer/fs/proc/stat new file mode 100644 index 000000000..455c3a5b7 --- /dev/null +++ b/tsl_tage/hmmer/fs/proc/stat @@ -0,0 +1,2 @@ +cpu 0 0 0 0 0 0 0 +cpu0 0 0 0 0 0 0 0 diff --git a/tsl_tage/hmmer/fs/sys/devices/system/cpu/online b/tsl_tage/hmmer/fs/sys/devices/system/cpu/online new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/tsl_tage/hmmer/fs/sys/devices/system/cpu/online @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/tsl_tage/hmmer/fs/sys/devices/system/cpu/possible b/tsl_tage/hmmer/fs/sys/devices/system/cpu/possible new file mode 100644 index 000000000..a63547adf --- /dev/null +++ b/tsl_tage/hmmer/fs/sys/devices/system/cpu/possible @@ -0,0 +1 @@ +0-0 \ No newline at end of file diff --git a/tsl_tage/hmmer/stats.txt b/tsl_tage/hmmer/stats.txt new file mode 100644 index 000000000..61df82b8e --- /dev/null +++ b/tsl_tage/hmmer/stats.txt @@ -0,0 +1,1345 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 36089976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 186515 # Simulator instruction rate (inst/s) +host_mem_usage 870772 # Number of bytes of host memory used +host_op_rate 188480 # Simulator op (including micro ops) rate (op/s) +host_seconds 1072.30 # Real time elapsed on the host +host_tick_rate 33656638 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 200000001 # Number of instructions simulated +sim_ops 202106988 # Number of ops (including micro ops) simulated +sim_seconds 0.036090 # Number of seconds simulated +sim_ticks 36089976500 # Number of ticks simulated +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.947162 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 7167119 # Number of BTB hits +system.cpu.branchPred.BTBLookups 7170908 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 88998 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 10751462 # Number of conditional branches predicted +system.cpu.branchPred.indirectHits 2366 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 3169 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectMisses 803 # Number of indirect misses. +system.cpu.branchPred.lookups 11355627 # Number of BP lookups +system.cpu.branchPred.loop_predictor.loopPredictorCorrect 7662436 # Number of times the loop predictor is the provider and the prediction is correct +system.cpu.branchPred.loop_predictor.loopPredictorWrong 2330750 # Number of times the loop predictor is the provider and the prediction is wrong +system.cpu.branchPred.statistical_corrector.scPredictorCorrect 3695053 # Number of time the SC predictor is the provider and the prediction is correct +system.cpu.branchPred.statistical_corrector.scPredictorWrong 6298133 # Number of time the SC predictor is the provider and the prediction is wrong +system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 835 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct +system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 216 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageAltMatchProvider::0 373284 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::1 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::2 31104 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::3 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::4 20514 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::5 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::6 37680 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::7 1474653 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::8 124402 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::9 670980 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::10 552342 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::11 68411 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::12 135895 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::13 91586 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::14 510497 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::15 360999 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::16 220435 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::17 98683 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::18 186098 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::19 189248 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::20 171186 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::21 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::22 100164 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::23 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::24 424741 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::25 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::26 536681 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::27 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::28 216856 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::29 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProvider::30 0 # TAGE provider for alt match +system.cpu.branchPred.tage.tageAltMatchProviderCorrect 27675 # Number of times TAGE Alt Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageAltMatchProviderWouldHaveHit 4843 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct +system.cpu.branchPred.tage.tageAltMatchProviderWrong 8702 # Number of times TAGE Alt Match is the provider and the prediction is wrong +system.cpu.branchPred.tage.tageBimodalProviderCorrect 1153124 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct +system.cpu.branchPred.tage.tageBimodalProviderWrong 1729 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong +system.cpu.branchPred.tage.tageLongestMatchProvider::0 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::1 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::2 13960 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::3 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::4 11922 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::5 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::6 17402 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::7 78825 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::8 143315 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::9 858337 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::10 680797 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::11 36663 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::12 198697 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::13 123137 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::14 382900 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::15 262380 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::16 243816 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::17 55633 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::18 126451 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::19 313510 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::20 170225 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::21 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::22 162822 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::23 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::24 501118 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::25 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::26 876651 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::27 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::28 820780 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::29 0 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProvider::30 517098 # TAGE provider for longest match +system.cpu.branchPred.tage.tageLongestMatchProviderCorrect 6512265 # Number of times TAGE Longest Match is the provider and the prediction is correct +system.cpu.branchPred.tage.tageLongestMatchProviderWouldHaveHit 5409 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct +system.cpu.branchPred.tage.tageLongestMatchProviderWrong 47797 # Number of times TAGE Longest Match is the provider and the prediction is wrong +system.cpu.branchPred.usedRAS 230755 # Number of times the RAS was used to get a target. +system.cpu.branchPredindirectMispredicted 183 # Number of mispredicted indirect branches. +system.cpu.cc_regfile_reads 104929599 # number of cc regfile reads +system.cpu.cc_regfile_writes 105047235 # number of cc regfile writes +system.cpu.commit.amos 0 # Number of atomic instructions committed +system.cpu.commit.branchMispredicts 88112 # The number of times a branch was mispredicted +system.cpu.commit.branches 10507134 # Number of branches committed +system.cpu.commit.bw_lim_events 17176338 # number cycles where commit BW limit reached +system.cpu.commit.commitNonSpecStalls 1984 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 3289513 # The number of squashed insts skipped by commit +system.cpu.commit.committedInsts 200016288 # Number of instructions committed +system.cpu.commit.committedOps 202123275 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::samples 71607414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.822658 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.175208 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21356801 29.82% 29.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 20011266 27.95% 57.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3204482 4.48% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4532399 6.33% 68.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3345787 4.67% 73.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1073292 1.50% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 403807 0.56% 75.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 503242 0.70% 76.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17176338 23.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71607414 # Number of insts commited each cycle +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 193664 # Number of function calls committed. +system.cpu.commit.int_insts 190952818 # Number of committed integer instructions. +system.cpu.commit.loads 55733241 # Number of loads committed +system.cpu.commit.membars 1940 # Number of memory barriers committed +system.cpu.commit.op_class_0::No_OpClass 19966 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 114381638 56.59% 56.60% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 128915 0.06% 56.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 23 0.00% 56.66% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 270712 0.13% 56.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 145592 0.07% 56.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 220531 0.11% 56.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 170794 0.08% 57.06% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 395597 0.20% 57.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 78776 0.04% 57.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 248538 0.12% 57.42% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.42% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 53772 0.03% 57.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 117669 0.06% 57.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 70988 0.04% 57.54% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 19364 0.01% 57.55% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 76290 0.04% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdDiv 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAes 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 57.59% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 55733241 27.57% 85.16% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 29990869 14.84% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 202123275 # Class of committed instruction +system.cpu.commit.refs 85724110 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.vec_insts 2608681 # Number of committed Vector instructions. +system.cpu.committedInsts 200000001 # Number of Instructions Simulated +system.cpu.committedOps 202106988 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.360900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.360900 # CPI: Total CPI of All Threads +system.cpu.decode.BlockedCycles 22051629 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 896 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 7092214 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 206527606 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 17195800 # Number of cycles decode is idle +system.cpu.decode.RunCycles 29545714 # Number of cycles decode is running +system.cpu.decode.SquashCycles 90772 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 3507 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 3196412 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 18 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.fetch.Branches 11355627 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 21526476 # Number of cache lines fetched +system.cpu.fetch.Cycles 50386868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 22253 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR +system.cpu.fetch.Insts 205070425 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 183316 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.157324 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 21601711 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7400240 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.841099 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 72080327 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.877729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.513262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 36643512 50.84% 50.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3295402 4.57% 55.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6290724 8.73% 64.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 808455 1.12% 65.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 402476 0.56% 65.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 753853 1.05% 66.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3502752 4.86% 71.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 335487 0.47% 72.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 20047666 27.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 72080327 # Number of instructions fetched each cycle (Total) +system.cpu.idleCycles 99627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 141781 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 10807212 # Number of branches executed +system.cpu.iew.exec_nop 18672 # number of nop insts executed +system.cpu.iew.exec_rate 2.839652 # Inst execution rate +system.cpu.iew.exec_refs 87169360 # number of memory reference insts executed +system.cpu.iew.exec_stores 30066608 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 1266788 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 56378378 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2052 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 23155 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 30306787 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 205413459 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 57102752 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 171746 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 204965928 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 175002 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 1313934 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 90772 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1536610 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 108471 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3154341 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 2413 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 37699 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 645135 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 315918 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2413 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 34609 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 107172 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 293850184 # num instructions consuming a value +system.cpu.iew.wb_count 203893357 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.536373 # average fanout of values written-back +system.cpu.iew.wb_producers 157613296 # num instructions producing a value +system.cpu.iew.wb_rate 2.824792 # insts written-back per cycle +system.cpu.iew.wb_sent 203966119 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 397302264 # number of integer regfile reads +system.cpu.int_regfile_writes 160715019 # number of integer regfile writes +system.cpu.ipc 2.770852 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.770852 # IPC: Total IPC of All Threads +system.cpu.iq.FU_type_0::No_OpClass 24035 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 115612356 56.36% 56.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 136529 0.07% 56.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 30 0.00% 56.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 345878 0.17% 56.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 203142 0.10% 56.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 223462 0.11% 56.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 171301 0.08% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 396851 0.19% 57.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 81447 0.04% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 254171 0.12% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 64719 0.03% 57.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 148128 0.07% 57.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 85596 0.04% 57.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 21498 0.01% 57.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 89897 0.04% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAes 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 57176884 27.87% 85.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 30101752 14.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 205137676 # Type of FU issued +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 1503942 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007331 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61436 4.08% 4.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 13 0.00% 4.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 14554 0.97% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 19027 1.27% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 51484 3.42% 9.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 69957 4.65% 14.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 2929 0.19% 14.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 52847 3.51% 18.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 17081 1.14% 19.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 16090 1.07% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdDiv 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAes 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAesMix 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 20.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1035264 68.84% 89.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 163260 10.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.int_alu_accesses 203405933 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 477648664 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 200926162 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 204964058 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 205392735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 205137676 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2052 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3287786 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 13217 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 68 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3436609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 72080327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.845959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.991143 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10904673 15.13% 15.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10977244 15.23% 30.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11017565 15.29% 45.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10473086 14.53% 60.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12587063 17.46% 77.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9948970 13.80% 91.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3293340 4.57% 96.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2174186 3.02% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 704200 0.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72080327 # Number of insts issued each cycle +system.cpu.iq.rate 2.842031 # Inst issue rate +system.cpu.iq.vec_alu_accesses 3211650 # Number of vector alu accesses +system.cpu.iq.vec_inst_queue_reads 6224172 # Number of vector instruction queue reads +system.cpu.iq.vec_inst_queue_wakeup_accesses 2967195 # Number of vector instruction queue wakeup accesses +system.cpu.iq.vec_inst_queue_writes 3720919 # Number of vector instruction queue writes +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 18 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.memDep0.conflictingLoads 5523360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12375973 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 56378378 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30306787 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 129217150 # number of misc regfile reads +system.cpu.misc_regfile_writes 1323223 # number of misc regfile writes +system.cpu.numCycles 72179954 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.rename.BlockCycles 3313997 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 267567844 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 1742789 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 18466761 # Number of cycles rename is idle +system.cpu.rename.LQFullEvents 9400795 # Number of times rename has blocked due to LQ full +system.cpu.rename.ROBFullEvents 43601 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenameLookups 516328822 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 206098987 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 272226663 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 31391866 # Number of cycles rename is running +system.cpu.rename.SQFullEvents 7062926 # Number of times rename has blocked due to SQ full +system.cpu.rename.SquashCycles 90772 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 18438533 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 4658792 # Number of HB maps that are undone due to squashing +system.cpu.rename.int_rename_lookups 398342859 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 378398 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 31410 # count of serializing insts renamed +system.cpu.rename.skidInsts 17013853 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 2062 # count of temporary serializing insts renamed +system.cpu.rename.vec_rename_lookups 4206929 # Number of vector rename lookups +system.cpu.rob.rob_reads 259838560 # The number of ROB reads +system.cpu.rob.rob_writes 411298961 # The number of ROB writes +system.cpu.timesIdled 925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.vec_regfile_reads 3817339 # number of vector regfile reads +system.cpu.vec_regfile_writes 2703158 # number of vector regfile writes +system.cpu.workload.numSyscalls 43 # Number of system calls +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 55588 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.tol2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.tol2bus.snoop_filter.hit_single_requests 1438952 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.hit_single_snoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.tol2bus.snoop_filter.tot_requests 2879801 # Total number of requests made to the snoop filter. +system.tol2bus.snoop_filter.tot_snoops 1 # Total number of snoops made to the snoop filter. +system.membus.trans_dist::ReadResp 1806 # Transaction distribution +system.membus.trans_dist::CleanEvict 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 53760 # Transaction distribution +system.membus.trans_dist::ReadExResp 53760 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1806 # Transaction distribution +system.membus.trans_dist::InvalidateReq 20 # Transaction distribution +system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port 111154 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 111154 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port 3556224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 3556224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 55586 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 55586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 55586 # Request fanout histogram +system.membus.reqLayer0.occupancy 68997000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 294744000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.tol2bus.trans_dist::ReadResp 659026 # Transaction distribution +system.tol2bus.trans_dist::WritebackDirty 1437242 # Transaction distribution +system.tol2bus.trans_dist::WritebackClean 514 # Transaction distribution +system.tol2bus.trans_dist::CleanEvict 1199 # Transaction distribution +system.tol2bus.trans_dist::ReadExReq 781629 # Transaction distribution +system.tol2bus.trans_dist::ReadExResp 781629 # Transaction distribution +system.tol2bus.trans_dist::ReadCleanReq 1387 # Transaction distribution +system.tol2bus.trans_dist::ReadSharedReq 657639 # Transaction distribution +system.tol2bus.trans_dist::InvalidateReq 194 # Transaction distribution +system.tol2bus.trans_dist::InvalidateResp 194 # Transaction distribution +system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side 3288 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side 4317362 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_count::total 4320650 # Packet count per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side 121664 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side 184096640 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.pkt_size::total 184218304 # Cumulative packet size per connected master and slave (bytes) +system.tol2bus.snoops 3 # Total snoops (count) +system.tol2bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.tol2bus.snoop_fanout::samples 1440852 # Request fanout histogram +system.tol2bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.tol2bus.snoop_fanout::stdev 0.001178 # Request fanout histogram +system.tol2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.tol2bus.snoop_fanout::0 1440850 100.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.tol2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.tol2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.tol2bus.snoop_fanout::total 1440852 # Request fanout histogram +system.tol2bus.reqLayer0.occupancy 2877656500 # Layer occupancy (ticks) +system.tol2bus.reqLayer0.utilization 8.0 # Layer utilization (%) +system.tol2bus.respLayer1.occupancy 2158999000 # Layer occupancy (ticks) +system.tol2bus.respLayer1.utilization 6.0 # Layer utilization (%) +system.tol2bus.respLayer0.occupancy 2080999 # Layer occupancy (ticks) +system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.l2.demand_hits::.cpu.inst 114 # number of demand (read+write) hits +system.l2.demand_hits::.cpu.data 1384975 # number of demand (read+write) hits +system.l2.demand_hits::total 1385089 # number of demand (read+write) hits +system.l2.overall_hits::.cpu.inst 114 # number of overall hits +system.l2.overall_hits::.cpu.data 1384975 # number of overall hits +system.l2.overall_hits::total 1385089 # number of overall hits +system.l2.demand_misses::.cpu.inst 1273 # number of demand (read+write) misses +system.l2.demand_misses::.cpu.data 54293 # number of demand (read+write) misses +system.l2.demand_misses::total 55566 # number of demand (read+write) misses +system.l2.overall_misses::.cpu.inst 1273 # number of overall misses +system.l2.overall_misses::.cpu.data 54293 # number of overall misses +system.l2.overall_misses::total 55566 # number of overall misses +system.l2.demand_miss_latency::.cpu.inst 100231000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::.cpu.data 4951821000 # number of demand (read+write) miss cycles +system.l2.demand_miss_latency::total 5052052000 # number of demand (read+write) miss cycles +system.l2.overall_miss_latency::.cpu.inst 100231000 # number of overall miss cycles +system.l2.overall_miss_latency::.cpu.data 4951821000 # number of overall miss cycles +system.l2.overall_miss_latency::total 5052052000 # number of overall miss cycles +system.l2.demand_accesses::.cpu.inst 1387 # number of demand (read+write) accesses +system.l2.demand_accesses::.cpu.data 1439268 # number of demand (read+write) accesses +system.l2.demand_accesses::total 1440655 # number of demand (read+write) accesses +system.l2.overall_accesses::.cpu.inst 1387 # number of overall (read+write) accesses +system.l2.overall_accesses::.cpu.data 1439268 # number of overall (read+write) accesses +system.l2.overall_accesses::total 1440655 # number of overall (read+write) accesses +system.l2.demand_miss_rate::.cpu.inst 0.917808 # miss rate for demand accesses +system.l2.demand_miss_rate::.cpu.data 0.037723 # miss rate for demand accesses +system.l2.demand_miss_rate::total 0.038570 # miss rate for demand accesses +system.l2.overall_miss_rate::.cpu.inst 0.917808 # miss rate for overall accesses +system.l2.overall_miss_rate::.cpu.data 0.037723 # miss rate for overall accesses +system.l2.overall_miss_rate::total 0.038570 # miss rate for overall accesses +system.l2.demand_avg_miss_latency::.cpu.inst 78736.056559 # average overall miss latency +system.l2.demand_avg_miss_latency::.cpu.data 91205.514523 # average overall miss latency +system.l2.demand_avg_miss_latency::total 90919.843070 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.inst 78736.056559 # average overall miss latency +system.l2.overall_avg_miss_latency::.cpu.data 91205.514523 # average overall miss latency +system.l2.overall_avg_miss_latency::total 90919.843070 # average overall miss latency +system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2.blocked::no_targets 0 # number of cycles access was blocked +system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2.demand_mshr_misses::.cpu.inst 1273 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::.cpu.data 54293 # number of demand (read+write) MSHR misses +system.l2.demand_mshr_misses::total 55566 # number of demand (read+write) MSHR misses +system.l2.overall_mshr_misses::.cpu.inst 1273 # number of overall MSHR misses +system.l2.overall_mshr_misses::.cpu.data 54293 # number of overall MSHR misses +system.l2.overall_mshr_misses::total 55566 # number of overall MSHR misses +system.l2.demand_mshr_miss_latency::.cpu.inst 87501000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::.cpu.data 4408891000 # number of demand (read+write) MSHR miss cycles +system.l2.demand_mshr_miss_latency::total 4496392000 # number of demand (read+write) MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.inst 87501000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::.cpu.data 4408891000 # number of overall MSHR miss cycles +system.l2.overall_mshr_miss_latency::total 4496392000 # number of overall MSHR miss cycles +system.l2.demand_mshr_miss_rate::.cpu.inst 0.917808 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::.cpu.data 0.037723 # mshr miss rate for demand accesses +system.l2.demand_mshr_miss_rate::total 0.038570 # mshr miss rate for demand accesses +system.l2.overall_mshr_miss_rate::.cpu.inst 0.917808 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::.cpu.data 0.037723 # mshr miss rate for overall accesses +system.l2.overall_mshr_miss_rate::total 0.038570 # mshr miss rate for overall accesses +system.l2.demand_avg_mshr_miss_latency::.cpu.inst 68736.056559 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::.cpu.data 81205.514523 # average overall mshr miss latency +system.l2.demand_avg_mshr_miss_latency::total 80919.843070 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.inst 68736.056559 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::.cpu.data 81205.514523 # average overall mshr miss latency +system.l2.overall_avg_mshr_miss_latency::total 80919.843070 # average overall mshr miss latency +system.l2.replacements 3 # number of replacements +system.l2.WritebackDirty_hits::.writebacks 1437242 # number of WritebackDirty hits +system.l2.WritebackDirty_hits::total 1437242 # number of WritebackDirty hits +system.l2.WritebackDirty_accesses::.writebacks 1437242 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackDirty_accesses::total 1437242 # number of WritebackDirty accesses(hits+misses) +system.l2.WritebackClean_hits::.writebacks 513 # number of WritebackClean hits +system.l2.WritebackClean_hits::total 513 # number of WritebackClean hits +system.l2.WritebackClean_accesses::.writebacks 513 # number of WritebackClean accesses(hits+misses) +system.l2.WritebackClean_accesses::total 513 # number of WritebackClean accesses(hits+misses) +system.l2.ReadExReq_hits::.cpu.data 727869 # number of ReadExReq hits +system.l2.ReadExReq_hits::total 727869 # number of ReadExReq hits +system.l2.ReadExReq_misses::.cpu.data 53760 # number of ReadExReq misses +system.l2.ReadExReq_misses::total 53760 # number of ReadExReq misses +system.l2.ReadExReq_miss_latency::.cpu.data 4908669500 # number of ReadExReq miss cycles +system.l2.ReadExReq_miss_latency::total 4908669500 # number of ReadExReq miss cycles +system.l2.ReadExReq_accesses::.cpu.data 781629 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_accesses::total 781629 # number of ReadExReq accesses(hits+misses) +system.l2.ReadExReq_miss_rate::.cpu.data 0.068779 # miss rate for ReadExReq accesses +system.l2.ReadExReq_miss_rate::total 0.068779 # miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_miss_latency::.cpu.data 91307.096354 # average ReadExReq miss latency +system.l2.ReadExReq_avg_miss_latency::total 91307.096354 # average ReadExReq miss latency +system.l2.ReadExReq_mshr_misses::.cpu.data 53760 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_misses::total 53760 # number of ReadExReq MSHR misses +system.l2.ReadExReq_mshr_miss_latency::.cpu.data 4371069500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_latency::total 4371069500 # number of ReadExReq MSHR miss cycles +system.l2.ReadExReq_mshr_miss_rate::.cpu.data 0.068779 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_mshr_miss_rate::total 0.068779 # mshr miss rate for ReadExReq accesses +system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 81307.096354 # average ReadExReq mshr miss latency +system.l2.ReadExReq_avg_mshr_miss_latency::total 81307.096354 # average ReadExReq mshr miss latency +system.l2.ReadCleanReq_hits::.cpu.inst 114 # number of ReadCleanReq hits +system.l2.ReadCleanReq_hits::total 114 # number of ReadCleanReq hits +system.l2.ReadCleanReq_misses::.cpu.inst 1273 # number of ReadCleanReq misses +system.l2.ReadCleanReq_misses::total 1273 # number of ReadCleanReq misses +system.l2.ReadCleanReq_miss_latency::.cpu.inst 100231000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_miss_latency::total 100231000 # number of ReadCleanReq miss cycles +system.l2.ReadCleanReq_accesses::.cpu.inst 1387 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_accesses::total 1387 # number of ReadCleanReq accesses(hits+misses) +system.l2.ReadCleanReq_miss_rate::.cpu.inst 0.917808 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_miss_rate::total 0.917808 # miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 78736.056559 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_avg_miss_latency::total 78736.056559 # average ReadCleanReq miss latency +system.l2.ReadCleanReq_mshr_misses::.cpu.inst 1273 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_misses::total 1273 # number of ReadCleanReq MSHR misses +system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst 87501000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_latency::total 87501000 # number of ReadCleanReq MSHR miss cycles +system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst 0.917808 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_mshr_miss_rate::total 0.917808 # mshr miss rate for ReadCleanReq accesses +system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 68736.056559 # average ReadCleanReq mshr miss latency +system.l2.ReadCleanReq_avg_mshr_miss_latency::total 68736.056559 # average ReadCleanReq mshr miss latency +system.l2.ReadSharedReq_hits::.cpu.data 657106 # number of ReadSharedReq hits +system.l2.ReadSharedReq_hits::total 657106 # number of ReadSharedReq hits +system.l2.ReadSharedReq_misses::.cpu.data 533 # number of ReadSharedReq misses +system.l2.ReadSharedReq_misses::total 533 # number of ReadSharedReq misses +system.l2.ReadSharedReq_miss_latency::.cpu.data 43151500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_miss_latency::total 43151500 # number of ReadSharedReq miss cycles +system.l2.ReadSharedReq_accesses::.cpu.data 657639 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_accesses::total 657639 # number of ReadSharedReq accesses(hits+misses) +system.l2.ReadSharedReq_miss_rate::.cpu.data 0.000810 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_miss_rate::total 0.000810 # miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 80959.662289 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_avg_miss_latency::total 80959.662289 # average ReadSharedReq miss latency +system.l2.ReadSharedReq_mshr_misses::.cpu.data 533 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_misses::total 533 # number of ReadSharedReq MSHR misses +system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data 37821500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_latency::total 37821500 # number of ReadSharedReq MSHR miss cycles +system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data 0.000810 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_mshr_miss_rate::total 0.000810 # mshr miss rate for ReadSharedReq accesses +system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 70959.662289 # average ReadSharedReq mshr miss latency +system.l2.ReadSharedReq_avg_mshr_miss_latency::total 70959.662289 # average ReadSharedReq mshr miss latency +system.l2.InvalidateReq_hits::.cpu.data 174 # number of InvalidateReq hits +system.l2.InvalidateReq_hits::total 174 # number of InvalidateReq hits +system.l2.InvalidateReq_misses::.cpu.data 20 # number of InvalidateReq misses +system.l2.InvalidateReq_misses::total 20 # number of InvalidateReq misses +system.l2.InvalidateReq_accesses::.cpu.data 194 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_accesses::total 194 # number of InvalidateReq accesses(hits+misses) +system.l2.InvalidateReq_miss_rate::.cpu.data 0.103093 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_miss_rate::total 0.103093 # miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_misses::.cpu.data 20 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_misses::total 20 # number of InvalidateReq MSHR misses +system.l2.InvalidateReq_mshr_miss_latency::.cpu.data 381000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_latency::total 381000 # number of InvalidateReq MSHR miss cycles +system.l2.InvalidateReq_mshr_miss_rate::.cpu.data 0.103093 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_mshr_miss_rate::total 0.103093 # mshr miss rate for InvalidateReq accesses +system.l2.InvalidateReq_avg_mshr_miss_latency::.cpu.data 19050 # average InvalidateReq mshr miss latency +system.l2.InvalidateReq_avg_mshr_miss_latency::total 19050 # average InvalidateReq mshr miss latency +system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.l2.tags.tagsinuse 44805.448617 # Cycle average of tags in use +system.l2.tags.total_refs 2879780 # Total number of references to valid blocks. +system.l2.tags.sampled_refs 55760 # Sample count of references to valid blocks. +system.l2.tags.avg_refs 51.645983 # Average number of references to valid blocks. +system.l2.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. +system.l2.tags.occ_blocks::.writebacks 29.048288 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.inst 1250.937774 # Average occupied blocks per requestor +system.l2.tags.occ_blocks::.cpu.data 43525.462555 # Average occupied blocks per requestor +system.l2.tags.occ_percent::.writebacks 0.000443 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.inst 0.019088 # Average percentage of cache occupancy +system.l2.tags.occ_percent::.cpu.data 0.664146 # Average percentage of cache occupancy +system.l2.tags.occ_percent::total 0.683677 # Average percentage of cache occupancy +system.l2.tags.occ_task_id_blocks::1024 55583 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.l2.tags.age_task_id_blocks_1024::4 55581 # Occupied blocks per task id +system.l2.tags.occ_task_id_percent::1024 0.848129 # Percentage of cache occupancy per task id +system.l2.tags.tag_accesses 23094160 # Number of tag accesses +system.l2.tags.data_accesses 23094160 # Number of data accesses +system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.cpu_voltage_domain.voltage 1 # Voltage in Volts +system.mem_ctrls.bytes_read::.cpu.inst 81472 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::.cpu.data 3474752 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 3556224 # Number of bytes read from this memory +system.mem_ctrls.bytes_inst_read::.cpu.inst 81472 # Number of instructions bytes read from this memory +system.mem_ctrls.bytes_inst_read::total 81472 # Number of instructions bytes read from this memory +system.mem_ctrls.num_reads::.cpu.inst 1273 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::.cpu.data 54293 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 55566 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::.cpu.inst 2257469 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::.cpu.data 96280251 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 98537720 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::.cpu.inst 2257469 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_inst_read::total 2257469 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.inst 2257469 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::.cpu.data 96280251 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 98537720 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.avgPriority_.cpu.inst::samples 1273.00 # Average QoS priority value for accepted requests +system.mem_ctrls.avgPriority_.cpu.data::samples 54293.00 # Average QoS priority value for accepted requests +system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) +system.mem_ctrls.priorityMaxLatency 0.000000661000 # per QoS priority maximum request to response latency (s) +system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE +system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ +system.mem_ctrls.numStayReadState 114479 # Number of times bus staying in READ state +system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state +system.mem_ctrls.readReqs 55566 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 55566 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 3545 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 3373 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 3344 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3237 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 3291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 3402 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 3481 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 3562 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 3560 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 3595 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 3568 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 3478 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 3530 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 3531 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 3504 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 3565 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.avgRdQLen 1.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.totQLat 1163116500 # Total ticks spent queuing +system.mem_ctrls.totBusLat 277830000 # Total ticks spent in databus transfers +system.mem_ctrls.totMemAccLat 2204979000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.avgQLat 20932.16 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39682.16 # Average memory access latency per DRAM burst +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.readRowHits 40195 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 72.34 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 55566 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 21012 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 17959 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 16467 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 107 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 15371 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 231.359313 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 113.680515 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 338.973738 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 11126 72.38% 72.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 996 6.48% 78.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 505 3.29% 82.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 170 1.11% 83.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 145 0.94% 84.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 105 0.68% 84.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 110 0.72% 85.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 107 0.70% 86.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2107 13.71% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 15371 # Bytes accessed per row activation +system.mem_ctrls.bytesReadDRAM 3556224 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 3556224 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.avgRdBW 98.54 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 98.54 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 0.77 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 0.77 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.totGap 34060696000 # Total gap between requests +system.mem_ctrls.avgGap 612977.29 # Average gap between requests +system.mem_ctrls.masterReadBytes::.cpu.inst 81472 # Per-master bytes read from memory +system.mem_ctrls.masterReadBytes::.cpu.data 3474752 # Per-master bytes read from memory +system.mem_ctrls.masterReadRate::.cpu.inst 2257468.912455512211 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadRate::.cpu.data 96280251.110720440745 # Per-master bytes read from memory rate (Bytes/sec) +system.mem_ctrls.masterReadAccesses::.cpu.inst 1273 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadAccesses::.cpu.data 54293 # Per-master read serviced memory accesses +system.mem_ctrls.masterReadTotalLat::.cpu.inst 35124750 # Per-master read total memory access latency +system.mem_ctrls.masterReadTotalLat::.cpu.data 2169854250 # Per-master read total memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.inst 27592.11 # Per-master read average memory access latency +system.mem_ctrls.masterReadAvgLat::.cpu.data 39965.64 # Per-master read average memory access latency +system.mem_ctrls.pageHitRate 72.34 # Row buffer hit rate, read and write combined +system.mem_ctrls.rank1.actEnergy 54392520 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank1.preEnergy 28910310 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank1.readEnergy 202283340 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank1.refreshEnergy 2848856400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank1.actBackEnergy 2913169680 # Energy for active background per rank (pJ) +system.mem_ctrls.rank1.preBackEnergy 11405355840 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank1.totalEnergy 17452968090 # Total energy per rank (pJ) +system.mem_ctrls.rank1.averagePower 483.595995 # Core power per rank (mW) +system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank1.memoryStateTime::IDLE 29567066250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::REF 1205100000 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT 5317810250 # Time in different power states +system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.rank0.actEnergy 55356420 # Energy for activate commands per rank (pJ) +system.mem_ctrls.rank0.preEnergy 29422635 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.rank0.readEnergy 194457900 # Energy for read commands per rank (pJ) +system.mem_ctrls.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls.rank0.refreshEnergy 2848856400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.rank0.actBackEnergy 2853194850 # Energy for active background per rank (pJ) +system.mem_ctrls.rank0.preBackEnergy 11455860960 # Energy for precharge background per rank (pJ) +system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls.rank0.totalEnergy 17437149165 # Total energy per rank (pJ) +system.mem_ctrls.rank0.averagePower 483.157676 # Core power per rank (mW) +system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.mem_ctrls.rank0.memoryStateTime::IDLE 29688609000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::REF 1205100000 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT 5196267500 # Time in different power states +system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.icache.demand_hits::.cpu.inst 21524659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21524659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::.cpu.inst 21524659 # number of overall hits +system.cpu.icache.overall_hits::total 21524659 # number of overall hits +system.cpu.icache.demand_misses::.cpu.inst 1817 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1817 # number of demand (read+write) misses +system.cpu.icache.overall_misses::.cpu.inst 1817 # number of overall misses +system.cpu.icache.overall_misses::total 1817 # number of overall misses +system.cpu.icache.demand_miss_latency::.cpu.inst 129421498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 129421498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::.cpu.inst 129421498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 129421498 # number of overall miss cycles +system.cpu.icache.demand_accesses::.cpu.inst 21526476 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 21526476 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::.cpu.inst 21526476 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 21526476 # number of overall (read+write) accesses +system.cpu.icache.demand_miss_rate::.cpu.inst 0.000084 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::.cpu.inst 0.000084 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::.cpu.inst 71228.122179 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71228.122179 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::.cpu.inst 71228.122179 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71228.122179 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1158 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::.writebacks 514 # number of writebacks +system.cpu.icache.writebacks::total 514 # number of writebacks +system.cpu.icache.demand_mshr_hits::.cpu.inst 430 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::.cpu.inst 430 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses::.cpu.inst 1387 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1387 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::.cpu.inst 1387 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1387 # number of overall MSHR misses +system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 103539998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 103539998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 103539998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 103539998 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 74650.322999 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.322999 # average overall mshr miss latency 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0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 71228.122179 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71228.122179 # average ReadReq miss latency +system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 430 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1387 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1387 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 103539998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 103539998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000064 # mshr miss rate for ReadReq accesses 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number of overall misses +system.cpu.dcache.overall_misses::total 6142084 # number of overall misses +system.cpu.dcache.demand_miss_latency::.cpu.data 105468557467 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105468557467 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::.cpu.data 105468557467 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105468557467 # number of overall miss cycles +system.cpu.dcache.demand_accesses::.cpu.data 83068474 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 83068474 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::.cpu.data 83069688 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 83069688 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_rate::.cpu.data 0.073940 # miss rate for demand accesses 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mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19279.401423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 19279.644601 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19279.644601 # average overall mshr miss latency +system.cpu.dcache.replacements 1438438 # number of replacements +system.cpu.dcache.ReadReq_hits::.cpu.data 51206423 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51206423 # number of ReadReq hits +system.cpu.dcache.ReadReq_misses::.cpu.data 1872488 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1872488 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_latency::.cpu.data 27604964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27604964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses::.cpu.data 53078911 # number of ReadReq accesses(hits+misses) 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miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.012394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 17112.316158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17112.316158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_hits::.cpu.data 25719978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 25719978 # number of WriteReq hits +system.cpu.dcache.WriteReq_misses::.cpu.data 4269578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4269578 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_latency::.cpu.data 77863371470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77863371470 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses::.cpu.data 29989556 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 29989556 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.142369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.142369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 18236.783933 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18236.783933 # average WriteReq miss latency +system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 3487965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3487965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 781613 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 781613 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 16494535279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16494535279 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.026063 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.026063 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 21103.199766 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21103.199766 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_hits::.cpu.data 1203 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1203 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_misses::.cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_accesses::.cpu.data 1214 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1214 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.009061 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.009061 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 485000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 485000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.005766 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005766 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 69285.714286 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69285.714286 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 221997 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 31713.857143 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 214997 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 30713.857143 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::.cpu.data 1978 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1978 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 1978 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1978 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::.cpu.data 1940 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1940 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_accesses::.cpu.data 1940 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1940 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tagsinuse 1013.712480 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 78370984 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1439462 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 54.444636 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 249500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::.cpu.data 1013.712480 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::.cpu.data 0.989954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.989954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 631 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 135 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 167586674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 167586674 # Number of data accesses +system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 36089976500 # Cumulative time (in ticks) in various power states +system.cpu.power_state.pwrStateResidencyTicks::ON 36089976500 # Cumulative time (in ticks) in various power states + +---------- End Simulation Statistics ----------